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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Blame information for rev 17

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    ddrsdramsim.h
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//
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// Project:     A wishbone controlled DDR3 SDRAM memory controller.
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//
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// Purpose:     
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#ifndef DDRSDRAMSIM_H
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#define DDRSDRAMSIM_H
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#define DDR_MRSET       0
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#define DDR_REFRESH     1
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#define DDR_PRECHARGE   2
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#define DDR_ACTIVATE    3
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#define DDR_WRITE       4
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#define DDR_READ        5
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#define DDR_ZQS         6
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#define DDR_NOOP        7
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#define NBANKS          8
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#define NTIMESLOTS      32
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#define NWIDTH          2
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class   BANKINFO {
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public:
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        int             m_state;
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        unsigned        m_row, m_wcounter, m_min_time_before_precharge,
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                        m_min_time_before_activate;
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        BANKINFO(void);
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        void    tick(int cmd, unsigned addr=0);
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};
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class   BUSTIMESLOT     {
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public:
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        int     m_used, m_read, m_data, m_rtt;
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        unsigned        m_addr;
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};
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class   DDRSDRAMSIM     {
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        int             m_reset_state, m_reset_counts, m_memlen, m_busloc,
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                        m_clocks_since_refresh, m_nrefresh_issued,
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                        m_last_dqs, m_last_rtt;
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        unsigned        *m_mem;
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        BUSTIMESLOT     *m_bus;
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        int     cmd(int,int,int,int);
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public:
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        BANKINFO        m_bank[8];
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        DDRSDRAMSIM(int lglen);
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        unsigned apply(int, int,
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                        int, int, int, int,
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                        int, int, int, int,
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                        int, int, int);
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        unsigned operator()(int reset_n, int cke,
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                        int csn, int rasn, int casn, int wen,
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                        int dqs, int dm, int odt, int busoe,
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                        int addr, int ba, int data) {
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                return apply(reset_n, cke, csn, rasn, casn, wen, dqs, dm, odt,
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                        busoe, addr, ba, data);
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        }
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        unsigned &mem(unsigned addr) { return m_mem[addr]; };
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        unsigned &operator[](unsigned addr) { return mem(addr); };
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};
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#endif

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