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////////////////////////////////////////////////////////////////////////////////

//

// Filename:    pddrsim.cpp

//

// Project:     A wishbone controlled DDR3 SDRAM memory controller.

//

// Purpose:     To expand a DDR3 SDRAM controllers influence across multiple

//              clocks.  Hence, if the DDR3 SDRAM controller runs at half

//      the clock rate of the DDR3-SDRAM, this will expand it to the full

//      clock rate.

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2016, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory, run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

#include <stdio.h>

#include <stdlib.h>

#include "ddrsdramsim.h"

#include "pddrsim.h"

unsigned long PDDRSIM::operator()(int reset_n, int cke, int busoe,

                unsigned cmda, unsigned cmdb, unsigned long data) {

        int     csn, rasn, casn, wen, dqs, dm, odt, addr, ba;

        unsigned        hdata, ldata;

        unsigned long   odata;

        // if ((reset_n)&&(cke)) printf("PDDR: %08x/%08x/%016lx\n", cmda, cmdb, data);

        csn  = (cmda >> 26)&1;

        rasn = (cmda >> 25)&1;

        casn = (cmda >> 24)&1;

        wen  = (cmda >> 23)&1;

        ba   = (cmda >> 20)&0x7;        //  3 bits

        addr = (cmda >>  6)&0x3fff;     // 14 bits

        dqs  = (cmda >>  5)&0x01;       //  1 bits

        dm   = (cmda >>  1)&0x0f;       //  4 bits

        odt  = (cmda      )&0x01;       //  1 bits

        // if ((reset_n)&&(cke)) printf("PDDR: %s/%02x/%s\n", (dqs)?"DQS":"   ",dm,(odt)?"ODT":"   ");

        hdata = DDRSDRAMSIM::apply(reset_n, cke, csn, rasn, casn, wen,

                        dqs, dm, odt, busoe, addr, ba, (unsigned)(data>>32));

        csn  = (cmdb >> 26)&1;

        rasn = (cmdb >> 25)&1;

        casn = (cmdb >> 24)&1;

        wen  = (cmdb >> 23)&1;

        ba   = (cmdb >> 20)&0x7;        //  3 bits

        addr = (cmdb >>  6)&0x3fff;     // 14 bits

        dqs  = (cmdb >>  5)&0x01;       //  1 bits

        dm   = (cmdb >>  1)&0x0f;       //  4 bits

        odt  = (cmdb      )&0x01;       //  1 bits

        // if ((reset_n)&&(cke)) printf("PDDR: %s/%02x/%s\n", (dqs)?"DQS":"   ",dm,(odt)?"ODT":"   ");

        ldata = DDRSDRAMSIM::apply(reset_n, cke, csn, rasn, casn, wen,

                        dqs, dm, odt, busoe, addr, ba, (unsigned)(data&(~(-1l<<32))));

        odata = (((unsigned long)hdata)<<32)|((unsigned long)ldata);

        return odata;

}