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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbddrsdram.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Possible commands to the DDR3 memory. These consist of settings for the
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// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
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`define DDR_MRSET 4'b0000
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`define DDR_REFRESH 4'b0001
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`define DDR_PRECHARGE 4'b0010
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`define DDR_ACTIVATE 4'b0011
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`define DDR_WRITE 4'b0100
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`define DDR_READ 4'b0101
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`define DDR_ZQS 4'b0110
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`define DDR_NOOP 4'b0111
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//`define DDR_DESELECT 4'b1???
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//
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// In this controller, 24-bit commands tend to be passed around. These
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// 'commands' are bit fields. Here we specify the bits associated with
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// the bit fields.
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`define DDR_RSTDONE 24 // End the reset sequence?
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`define DDR_RSTTIMER 23 // Does this reset command take multiple clocks?
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`define DDR_RSTBIT 22 // Value to place on reset_n
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`define DDR_CKEBIT 21 // Should this reset command set CKE?
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//
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// Refresh command bit fields
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`define DDR_NEEDREFRESH 23
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`define DDR_RFTIMER 22
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`define DDR_RFBEGIN 21
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//
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`define DDR_CMDLEN 21
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`define DDR_CSBIT 20
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`define DDR_RASBIT 19
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`define DDR_CASBIT 18
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`define DDR_WEBIT 17
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`define DDR_NOPTIMER 16 // Steal this from BA bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_ADDR_BITS 14
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//
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`define BUSREG 7
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`define BUSNOW 8
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module wbddrsdram(i_clk, i_reset,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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CKRFC = 320,
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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input i_clk, i_reset;
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [25:0] i_wb_addr;
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input [31:0] i_wb_data;
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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// DDR3 RAM Controller
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output wire o_ddr_reset_n, o_ddr_cke;
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// Control outputs
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output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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output wire o_ddr_dqs;
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output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
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// Address outputs
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output reg [13:0] o_ddr_addr;
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output reg [2:0] o_ddr_ba;
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// And the data inputs and outputs
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output reg [31:0] o_ddr_data;
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input [31:0] i_ddr_data;
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reg drive_dqs;
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// The pending transaction
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reg [31:0] r_data;
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reg r_pending, r_we;
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reg [25:0] r_addr;
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reg [13:0] r_row;
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reg [2:0] r_bank;
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reg [9:0] r_col;
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reg [1:0] r_sub;
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reg r_move; // It was accepted, and can move to next stage
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// The pending transaction, one further into the pipeline. This is
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// the stage where the read/write command is actually given to the
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// interface if we haven't stalled.
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reg [31:0] s_data;
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reg s_pending, s_we; // , s_match;
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reg [25:0] s_addr;
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reg [13:0] s_row, s_nxt_row;
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reg [2:0] s_bank, s_nxt_bank;
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reg [9:0] s_col;
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reg [1:0] s_sub;
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// Can the pending transaction be satisfied with the current (ongoing)
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// transaction?
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reg m_move, m_match, m_pending, m_we;
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reg [25:0] m_addr;
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reg [13:0] m_row;
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reg [2:0] m_bank;
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reg [9:0] m_col;
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reg [1:0] m_sub;
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// Can we preload the next bank?
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reg [13:0] r_nxt_row;
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reg [2:0] r_nxt_bank;
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reg need_close_bank, need_close_this_bank,
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last_close_bank, maybe_close_next_bank,
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last_maybe_close,
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need_open_bank, last_open_bank, maybe_open_next_bank,
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last_maybe_open,
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valid_bank, last_valid_bank;
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reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd,
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maybe_close_cmd, maybe_open_cmd, rw_cmd;
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reg [1:0] rw_sub;
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reg rw_we;
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wire w_this_closing_bank, w_this_opening_bank,
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w_this_maybe_close, w_this_maybe_open,
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w_this_rw_move;
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reg last_closing_bank, last_opening_bank;
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//
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// tWTR = 7.5
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// tRRD = 7.5
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// tREFI= 7.8
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// tFAW = 45
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// tRTP = 7.5
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// tCKE = 5.625
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// tRFC = 160
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// tRP = 13.5
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// tRAS = 36
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// tRCD = 13.5
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//
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// RESET:
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// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
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// Hold cke low during this time as well
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// The clock should be free running into the chip during this time
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// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
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// ODT must be held low
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// 2. Hold cke low for another 500us, or 100,000 clocks
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// 3. Raise CKE, continue outputting a NOOP for
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// tXPR, tDLLk, and tZQInit
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// 4. Load MRS2, wait tMRD
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// 4. Load MRS3, wait tMRD
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// 4. Load MRS1, wait tMOD
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// Before using the SDRAM, we'll need to program at least 3 of the mode
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// registers, if not all 4.
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// tMOD clocks are required to program the mode registers, during which
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// time the RAM must be idle.
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//
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// NOOP: CS low, RAS, CAS, and WE high
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//
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// Reset logic should be simple, and is given as follows:
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// memory: reset_address. Each memory location provides either a "command" to
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// timer commands indicate whether or not the command during the timer is to
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// be set to idle, or whether the command is instead left as it was.
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reg reset_override, reset_ztimer, maintenance_override;
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reg [4:0] reset_address;
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd, refresh_cmd,
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maintenance_cmd;
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reg [24:0] reset_instruction;
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reg [16:0] reset_timer;
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initial reset_override = 1'b1;
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initial reset_address = 5'h0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_override <= 1'b1;
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reset_cmd <= { `DDR_NOOP, reset_instruction[16:0]};
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end else if (reset_ztimer)
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begin
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if (reset_instruction[`DDR_RSTDONE])
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reset_override <= 1'b0;
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reset_cmd <= reset_instruction[20:0];
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end
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always @(posedge i_clk)
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if (i_reset)
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o_ddr_cke <= 1'b0;
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else if ((reset_override)&&(reset_ztimer))
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o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
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initial reset_ztimer = 1'b0; // Is the timer zero?
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initial reset_timer = 17'h02;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= 17'd2;
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end else if (!reset_ztimer)
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begin
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reset_ztimer <= (reset_timer == 17'h01);
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reset_timer <= reset_timer - 17'h01;
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end else if (reset_instruction[`DDR_RSTTIMER])
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= reset_instruction[16:0];
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end
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dgisselq |
wire [16:0] w_ckXPR = CKXPR, w_ckRST = 4, w_ckRP = 3,
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w_ckRFC = CKRFC;
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always @(posedge i_clk)
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if (i_reset)
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reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
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// 1. Reset asserted (active low) for 200 us. (@200MHz)
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5'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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// 2. Reset de-asserted, wait 500 us before asserting CKE
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5'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd100_000 };
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// 3. Assert CKE, wait minimum of Reset CKE Exit time
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5'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
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// 4. Look MR2. (1CK, no TIMER)
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5'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2,
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3'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
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dgisselq |
// 3. Wait 4 clocks (tMRD)
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5'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h02 };
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dgisselq |
// 5. Set MR1
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5'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1,
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dgisselq |
1'h0, // Reserved for Future Use (RFU)
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dgisselq |
1'b0, // Qoff - output buffer enabled
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1'b1, // TDQS ... enabled
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1'b0, // RFU
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1'b0, // High order bit, Rtt_Nom (3'b011)
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1'b0, // RFU
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//
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1'b0, // Disable write-leveling
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1'b1, // Mid order bit of Rtt_Nom
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1'b0, // High order bit of Output Drvr Impedence Ctrl
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2'b0, // Additive latency = 0
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1'b1, // Low order bit of Rtt_Nom
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1'b1, // DIC set to 2'b01
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1'b1 }; // MRS1, DLL enable
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// 7. Wait another 4 clocks
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dgisselq |
5'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h02 };
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dgisselq |
// 8. Send MRS0
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5'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0,
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1'b0, // Reserved for future use
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dgisselq |
1'b0, // PPD control, (slow exit(DLL off))
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3'b1, // Write recovery for auto precharge
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1'b0, // DLL Reset (No)
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//
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1'b0, // TM mode normal
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3'b01, // High 3-bits, CAS latency (=4'b0010 = 4'd5)
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1'b0, // Read burst type = nibble sequential
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1'b0, // Low bit of cas latency
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2'b0 }; // Burst length = 8 (Fixed)
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// 9. Wait tMOD, is max(12 clocks, 15ns)
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dgisselq |
5'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h0a };
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dgisselq |
// 10. Issue a ZQCL command to start ZQ calibration, A10 is high
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dgisselq |
5'h9: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
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dgisselq |
//11.Wait for both tDLLK and tZQinit completed, both are 512 cks
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6 |
dgisselq |
5'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd512 };
|
293 |
4 |
dgisselq |
// 12. Precharge all command
|
294 |
6 |
dgisselq |
5'hb: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
|
295 |
4 |
dgisselq |
// 13. Wait for the precharge to complete
|
296 |
6 |
dgisselq |
5'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRP };
|
297 |
4 |
dgisselq |
// 14. A single Auto Refresh commands
|
298 |
6 |
dgisselq |
5'hd: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
|
299 |
4 |
dgisselq |
// 15. Wait for the auto refresh to complete
|
300 |
6 |
dgisselq |
5'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC };
|
301 |
4 |
dgisselq |
// Two Auto Refresh commands
|
302 |
2 |
dgisselq |
default:
|
303 |
5 |
dgisselq |
reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
|
304 |
2 |
dgisselq |
endcase
|
305 |
|
|
// reset_instruction <= reset_mem[reset_address];
|
306 |
|
|
|
307 |
6 |
dgisselq |
initial reset_address = 5'h0;
|
308 |
2 |
dgisselq |
always @(posedge i_clk)
|
309 |
|
|
if (i_reset)
|
310 |
6 |
dgisselq |
reset_address <= 5'h1;
|
311 |
|
|
else if ((reset_ztimer)&&(reset_override))
|
312 |
|
|
reset_address <= reset_address + 5'h1;
|
313 |
2 |
dgisselq |
//
|
314 |
|
|
// initial reset_mem =
|
315 |
|
|
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
|
316 |
|
|
// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
|
317 |
|
|
// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
|
318 |
|
|
// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
|
319 |
|
|
// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
320 |
|
|
// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
|
321 |
|
|
// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
322 |
|
|
// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
323 |
|
|
// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
324 |
|
|
// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
325 |
|
|
// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
|
326 |
|
|
// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
|
327 |
|
|
// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
328 |
|
|
// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
329 |
|
|
// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
330 |
|
|
// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
331 |
|
|
|
332 |
|
|
|
333 |
|
|
//
|
334 |
|
|
//
|
335 |
|
|
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
336 |
|
|
//
|
337 |
|
|
// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
|
338 |
|
|
//
|
339 |
|
|
//
|
340 |
|
|
//
|
341 |
3 |
dgisselq |
reg need_refresh;
|
342 |
2 |
dgisselq |
|
343 |
3 |
dgisselq |
wire w_precharge_all;
|
344 |
|
|
reg banks_are_closing, all_banks_closed;
|
345 |
6 |
dgisselq |
reg [3:0] bank_status [0:7];
|
346 |
|
|
reg [13:0] bank_address [0:7];
|
347 |
|
|
|
348 |
2 |
dgisselq |
always @(posedge i_clk)
|
349 |
|
|
begin
|
350 |
6 |
dgisselq |
bank_status[0] <= { bank_status[0][2:0], bank_status[0][0] };
|
351 |
|
|
bank_status[1] <= { bank_status[1][2:0], bank_status[1][0] };
|
352 |
|
|
bank_status[2] <= { bank_status[2][2:0], bank_status[2][0] };
|
353 |
|
|
bank_status[3] <= { bank_status[3][2:0], bank_status[3][0] };
|
354 |
|
|
bank_status[4] <= { bank_status[4][2:0], bank_status[4][0] };
|
355 |
|
|
bank_status[5] <= { bank_status[5][2:0], bank_status[5][0] };
|
356 |
|
|
bank_status[6] <= { bank_status[6][2:0], bank_status[6][0] };
|
357 |
|
|
bank_status[7] <= { bank_status[7][2:0], bank_status[7][0] };
|
358 |
|
|
all_banks_closed <= (bank_status[0][2:0] == 3'b00)
|
359 |
|
|
&&(bank_status[1][2:0] == 3'b00)
|
360 |
|
|
&&(bank_status[2][2:0] == 3'b00)
|
361 |
|
|
&&(bank_status[3][2:0] == 3'b00)
|
362 |
|
|
&&(bank_status[4][2:0] == 3'b00)
|
363 |
|
|
&&(bank_status[5][2:0] == 3'b00)
|
364 |
|
|
&&(bank_status[6][2:0] == 3'b00)
|
365 |
|
|
&&(bank_status[7][2:0] == 3'b00);
|
366 |
7 |
dgisselq |
if (reset_override)
|
367 |
2 |
dgisselq |
begin
|
368 |
6 |
dgisselq |
bank_status[0][0] <= 1'b0;
|
369 |
|
|
bank_status[1][0] <= 1'b0;
|
370 |
|
|
bank_status[2][0] <= 1'b0;
|
371 |
|
|
bank_status[3][0] <= 1'b0;
|
372 |
|
|
bank_status[4][0] <= 1'b0;
|
373 |
|
|
bank_status[5][0] <= 1'b0;
|
374 |
|
|
bank_status[6][0] <= 1'b0;
|
375 |
|
|
bank_status[7][0] <= 1'b0;
|
376 |
2 |
dgisselq |
banks_are_closing <= 1'b1;
|
377 |
7 |
dgisselq |
end else if ((need_refresh)||(w_precharge_all))
|
378 |
|
|
begin
|
379 |
|
|
bank_status[0][0] <= 1'b0;
|
380 |
|
|
bank_status[1][0] <= 1'b0;
|
381 |
|
|
bank_status[2][0] <= 1'b0;
|
382 |
|
|
bank_status[3][0] <= 1'b0;
|
383 |
|
|
bank_status[4][0] <= 1'b0;
|
384 |
|
|
bank_status[5][0] <= 1'b0;
|
385 |
|
|
bank_status[6][0] <= 1'b0;
|
386 |
|
|
bank_status[7][0] <= 1'b0;
|
387 |
|
|
banks_are_closing <= 1'b1;
|
388 |
2 |
dgisselq |
end else if (need_close_bank)
|
389 |
|
|
begin
|
390 |
6 |
dgisselq |
bank_status[close_bank_cmd[16:14]]
|
391 |
8 |
dgisselq |
<= { bank_status[close_bank_cmd[16:14]][2:0], 1'b0 };
|
392 |
6 |
dgisselq |
// bank_status[close_bank_cmd[16:14]][0] <= 1'b0;
|
393 |
2 |
dgisselq |
end else if (need_open_bank)
|
394 |
|
|
begin
|
395 |
6 |
dgisselq |
bank_status[activate_bank_cmd[16:14]]
|
396 |
|
|
<= { bank_status[activate_bank_cmd[16:14]][2:0], 1'b1 };
|
397 |
|
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
398 |
2 |
dgisselq |
all_banks_closed <= 1'b0;
|
399 |
|
|
banks_are_closing <= 1'b0;
|
400 |
6 |
dgisselq |
end else if ((valid_bank)&&(!r_move))
|
401 |
|
|
;
|
402 |
|
|
else if (maybe_close_next_bank)
|
403 |
|
|
begin
|
404 |
|
|
bank_status[maybe_close_cmd[16:14]]
|
405 |
8 |
dgisselq |
<= { bank_status[maybe_close_cmd[16:14]][2:0], 1'b0 };
|
406 |
6 |
dgisselq |
end else if (maybe_open_next_bank)
|
407 |
|
|
begin
|
408 |
|
|
bank_status[maybe_open_cmd[16:14]]
|
409 |
|
|
<= { bank_status[maybe_open_cmd[16:14]][2:0], 1'b1 };
|
410 |
|
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
411 |
|
|
all_banks_closed <= 1'b0;
|
412 |
|
|
banks_are_closing <= 1'b0;
|
413 |
2 |
dgisselq |
end
|
414 |
|
|
end
|
415 |
|
|
|
416 |
|
|
always @(posedge i_clk)
|
417 |
3 |
dgisselq |
// if (cmd[22:19] == `DDR_ACTIVATE)
|
418 |
8 |
dgisselq |
if (w_this_opening_bank)
|
419 |
5 |
dgisselq |
bank_address[activate_bank_cmd[16:14]]
|
420 |
|
|
<= activate_bank_cmd[13:0];
|
421 |
8 |
dgisselq |
else if (!w_this_maybe_open)
|
422 |
|
|
bank_address[maybe_open_cmd[16:14]]
|
423 |
|
|
<= maybe_open_cmd[13:0];
|
424 |
2 |
dgisselq |
|
425 |
|
|
//
|
426 |
|
|
//
|
427 |
|
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
428 |
|
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
429 |
|
|
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
|
430 |
|
|
//
|
431 |
|
|
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
|
432 |
|
|
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
|
433 |
|
|
// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
|
434 |
|
|
// time, no more refreshes will be needed for 6240 clocks.
|
435 |
|
|
//
|
436 |
|
|
// Let's think this through:
|
437 |
|
|
// REFRESH_COST = (n*(320)+24)/(n*1560)
|
438 |
|
|
//
|
439 |
|
|
//
|
440 |
|
|
//
|
441 |
7 |
dgisselq |
reg refresh_ztimer;
|
442 |
|
|
reg [16:0] refresh_counter;
|
443 |
|
|
reg [3:0] refresh_addr;
|
444 |
|
|
reg [23:0] refresh_instruction;
|
445 |
2 |
dgisselq |
always @(posedge i_clk)
|
446 |
7 |
dgisselq |
if (reset_override)
|
447 |
|
|
refresh_addr <= 4'hf;
|
448 |
|
|
else if (refresh_ztimer)
|
449 |
|
|
refresh_addr <= refresh_addr + 1;
|
450 |
|
|
else if (refresh_instruction[`DDR_RFBEGIN])
|
451 |
|
|
refresh_addr <= 4'h0;
|
452 |
6 |
dgisselq |
|
453 |
2 |
dgisselq |
always @(posedge i_clk)
|
454 |
7 |
dgisselq |
if (reset_override)
|
455 |
|
|
begin
|
456 |
|
|
refresh_ztimer <= 1'b1;
|
457 |
|
|
refresh_counter <= 17'd0;
|
458 |
|
|
end else if (!refresh_ztimer)
|
459 |
|
|
begin
|
460 |
|
|
refresh_ztimer <= (refresh_counter == 17'h1);
|
461 |
|
|
refresh_counter <= (refresh_counter - 17'h1);
|
462 |
|
|
end else if (refresh_instruction[`DDR_RFTIMER])
|
463 |
|
|
begin
|
464 |
|
|
refresh_ztimer <= 1'b0;
|
465 |
|
|
refresh_counter <= refresh_instruction[16:0];
|
466 |
|
|
end
|
467 |
2 |
dgisselq |
|
468 |
7 |
dgisselq |
wire [16:0] w_ckREFIn, w_ckREFRst;
|
469 |
|
|
assign w_ckREFIn[ 12: 0] = CKREFI4-5*CKRFC-2-10;
|
470 |
|
|
assign w_ckREFIn[ 16:13] = 4'h0;
|
471 |
8 |
dgisselq |
assign w_ckREFRst[12: 0] = CKRFC-2-12;
|
472 |
7 |
dgisselq |
assign w_ckREFRst[16:13] = 4'h0;
|
473 |
|
|
|
474 |
2 |
dgisselq |
always @(posedge i_clk)
|
475 |
7 |
dgisselq |
if (reset_override)
|
476 |
|
|
refresh_instruction <= { 3'h0, `DDR_NOOP, w_ckREFIn };
|
477 |
|
|
else if (refresh_ztimer)
|
478 |
|
|
refresh_cmd <= refresh_instruction[20:0];
|
479 |
2 |
dgisselq |
always @(posedge i_clk)
|
480 |
7 |
dgisselq |
if (reset_override)
|
481 |
|
|
need_refresh <= 1'b0;
|
482 |
|
|
else if (refresh_ztimer)
|
483 |
|
|
need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
|
484 |
2 |
dgisselq |
|
485 |
|
|
always @(posedge i_clk)
|
486 |
7 |
dgisselq |
if (refresh_ztimer)
|
487 |
|
|
case(refresh_addr)//NEED-RFC, HAVE-TIMER,
|
488 |
|
|
4'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFIn };
|
489 |
|
|
// 17'd10 = time to complete write, plus write recovery time
|
490 |
|
|
// minus two (cause we can't count zero or one)
|
491 |
|
|
// = WL+4+tWR-2 = 10
|
492 |
|
|
// = 5+4+3-2 = 10
|
493 |
|
|
4'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, 17'd10 };
|
494 |
|
|
4'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
|
495 |
|
|
4'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, 17'd2 };
|
496 |
|
|
4'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
497 |
|
|
4'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
498 |
|
|
4'h6: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
499 |
|
|
4'h7: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
500 |
|
|
4'h8: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
501 |
|
|
4'h9: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
502 |
|
|
4'ha: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
503 |
|
|
4'hb: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
504 |
8 |
dgisselq |
4'hc: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFRst };
|
505 |
7 |
dgisselq |
default:
|
506 |
|
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
507 |
|
|
endcase
|
508 |
2 |
dgisselq |
|
509 |
|
|
|
510 |
|
|
//
|
511 |
|
|
//
|
512 |
|
|
// Let's track: when will our bus be active? When will we be reading or
|
513 |
|
|
// writing?
|
514 |
|
|
//
|
515 |
|
|
//
|
516 |
7 |
dgisselq |
reg [`BUSNOW:0] bus_active, bus_read, bus_new;
|
517 |
|
|
reg [1:0] bus_subaddr [`BUSNOW:0];
|
518 |
3 |
dgisselq |
initial bus_active = 0;
|
519 |
2 |
dgisselq |
always @(posedge i_clk)
|
520 |
|
|
begin
|
521 |
7 |
dgisselq |
bus_active[`BUSNOW:0] <= { bus_active[(`BUSNOW-1):0], 1'b0 };
|
522 |
|
|
bus_read[`BUSNOW:0] <= { bus_read[(`BUSNOW-1):0], 1'b0 }; // Drive the d-bus?
|
523 |
9 |
dgisselq |
// Is this a new command? i.e., the start of a transaction?
|
524 |
|
|
bus_new[`BUSNOW:0] <= { bus_new[(`BUSNOW-1):0], 1'b0 };
|
525 |
3 |
dgisselq |
//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
|
526 |
2 |
dgisselq |
bus_subaddr[8] <= bus_subaddr[7];
|
527 |
|
|
bus_subaddr[7] <= bus_subaddr[6];
|
528 |
|
|
bus_subaddr[6] <= bus_subaddr[5];
|
529 |
|
|
bus_subaddr[5] <= bus_subaddr[4];
|
530 |
|
|
bus_subaddr[4] <= bus_subaddr[3];
|
531 |
|
|
bus_subaddr[3] <= bus_subaddr[2];
|
532 |
|
|
bus_subaddr[2] <= bus_subaddr[1];
|
533 |
|
|
bus_subaddr[1] <= bus_subaddr[0];
|
534 |
|
|
bus_subaddr[0] <= 2'h3;
|
535 |
7 |
dgisselq |
if (w_this_rw_move)
|
536 |
2 |
dgisselq |
begin
|
537 |
|
|
bus_active[3:0]<= 4'hf; // Once per clock
|
538 |
|
|
bus_read[3:0] <= 4'hf; // These will be reads
|
539 |
|
|
bus_subaddr[3] <= 2'h0;
|
540 |
|
|
bus_subaddr[2] <= 2'h1;
|
541 |
|
|
bus_subaddr[1] <= 2'h2;
|
542 |
9 |
dgisselq |
bus_new[{ 2'b0, rw_sub }] <= 1'b1;
|
543 |
4 |
dgisselq |
|
544 |
9 |
dgisselq |
bus_read[3:0] <= (rw_we)? 4'h0:4'hf;
|
545 |
2 |
dgisselq |
end
|
546 |
|
|
end
|
547 |
|
|
|
548 |
|
|
always @(posedge i_clk)
|
549 |
7 |
dgisselq |
drive_dqs <= (~bus_read[`BUSREG])&&(|bus_active[`BUSREG]);
|
550 |
2 |
dgisselq |
|
551 |
|
|
//
|
552 |
|
|
//
|
553 |
|
|
// Now, let's see, can we issue a read command?
|
554 |
|
|
//
|
555 |
|
|
//
|
556 |
9 |
dgisselq |
wire w_s_match;
|
557 |
|
|
assign w_s_match = (s_pending)&&(r_pending)&&(r_we == s_we)
|
558 |
|
|
&&(r_row == s_row)&&(r_bank == s_bank)
|
559 |
|
|
&&(r_col == s_col)
|
560 |
|
|
&&(r_sub > s_sub);
|
561 |
|
|
reg pipe_stall;
|
562 |
2 |
dgisselq |
always @(posedge i_clk)
|
563 |
|
|
begin
|
564 |
9 |
dgisselq |
r_pending <= (i_wb_stb)&&(~o_wb_stall)
|
565 |
|
|
||(r_pending)&&(pipe_stall);
|
566 |
|
|
if (~pipe_stall)
|
567 |
|
|
s_pending <= r_pending;
|
568 |
|
|
if (~pipe_stall)
|
569 |
2 |
dgisselq |
begin
|
570 |
9 |
dgisselq |
pipe_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
571 |
|
|
o_wb_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
572 |
|
|
end else begin // if (pipe_stall)
|
573 |
|
|
pipe_stall <= (s_pending)&&((!w_s_valid)||(valid_bank)||(r_move)||(last_valid_bank));
|
574 |
|
|
o_wb_stall <= (s_pending)&&((!w_s_valid)||(valid_bank)||(r_move)||(last_valid_bank));
|
575 |
|
|
end
|
576 |
|
|
if (need_refresh)
|
577 |
2 |
dgisselq |
o_wb_stall <= 1'b1;
|
578 |
|
|
|
579 |
9 |
dgisselq |
if (~pipe_stall)
|
580 |
2 |
dgisselq |
begin
|
581 |
|
|
r_we <= i_wb_we;
|
582 |
|
|
r_addr <= i_wb_addr;
|
583 |
|
|
r_data <= i_wb_data;
|
584 |
5 |
dgisselq |
r_row <= i_wb_addr[25:12];
|
585 |
|
|
r_bank <= i_wb_addr[11:9];
|
586 |
|
|
r_col <= { i_wb_addr[8:2], 3'b000 }; // 9:2
|
587 |
2 |
dgisselq |
r_sub <= i_wb_addr[1:0];
|
588 |
|
|
|
589 |
|
|
// pre-emptive work
|
590 |
6 |
dgisselq |
r_nxt_row <= (i_wb_addr[11:9]==3'h7)?i_wb_addr[25:12]+14'h1:i_wb_addr[25:12];
|
591 |
5 |
dgisselq |
r_nxt_bank <= i_wb_addr[11:9]+3'h1;
|
592 |
2 |
dgisselq |
end
|
593 |
9 |
dgisselq |
|
594 |
|
|
if (~pipe_stall)
|
595 |
|
|
begin
|
596 |
|
|
// Moving one down the pipeline
|
597 |
|
|
s_we <= r_we;
|
598 |
|
|
s_addr <= r_addr;
|
599 |
|
|
s_data <= r_data;
|
600 |
|
|
s_row <= r_row;
|
601 |
|
|
s_bank <= r_bank;
|
602 |
|
|
s_col <= r_col;
|
603 |
|
|
s_sub <= r_sub;
|
604 |
|
|
|
605 |
|
|
// pre-emptive work
|
606 |
|
|
s_nxt_row <= r_nxt_row;
|
607 |
|
|
s_nxt_bank <= r_nxt_bank;
|
608 |
|
|
|
609 |
10 |
dgisselq |
// s_match <= w_s_match;
|
610 |
9 |
dgisselq |
end
|
611 |
2 |
dgisselq |
end
|
612 |
|
|
|
613 |
9 |
dgisselq |
wire w_need_close_this_bank, w_need_open_bank,
|
614 |
|
|
w_r_valid, w_s_valid;
|
615 |
6 |
dgisselq |
assign w_need_close_this_bank = (r_pending)&&(bank_status[r_bank][0])
|
616 |
9 |
dgisselq |
&&(r_row != bank_address[r_bank])
|
617 |
|
|
||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][0])
|
618 |
|
|
&&(s_row != bank_address[s_bank]);
|
619 |
|
|
assign w_need_open_bank = (r_pending)&&(bank_status[r_bank][1:0]==2'b00)
|
620 |
|
|
||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][1:0]==2'b00);
|
621 |
|
|
assign w_r_valid = (!need_refresh)&&(r_pending)
|
622 |
|
|
&&(bank_status[r_bank][3])
|
623 |
|
|
&&(bank_address[r_bank]==r_row)
|
624 |
|
|
&&(!bus_active[0]);
|
625 |
|
|
assign w_s_valid = (!need_refresh)&&(s_pending)
|
626 |
|
|
&&(bank_status[s_bank][3])
|
627 |
|
|
&&(bank_address[s_bank]==s_row)
|
628 |
|
|
&&(!bus_active[0]);
|
629 |
3 |
dgisselq |
|
630 |
2 |
dgisselq |
always @(posedge i_clk)
|
631 |
|
|
begin
|
632 |
6 |
dgisselq |
need_close_bank <= (w_need_close_this_bank)
|
633 |
10 |
dgisselq |
&&(!need_open_bank)
|
634 |
|
|
&&(!need_close_bank)
|
635 |
6 |
dgisselq |
&&(!w_this_closing_bank)&&(!last_closing_bank);
|
636 |
2 |
dgisselq |
|
637 |
|
|
maybe_close_next_bank <= (r_pending)
|
638 |
6 |
dgisselq |
&&(bank_status[r_nxt_bank][0])
|
639 |
2 |
dgisselq |
&&(r_nxt_row != bank_address[r_nxt_bank])
|
640 |
6 |
dgisselq |
&&(!w_this_maybe_close)&&(!last_maybe_close);
|
641 |
2 |
dgisselq |
|
642 |
6 |
dgisselq |
close_bank_cmd <= { `DDR_PRECHARGE, r_bank, r_row[13:11], 1'b0, r_row[9:0] };
|
643 |
|
|
maybe_close_cmd <= { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[13:11], 1'b0, r_nxt_row[9:0] };
|
644 |
2 |
dgisselq |
|
645 |
|
|
|
646 |
6 |
dgisselq |
need_open_bank <= (w_need_open_bank)
|
647 |
|
|
&&(!w_this_opening_bank)&&(!last_opening_bank);
|
648 |
|
|
last_open_bank <= (w_this_opening_bank);
|
649 |
2 |
dgisselq |
|
650 |
|
|
maybe_open_next_bank <= (r_pending)
|
651 |
6 |
dgisselq |
&&(bank_status[r_bank][0] == 1'b1)
|
652 |
|
|
&&(bank_status[r_nxt_bank][1:0] == 2'b00)
|
653 |
|
|
&&(!w_this_maybe_open)&&(!last_maybe_open);
|
654 |
|
|
last_maybe_open <= (w_this_maybe_open);
|
655 |
2 |
dgisselq |
|
656 |
6 |
dgisselq |
activate_bank_cmd<= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
|
657 |
|
|
maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
|
658 |
2 |
dgisselq |
|
659 |
|
|
|
660 |
|
|
|
661 |
9 |
dgisselq |
valid_bank <= ((w_r_valid)||(pipe_stall)&&(w_s_valid))
|
662 |
|
|
&&(!last_valid_bank)&&(!r_move);
|
663 |
6 |
dgisselq |
last_valid_bank <= r_move;
|
664 |
2 |
dgisselq |
|
665 |
9 |
dgisselq |
if ((s_pending)&&(pipe_stall))
|
666 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
|
667 |
|
|
else if (r_pending)
|
668 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (r_we)?`DDR_WRITE:`DDR_READ;
|
669 |
|
|
else
|
670 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= `DDR_NOOP;
|
671 |
|
|
if ((s_pending)&&(pipe_stall))
|
672 |
|
|
rw_cmd[`DDR_WEBIT-1:0] <= { s_bank, 3'h0, 1'b0, s_col };
|
673 |
|
|
else
|
674 |
|
|
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 3'h0, 1'b0, r_col };
|
675 |
|
|
if ((s_pending)&&(pipe_stall))
|
676 |
|
|
rw_sub <= 2'b11 - s_sub;
|
677 |
|
|
else
|
678 |
|
|
rw_sub <= 2'b11 - r_sub;
|
679 |
|
|
if ((s_pending)&&(pipe_stall))
|
680 |
|
|
rw_we <= s_we;
|
681 |
|
|
else
|
682 |
|
|
rw_we <= r_we;
|
683 |
|
|
|
684 |
2 |
dgisselq |
end
|
685 |
|
|
|
686 |
|
|
//
|
687 |
|
|
//
|
688 |
|
|
// Okay, let's look at the last assignment in our chain. It should look
|
689 |
|
|
// something like:
|
690 |
|
|
always @(posedge i_clk)
|
691 |
4 |
dgisselq |
if (i_reset)
|
692 |
|
|
o_ddr_reset_n <= 1'b0;
|
693 |
|
|
else if (reset_ztimer)
|
694 |
|
|
o_ddr_reset_n <= reset_instruction[`DDR_RSTBIT];
|
695 |
2 |
dgisselq |
always @(posedge i_clk)
|
696 |
4 |
dgisselq |
if (i_reset)
|
697 |
|
|
o_ddr_cke <= 1'b0;
|
698 |
|
|
else if (reset_ztimer)
|
699 |
|
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
700 |
6 |
dgisselq |
|
701 |
9 |
dgisselq |
always @(posedge i_clk)
|
702 |
|
|
if (i_reset)
|
703 |
|
|
maintenance_override <= 1'b1;
|
704 |
|
|
else
|
705 |
|
|
maintenance_override <= (reset_override)||(need_refresh);
|
706 |
7 |
dgisselq |
|
707 |
9 |
dgisselq |
initial maintenance_cmd = { `DDR_NOOP, 17'h00 };
|
708 |
|
|
always @(posedge i_clk)
|
709 |
|
|
if (i_reset)
|
710 |
|
|
maintenance_cmd <= { `DDR_NOOP, 17'h00 };
|
711 |
|
|
else
|
712 |
|
|
maintenance_cmd <= (reset_override)?reset_cmd:refresh_cmd;
|
713 |
|
|
|
714 |
|
|
assign w_this_closing_bank = (!maintenance_override)
|
715 |
6 |
dgisselq |
&&(need_close_bank);
|
716 |
9 |
dgisselq |
assign w_this_opening_bank = (!maintenance_override)
|
717 |
6 |
dgisselq |
&&(!need_close_bank)&&(need_open_bank);
|
718 |
9 |
dgisselq |
assign w_this_rw_move = (!maintenance_override)
|
719 |
7 |
dgisselq |
&&(!need_close_bank)&&(!need_open_bank)
|
720 |
|
|
&&(valid_bank)&&(!r_move);
|
721 |
9 |
dgisselq |
assign w_this_maybe_close = (!maintenance_override)
|
722 |
6 |
dgisselq |
&&(!need_close_bank)&&(!need_open_bank)
|
723 |
|
|
&&((!valid_bank)||(r_move))
|
724 |
|
|
&&(maybe_close_next_bank);
|
725 |
9 |
dgisselq |
assign w_this_maybe_open = (!maintenance_override)
|
726 |
6 |
dgisselq |
&&(!need_close_bank)&&(!need_open_bank)
|
727 |
|
|
&&((!valid_bank)||(r_move))
|
728 |
|
|
&&(!maybe_close_next_bank)
|
729 |
|
|
&&(maybe_open_next_bank);
|
730 |
2 |
dgisselq |
always @(posedge i_clk)
|
731 |
|
|
begin
|
732 |
6 |
dgisselq |
last_opening_bank <= 1'b0;
|
733 |
|
|
last_closing_bank <= 1'b0;
|
734 |
|
|
last_maybe_open <= 1'b0;
|
735 |
|
|
last_maybe_close <= 1'b0;
|
736 |
2 |
dgisselq |
r_move <= 1'b0;
|
737 |
9 |
dgisselq |
if (maintenance_override) // Command from either reset or
|
738 |
|
|
cmd <= maintenance_cmd; // refresh logic
|
739 |
|
|
else if (need_close_bank)
|
740 |
2 |
dgisselq |
begin
|
741 |
|
|
cmd <= close_bank_cmd;
|
742 |
6 |
dgisselq |
last_closing_bank <= 1'b1;
|
743 |
|
|
end else if (need_open_bank)
|
744 |
|
|
begin
|
745 |
2 |
dgisselq |
cmd <= activate_bank_cmd;
|
746 |
6 |
dgisselq |
last_opening_bank <= 1'b1;
|
747 |
|
|
end else if ((valid_bank)&&(!r_move))
|
748 |
2 |
dgisselq |
begin
|
749 |
|
|
cmd <= rw_cmd;
|
750 |
|
|
r_move <= 1'b1;
|
751 |
6 |
dgisselq |
end else if (maybe_close_next_bank)
|
752 |
|
|
begin
|
753 |
|
|
cmd <= maybe_close_cmd;
|
754 |
|
|
last_maybe_close <= 1'b1;
|
755 |
|
|
end else if (maybe_open_next_bank)
|
756 |
|
|
begin
|
757 |
|
|
cmd <= maybe_open_cmd;
|
758 |
|
|
last_maybe_open <= 1'b1;
|
759 |
2 |
dgisselq |
end else
|
760 |
4 |
dgisselq |
cmd <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
761 |
2 |
dgisselq |
end
|
762 |
|
|
|
763 |
7 |
dgisselq |
`define LGFIFOLN 4
|
764 |
|
|
`define FIFOLEN 16
|
765 |
|
|
reg [(`LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
|
766 |
|
|
reg [31:0] bus_fifo_data [0:(`FIFOLEN-1)];
|
767 |
|
|
reg [1:0] bus_fifo_sub [0:(`FIFOLEN-1)];
|
768 |
|
|
reg bus_fifo_new [0:(`FIFOLEN-1)];
|
769 |
|
|
reg pre_ack;
|
770 |
3 |
dgisselq |
|
771 |
7 |
dgisselq |
// The bus R/W FIFO
|
772 |
|
|
wire w_bus_fifo_read_next_transaction;
|
773 |
9 |
dgisselq |
assign w_bus_fifo_read_next_transaction =
|
774 |
|
|
(bus_fifo_sub[bus_fifo_tail]==bus_subaddr[`BUSREG])
|
775 |
|
|
&&(bus_fifo_tail != bus_fifo_head)
|
776 |
|
|
&&(bus_active[`BUSREG])
|
777 |
|
|
&&(bus_new[`BUSREG] == bus_fifo_new[bus_fifo_tail]);
|
778 |
7 |
dgisselq |
always @(posedge i_clk)
|
779 |
|
|
begin
|
780 |
|
|
pre_ack <= 1'b0;
|
781 |
|
|
o_ddr_dm <= 1'b0;
|
782 |
|
|
if ((i_reset)||(reset_override))
|
783 |
|
|
begin
|
784 |
|
|
bus_fifo_head <= 4'h0;
|
785 |
|
|
bus_fifo_tail <= 4'h0;
|
786 |
|
|
o_ddr_dm <= 1'b0;
|
787 |
|
|
end else begin
|
788 |
10 |
dgisselq |
if
|
789 |
|
|
//((w_this_rw_move)||((s_pending)&&(s_match)&&(!pipe_stall)))
|
790 |
|
|
((s_pending)&&(!pipe_stall))
|
791 |
7 |
dgisselq |
bus_fifo_head <= bus_fifo_head + 4'h1;
|
792 |
|
|
|
793 |
|
|
o_ddr_dm <= (bus_active[`BUSREG])&&(!bus_read[`BUSREG]);
|
794 |
|
|
if (w_bus_fifo_read_next_transaction)
|
795 |
|
|
begin
|
796 |
|
|
bus_fifo_tail <= bus_fifo_tail + 4'h1;
|
797 |
|
|
pre_ack <= 1'b1;
|
798 |
|
|
o_ddr_dm <= 1'b0;
|
799 |
|
|
end
|
800 |
|
|
end
|
801 |
9 |
dgisselq |
bus_fifo_data[bus_fifo_head] <= s_data;
|
802 |
|
|
bus_fifo_sub[bus_fifo_head] <= s_sub;
|
803 |
7 |
dgisselq |
bus_fifo_new[bus_fifo_head] <= w_this_rw_move;
|
804 |
|
|
end
|
805 |
|
|
|
806 |
|
|
|
807 |
3 |
dgisselq |
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
|
808 |
|
|
assign o_ddr_ras_n = cmd[`DDR_RASBIT];
|
809 |
|
|
assign o_ddr_cas_n = cmd[`DDR_CASBIT];
|
810 |
|
|
assign o_ddr_we_n = cmd[`DDR_WEBIT];
|
811 |
2 |
dgisselq |
assign o_ddr_dqs = drive_dqs;
|
812 |
3 |
dgisselq |
assign o_ddr_addr = cmd[(`DDR_ADDR_BITS-1):0];
|
813 |
|
|
assign o_ddr_ba = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
|
814 |
7 |
dgisselq |
always @(posedge i_clk)
|
815 |
|
|
o_ddr_data <= bus_fifo_data[bus_fifo_tail];
|
816 |
3 |
dgisselq |
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
817 |
2 |
dgisselq |
&&(o_ddr_addr[10]); // 5 bits
|
818 |
|
|
|
819 |
|
|
// Need to set o_wb_dqs high one clock prior to any read.
|
820 |
|
|
// As per spec, ODT = 0 during reads
|
821 |
7 |
dgisselq |
assign o_ddr_bus_oe = ~bus_read[`BUSNOW];
|
822 |
2 |
dgisselq |
|
823 |
4 |
dgisselq |
// ODT must be in high impedence while reset_n=0, then it can be set
|
824 |
|
|
// to low or high.
|
825 |
|
|
assign o_ddr_odt = o_ddr_bus_oe;
|
826 |
2 |
dgisselq |
|
827 |
7 |
dgisselq |
always @(posedge i_clk)
|
828 |
|
|
o_wb_ack <= pre_ack;
|
829 |
|
|
always @(posedge i_clk)
|
830 |
|
|
o_wb_data <= i_ddr_data;
|
831 |
4 |
dgisselq |
|
832 |
2 |
dgisselq |
endmodule
|