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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbddrsdram.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Possible commands to the DDR3 memory. These consist of settings for the
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// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
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`define DDR_MRSET 4'b0000
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`define DDR_REFRESH 4'b0001
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`define DDR_PRECHARGE 4'b0010
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`define DDR_ACTIVATE 4'b0011
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`define DDR_WRITE 4'b0100
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`define DDR_READ 4'b0101
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`define DDR_ZQS 4'b0110
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`define DDR_NOOP 4'b0111
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//`define DDR_DESELECT 4'b1???
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//
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// In this controller, 24-bit commands tend to be passed around. These
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// 'commands' are bit fields. Here we specify the bits associated with
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// the bit fields.
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`define DDR_RSTDONE 24 // End the reset sequence?
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`define DDR_RSTTIMER 23 // Does this reset command take multiple clocks?
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`define DDR_RSTBIT 22 // Value to place on reset_n
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`define DDR_CKEBIT 21 // Should this reset command set CKE?
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//
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// Refresh command bit fields
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`define DDR_NEEDREFRESH 23
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`define DDR_RFTIMER 22
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`define DDR_RFBEGIN 21
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//
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`define DDR_CMDLEN 21
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`define DDR_CSBIT 20
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`define DDR_RASBIT 19
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`define DDR_CASBIT 18
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`define DDR_WEBIT 17
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`define DDR_NOPTIMER 16 // Steal this from BA bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_ADDR_BITS 14
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//
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`define BUSREG 7
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`define BUSNOW 8
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module wbddrsdram(i_clk, i_reset,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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parameter CKRBITS = 13, // Bits in CKREFI4
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CKREFI = 13'd1560, // 4 * 7.8us at 200 MHz clock
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CKRFC = 320,
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CKWR = 3,
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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input i_clk, i_reset;
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [25:0] i_wb_addr;
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input [31:0] i_wb_data;
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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// DDR3 RAM Controller
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output reg o_ddr_reset_n, o_ddr_cke;
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// Control outputs
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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output wire o_ddr_dqs;
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output reg o_ddr_dm;
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output reg o_ddr_odt;
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output wire o_ddr_bus_oe;
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// Address outputs
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output wire [13:0] o_ddr_addr;
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output wire [2:0] o_ddr_ba;
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// And the data inputs and outputs
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output reg [31:0] o_ddr_data;
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input [31:0] i_ddr_data;
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reg drive_dqs;
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// The pending transaction
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reg [31:0] r_data;
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reg r_pending, r_we;
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reg [25:0] r_addr;
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reg [13:0] r_row;
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reg [2:0] r_bank;
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reg [9:0] r_col;
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reg [1:0] r_sub;
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reg r_move; // It was accepted, and can move to next stage
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// The pending transaction, one further into the pipeline. This is
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// the stage where the read/write command is actually given to the
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// interface if we haven't stalled.
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reg [31:0] s_data;
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reg s_pending, s_we; // , s_match;
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reg [25:0] s_addr;
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reg [13:0] s_row, s_nxt_row;
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reg [2:0] s_bank, s_nxt_bank;
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reg [9:0] s_col;
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reg [1:0] s_sub;
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// Can the pending transaction be satisfied with the current (ongoing)
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// transaction?
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reg m_move, m_match, m_pending, m_we;
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reg [25:0] m_addr;
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reg [13:0] m_row;
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reg [2:0] m_bank;
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reg [9:0] m_col;
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reg [1:0] m_sub;
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// Can we preload the next bank?
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reg [13:0] r_nxt_row;
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reg [2:0] r_nxt_bank;
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reg need_close_bank, need_close_this_bank,
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last_close_bank, maybe_close_next_bank,
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last_maybe_close,
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need_open_bank, last_open_bank, maybe_open_next_bank,
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last_maybe_open,
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valid_bank, last_valid_bank;
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reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd,
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maybe_close_cmd, maybe_open_cmd, rw_cmd;
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reg [1:0] rw_sub;
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reg rw_we;
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wire w_this_closing_bank, w_this_opening_bank,
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w_this_maybe_close, w_this_maybe_open,
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w_this_rw_move;
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reg last_closing_bank, last_opening_bank;
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wire w_need_close_this_bank, w_need_open_bank,
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w_r_valid, w_s_valid, w_s_match;
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//
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// tWTR = 7.5
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// tRRD = 7.5
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// tREFI= 7.8
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// tFAW = 45
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// tRTP = 7.5
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// tCKE = 5.625
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// tRFC = 160
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// tRP = 13.5
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// tRAS = 36
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// tRCD = 13.5
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//
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// RESET:
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// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
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// Hold cke low during this time as well
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// The clock should be free running into the chip during this time
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// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
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// ODT must be held low
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// 2. Hold cke low for another 500us, or 100,000 clocks
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// 3. Raise CKE, continue outputting a NOOP for
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// tXPR, tDLLk, and tZQInit
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// 4. Load MRS2, wait tMRD
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// 4. Load MRS3, wait tMRD
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// 4. Load MRS1, wait tMOD
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// Before using the SDRAM, we'll need to program at least 3 of the mode
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// registers, if not all 4.
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// tMOD clocks are required to program the mode registers, during which
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// time the RAM must be idle.
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//
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// NOOP: CS low, RAS, CAS, and WE high
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//
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// Reset logic should be simple, and is given as follows:
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// memory: reset_address. Each memory location provides either a "command" to
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// timer commands indicate whether or not the command during the timer is to
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// be set to idle, or whether the command is instead left as it was.
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reg reset_override, reset_ztimer, maintenance_override;
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reg [4:0] reset_address;
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd, refresh_cmd,
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maintenance_cmd;
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reg [24:0] reset_instruction;
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reg [16:0] reset_timer;
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initial reset_override = 1'b1;
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initial reset_address = 5'h0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_override <= 1'b1;
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reset_cmd <= { `DDR_NOOP, reset_instruction[16:0]};
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end else if (reset_ztimer)
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begin
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if (reset_instruction[`DDR_RSTDONE])
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reset_override <= 1'b0;
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reset_cmd <= reset_instruction[20:0];
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end
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dgisselq |
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dgisselq |
initial reset_ztimer = 1'b0; // Is the timer zero?
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initial reset_timer = 17'h02;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= 17'd2;
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end else if (!reset_ztimer)
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begin
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reset_ztimer <= (reset_timer == 17'h01);
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reset_timer <= reset_timer - 17'h01;
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end else if (reset_instruction[`DDR_RSTTIMER])
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= reset_instruction[16:0];
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end
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dgisselq |
wire [16:0] w_ckXPR = CKXPR, w_ckRST = 4, w_ckRP = 3,
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w_ckRFC_first = CKRFC-2-9;
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always @(posedge i_clk)
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if (i_reset)
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reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
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dgisselq |
// 1. Reset asserted (active low) for 200 us. (@200MHz)
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5'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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// 2. Reset de-asserted, wait 500 us before asserting CKE
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5'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd100_000 };
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// 3. Assert CKE, wait minimum of Reset CKE Exit time
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5'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
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// 4. Look MR2. (1CK, no TIMER)
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5'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2,
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3'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
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dgisselq |
// 3. Wait 4 clocks (tMRD)
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5'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h02 };
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// 5. Set MR1
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5'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1,
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dgisselq |
1'h0, // Reserved for Future Use (RFU)
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dgisselq |
1'b0, // Qoff - output buffer enabled
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1'b1, // TDQS ... enabled
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1'b0, // RFU
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1'b0, // High order bit, Rtt_Nom (3'b011)
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1'b0, // RFU
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//
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1'b0, // Disable write-leveling
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1'b1, // Mid order bit of Rtt_Nom
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1'b0, // High order bit of Output Drvr Impedence Ctrl
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2'b0, // Additive latency = 0
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1'b1, // Low order bit of Rtt_Nom
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dgisselq |
1'b0, // DIC set to 2'b00
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1'b0 }; // MRS1, DLL enable
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dgisselq |
// 7. Wait another 4 clocks
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5'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h02 };
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dgisselq |
// 8. Send MRS0
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5'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0,
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dgisselq |
1'b0, // Reserved for future use
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dgisselq |
1'b0, // PPD control, (slow exit(DLL off))
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3'b1, // Write recovery for auto precharge
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1'b0, // DLL Reset (No)
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//
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1'b0, // TM mode normal
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3'b01, // High 3-bits, CAS latency (=4'b0010 = 4'd5)
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1'b0, // Read burst type = nibble sequential
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1'b0, // Low bit of cas latency
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2'b0 }; // Burst length = 8 (Fixed)
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// 9. Wait tMOD, is max(12 clocks, 15ns)
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dgisselq |
5'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h0a };
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dgisselq |
// 10. Issue a ZQCL command to start ZQ calibration, A10 is high
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6 |
dgisselq |
5'h9: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
|
292 |
4 |
dgisselq |
//11.Wait for both tDLLK and tZQinit completed, both are 512 cks
|
293 |
6 |
dgisselq |
5'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd512 };
|
294 |
4 |
dgisselq |
// 12. Precharge all command
|
295 |
6 |
dgisselq |
5'hb: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
|
296 |
4 |
dgisselq |
// 13. Wait for the precharge to complete
|
297 |
6 |
dgisselq |
5'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRP };
|
298 |
4 |
dgisselq |
// 14. A single Auto Refresh commands
|
299 |
6 |
dgisselq |
5'hd: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
|
300 |
4 |
dgisselq |
// 15. Wait for the auto refresh to complete
|
301 |
14 |
dgisselq |
5'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
|
302 |
4 |
dgisselq |
// Two Auto Refresh commands
|
303 |
2 |
dgisselq |
default:
|
304 |
5 |
dgisselq |
reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
|
305 |
2 |
dgisselq |
endcase
|
306 |
|
|
// reset_instruction <= reset_mem[reset_address];
|
307 |
|
|
|
308 |
6 |
dgisselq |
initial reset_address = 5'h0;
|
309 |
2 |
dgisselq |
always @(posedge i_clk)
|
310 |
|
|
if (i_reset)
|
311 |
6 |
dgisselq |
reset_address <= 5'h1;
|
312 |
|
|
else if ((reset_ztimer)&&(reset_override))
|
313 |
|
|
reset_address <= reset_address + 5'h1;
|
314 |
2 |
dgisselq |
//
|
315 |
|
|
// initial reset_mem =
|
316 |
|
|
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
|
317 |
|
|
// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
|
318 |
|
|
// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
|
319 |
|
|
// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
|
320 |
|
|
// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
321 |
|
|
// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
|
322 |
|
|
// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
323 |
|
|
// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
324 |
|
|
// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
325 |
|
|
// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
326 |
|
|
// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
|
327 |
|
|
// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
|
328 |
|
|
// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
329 |
|
|
// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
330 |
|
|
// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
331 |
|
|
// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
332 |
|
|
|
333 |
|
|
|
334 |
|
|
//
|
335 |
|
|
//
|
336 |
|
|
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
337 |
|
|
//
|
338 |
|
|
// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
|
339 |
|
|
//
|
340 |
|
|
//
|
341 |
|
|
//
|
342 |
3 |
dgisselq |
reg need_refresh;
|
343 |
2 |
dgisselq |
|
344 |
3 |
dgisselq |
wire w_precharge_all;
|
345 |
|
|
reg banks_are_closing, all_banks_closed;
|
346 |
6 |
dgisselq |
reg [3:0] bank_status [0:7];
|
347 |
|
|
reg [13:0] bank_address [0:7];
|
348 |
12 |
dgisselq |
reg [3:0] bank_wr_ck [0:7]; // tWTR
|
349 |
|
|
reg bank_wr_ckzro [0:7]; // tWTR
|
350 |
14 |
dgisselq |
reg [7:0] bank_open;
|
351 |
|
|
reg [7:0] bank_closed;
|
352 |
6 |
dgisselq |
|
353 |
12 |
dgisselq |
wire [3:0] write_recycle_clocks;
|
354 |
|
|
assign write_recycle_clocks = CKWR+4+4;
|
355 |
|
|
|
356 |
14 |
dgisselq |
initial bank_open = 8'h00;
|
357 |
|
|
initial bank_closed = 8'hff;
|
358 |
2 |
dgisselq |
always @(posedge i_clk)
|
359 |
|
|
begin
|
360 |
6 |
dgisselq |
bank_status[0] <= { bank_status[0][2:0], bank_status[0][0] };
|
361 |
|
|
bank_status[1] <= { bank_status[1][2:0], bank_status[1][0] };
|
362 |
|
|
bank_status[2] <= { bank_status[2][2:0], bank_status[2][0] };
|
363 |
|
|
bank_status[3] <= { bank_status[3][2:0], bank_status[3][0] };
|
364 |
|
|
bank_status[4] <= { bank_status[4][2:0], bank_status[4][0] };
|
365 |
|
|
bank_status[5] <= { bank_status[5][2:0], bank_status[5][0] };
|
366 |
|
|
bank_status[6] <= { bank_status[6][2:0], bank_status[6][0] };
|
367 |
|
|
bank_status[7] <= { bank_status[7][2:0], bank_status[7][0] };
|
368 |
|
|
all_banks_closed <= (bank_status[0][2:0] == 3'b00)
|
369 |
|
|
&&(bank_status[1][2:0] == 3'b00)
|
370 |
|
|
&&(bank_status[2][2:0] == 3'b00)
|
371 |
|
|
&&(bank_status[3][2:0] == 3'b00)
|
372 |
|
|
&&(bank_status[4][2:0] == 3'b00)
|
373 |
|
|
&&(bank_status[5][2:0] == 3'b00)
|
374 |
|
|
&&(bank_status[6][2:0] == 3'b00)
|
375 |
|
|
&&(bank_status[7][2:0] == 3'b00);
|
376 |
12 |
dgisselq |
|
377 |
|
|
bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-4'h1):4'h0;
|
378 |
|
|
bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-4'h1):4'h0;
|
379 |
|
|
bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-4'h1):4'h0;
|
380 |
|
|
bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-4'h1):4'h0;
|
381 |
|
|
bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-4'h1):4'h0;
|
382 |
|
|
bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-4'h1):4'h0;
|
383 |
|
|
bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-4'h1):4'h0;
|
384 |
|
|
bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-4'h1):4'h0;
|
385 |
|
|
|
386 |
|
|
bank_wr_ckzro[0] <= (bank_wr_ck[0][3:1]==3'b00);
|
387 |
|
|
bank_wr_ckzro[1] <= (bank_wr_ck[1][3:1]==3'b00);
|
388 |
|
|
bank_wr_ckzro[2] <= (bank_wr_ck[2][3:1]==3'b00);
|
389 |
|
|
bank_wr_ckzro[3] <= (bank_wr_ck[3][3:1]==3'b00);
|
390 |
|
|
bank_wr_ckzro[4] <= (bank_wr_ck[4][3:1]==3'b00);
|
391 |
|
|
bank_wr_ckzro[5] <= (bank_wr_ck[5][3:1]==3'b00);
|
392 |
|
|
bank_wr_ckzro[6] <= (bank_wr_ck[6][3:1]==3'b00);
|
393 |
|
|
bank_wr_ckzro[7] <= (bank_wr_ck[7][3:1]==3'b00);
|
394 |
|
|
|
395 |
14 |
dgisselq |
bank_open[0] <= (bank_status[0][1:0] == 2'h3);
|
396 |
|
|
bank_open[1] <= (bank_status[1][1:0] == 2'h3);
|
397 |
|
|
bank_open[2] <= (bank_status[2][1:0] == 2'h3);
|
398 |
|
|
bank_open[3] <= (bank_status[3][1:0] == 2'h3);
|
399 |
|
|
bank_open[4] <= (bank_status[4][1:0] == 2'h3);
|
400 |
|
|
bank_open[5] <= (bank_status[5][1:0] == 2'h3);
|
401 |
|
|
bank_open[6] <= (bank_status[6][1:0] == 2'h3);
|
402 |
|
|
bank_open[7] <= (bank_status[7][1:0] == 2'h3);
|
403 |
|
|
|
404 |
|
|
bank_closed[0] <= (bank_status[0][0] == 1'b0);
|
405 |
|
|
bank_closed[1] <= (bank_status[1][0] == 1'b0);
|
406 |
|
|
bank_closed[2] <= (bank_status[2][0] == 1'b0);
|
407 |
|
|
bank_closed[3] <= (bank_status[3][0] == 1'b0);
|
408 |
|
|
bank_closed[4] <= (bank_status[4][0] == 1'b0);
|
409 |
|
|
bank_closed[5] <= (bank_status[5][0] == 1'b0);
|
410 |
|
|
bank_closed[6] <= (bank_status[6][0] == 1'b0);
|
411 |
|
|
bank_closed[7] <= (bank_status[7][0] == 1'b0);
|
412 |
|
|
|
413 |
12 |
dgisselq |
if (w_this_rw_move)
|
414 |
|
|
bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 4'h0
|
415 |
|
|
: write_recycle_clocks;
|
416 |
|
|
|
417 |
14 |
dgisselq |
if (maintenance_override)
|
418 |
2 |
dgisselq |
begin
|
419 |
6 |
dgisselq |
bank_status[0][0] <= 1'b0;
|
420 |
|
|
bank_status[1][0] <= 1'b0;
|
421 |
|
|
bank_status[2][0] <= 1'b0;
|
422 |
|
|
bank_status[3][0] <= 1'b0;
|
423 |
|
|
bank_status[4][0] <= 1'b0;
|
424 |
|
|
bank_status[5][0] <= 1'b0;
|
425 |
|
|
bank_status[6][0] <= 1'b0;
|
426 |
|
|
bank_status[7][0] <= 1'b0;
|
427 |
2 |
dgisselq |
banks_are_closing <= 1'b1;
|
428 |
14 |
dgisselq |
bank_closed <= 8'hff;
|
429 |
|
|
bank_open <= 8'h00;
|
430 |
2 |
dgisselq |
end else if (need_close_bank)
|
431 |
|
|
begin
|
432 |
6 |
dgisselq |
bank_status[close_bank_cmd[16:14]]
|
433 |
8 |
dgisselq |
<= { bank_status[close_bank_cmd[16:14]][2:0], 1'b0 };
|
434 |
14 |
dgisselq |
bank_open[close_bank_cmd[16:14]] <= 1'b0;
|
435 |
6 |
dgisselq |
// bank_status[close_bank_cmd[16:14]][0] <= 1'b0;
|
436 |
2 |
dgisselq |
end else if (need_open_bank)
|
437 |
|
|
begin
|
438 |
6 |
dgisselq |
bank_status[activate_bank_cmd[16:14]]
|
439 |
|
|
<= { bank_status[activate_bank_cmd[16:14]][2:0], 1'b1 };
|
440 |
|
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
441 |
2 |
dgisselq |
all_banks_closed <= 1'b0;
|
442 |
|
|
banks_are_closing <= 1'b0;
|
443 |
14 |
dgisselq |
bank_closed[activate_bank_cmd[16:14]] <= 1'b0;
|
444 |
|
|
end else if (valid_bank)
|
445 |
6 |
dgisselq |
;
|
446 |
|
|
else if (maybe_close_next_bank)
|
447 |
|
|
begin
|
448 |
|
|
bank_status[maybe_close_cmd[16:14]]
|
449 |
8 |
dgisselq |
<= { bank_status[maybe_close_cmd[16:14]][2:0], 1'b0 };
|
450 |
14 |
dgisselq |
bank_open[maybe_close_cmd[16:14]] <= 1'b0;
|
451 |
6 |
dgisselq |
end else if (maybe_open_next_bank)
|
452 |
|
|
begin
|
453 |
|
|
bank_status[maybe_open_cmd[16:14]]
|
454 |
|
|
<= { bank_status[maybe_open_cmd[16:14]][2:0], 1'b1 };
|
455 |
|
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
456 |
|
|
all_banks_closed <= 1'b0;
|
457 |
|
|
banks_are_closing <= 1'b0;
|
458 |
14 |
dgisselq |
bank_closed[maybe_open_cmd[16:14]] <= 1'b0;
|
459 |
2 |
dgisselq |
end
|
460 |
|
|
end
|
461 |
|
|
|
462 |
|
|
always @(posedge i_clk)
|
463 |
3 |
dgisselq |
// if (cmd[22:19] == `DDR_ACTIVATE)
|
464 |
8 |
dgisselq |
if (w_this_opening_bank)
|
465 |
5 |
dgisselq |
bank_address[activate_bank_cmd[16:14]]
|
466 |
|
|
<= activate_bank_cmd[13:0];
|
467 |
8 |
dgisselq |
else if (!w_this_maybe_open)
|
468 |
|
|
bank_address[maybe_open_cmd[16:14]]
|
469 |
|
|
<= maybe_open_cmd[13:0];
|
470 |
2 |
dgisselq |
|
471 |
|
|
//
|
472 |
|
|
//
|
473 |
|
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
474 |
|
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
475 |
|
|
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
|
476 |
|
|
//
|
477 |
|
|
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
|
478 |
|
|
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
|
479 |
|
|
// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
|
480 |
|
|
// time, no more refreshes will be needed for 6240 clocks.
|
481 |
|
|
//
|
482 |
|
|
// Let's think this through:
|
483 |
|
|
// REFRESH_COST = (n*(320)+24)/(n*1560)
|
484 |
|
|
//
|
485 |
|
|
//
|
486 |
|
|
//
|
487 |
7 |
dgisselq |
reg refresh_ztimer;
|
488 |
|
|
reg [16:0] refresh_counter;
|
489 |
14 |
dgisselq |
reg [2:0] refresh_addr;
|
490 |
7 |
dgisselq |
reg [23:0] refresh_instruction;
|
491 |
2 |
dgisselq |
always @(posedge i_clk)
|
492 |
7 |
dgisselq |
if (reset_override)
|
493 |
14 |
dgisselq |
refresh_addr <= 3'hf;
|
494 |
7 |
dgisselq |
else if (refresh_ztimer)
|
495 |
14 |
dgisselq |
refresh_addr <= refresh_addr + 3'h1;
|
496 |
7 |
dgisselq |
else if (refresh_instruction[`DDR_RFBEGIN])
|
497 |
14 |
dgisselq |
refresh_addr <= 3'h0;
|
498 |
6 |
dgisselq |
|
499 |
2 |
dgisselq |
always @(posedge i_clk)
|
500 |
7 |
dgisselq |
if (reset_override)
|
501 |
|
|
begin
|
502 |
|
|
refresh_ztimer <= 1'b1;
|
503 |
|
|
refresh_counter <= 17'd0;
|
504 |
|
|
end else if (!refresh_ztimer)
|
505 |
|
|
begin
|
506 |
|
|
refresh_ztimer <= (refresh_counter == 17'h1);
|
507 |
|
|
refresh_counter <= (refresh_counter - 17'h1);
|
508 |
|
|
end else if (refresh_instruction[`DDR_RFTIMER])
|
509 |
|
|
begin
|
510 |
|
|
refresh_ztimer <= 1'b0;
|
511 |
|
|
refresh_counter <= refresh_instruction[16:0];
|
512 |
|
|
end
|
513 |
2 |
dgisselq |
|
514 |
14 |
dgisselq |
`ifdef QUADRUPLE_REFRESH
|
515 |
|
|
// REFI4 = 13'd6240
|
516 |
7 |
dgisselq |
wire [16:0] w_ckREFIn, w_ckREFRst;
|
517 |
13 |
dgisselq |
assign w_ckREFIn[(CKRBITS-1): 0] = CKREFI4-5*CKRFC-2-10;
|
518 |
|
|
assign w_ckREFIn[ 16:(CKRBITS)] = 0;
|
519 |
|
|
assign w_ckREFRst = CKRFC-2-12;
|
520 |
7 |
dgisselq |
|
521 |
2 |
dgisselq |
always @(posedge i_clk)
|
522 |
7 |
dgisselq |
if (refresh_ztimer)
|
523 |
|
|
case(refresh_addr)//NEED-RFC, HAVE-TIMER,
|
524 |
|
|
4'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFIn };
|
525 |
|
|
// 17'd10 = time to complete write, plus write recovery time
|
526 |
|
|
// minus two (cause we can't count zero or one)
|
527 |
|
|
// = WL+4+tWR-2 = 10
|
528 |
|
|
// = 5+4+3-2 = 10
|
529 |
|
|
4'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, 17'd10 };
|
530 |
|
|
4'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
|
531 |
|
|
4'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, 17'd2 };
|
532 |
|
|
4'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
533 |
|
|
4'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
534 |
|
|
4'h6: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
535 |
|
|
4'h7: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
536 |
|
|
4'h8: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
537 |
|
|
4'h9: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
538 |
|
|
4'ha: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
539 |
|
|
4'hb: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
540 |
8 |
dgisselq |
4'hc: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFRst };
|
541 |
7 |
dgisselq |
default:
|
542 |
|
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
543 |
|
|
endcase
|
544 |
14 |
dgisselq |
`else
|
545 |
|
|
wire [16:0] w_ckREFI_left, w_ckRFC_nxt;
|
546 |
|
|
assign w_ckREFI_left[12:0] = CKREFI-CKRFC-2-19;
|
547 |
|
|
assign w_ckREFI_left[16:13] = 0;
|
548 |
|
|
assign w_ckRFC_nxt[8:0] = CKRFC+9'h2;
|
549 |
|
|
assign w_ckRFC_nxt[16:9] = 0;
|
550 |
2 |
dgisselq |
|
551 |
14 |
dgisselq |
always @(posedge i_clk)
|
552 |
|
|
if (refresh_ztimer)
|
553 |
|
|
case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
|
554 |
|
|
3'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFI_left };
|
555 |
|
|
3'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, 17'd10 };
|
556 |
|
|
3'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
|
557 |
|
|
3'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, 17'd2 };
|
558 |
|
|
3'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
559 |
|
|
3'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC_nxt };
|
560 |
|
|
default:
|
561 |
|
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
562 |
|
|
endcase
|
563 |
|
|
`endif
|
564 |
2 |
dgisselq |
|
565 |
14 |
dgisselq |
always @(posedge i_clk)
|
566 |
|
|
if (reset_override)
|
567 |
|
|
refresh_cmd <= { `DDR_NOOP, w_ckREFI_left };
|
568 |
|
|
else if (refresh_ztimer)
|
569 |
|
|
refresh_cmd <= refresh_instruction[20:0];
|
570 |
|
|
always @(posedge i_clk)
|
571 |
|
|
if (reset_override)
|
572 |
|
|
need_refresh <= 1'b0;
|
573 |
|
|
else if (refresh_ztimer)
|
574 |
|
|
need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
|
575 |
|
|
|
576 |
|
|
|
577 |
2 |
dgisselq |
//
|
578 |
|
|
//
|
579 |
|
|
// Let's track: when will our bus be active? When will we be reading or
|
580 |
|
|
// writing?
|
581 |
|
|
//
|
582 |
|
|
//
|
583 |
13 |
dgisselq |
reg [`BUSNOW:0] bus_active, bus_read, bus_new, bus_ack;
|
584 |
7 |
dgisselq |
reg [1:0] bus_subaddr [`BUSNOW:0];
|
585 |
3 |
dgisselq |
initial bus_active = 0;
|
586 |
14 |
dgisselq |
initial bus_ack = 0;
|
587 |
2 |
dgisselq |
always @(posedge i_clk)
|
588 |
|
|
begin
|
589 |
7 |
dgisselq |
bus_active[`BUSNOW:0] <= { bus_active[(`BUSNOW-1):0], 1'b0 };
|
590 |
|
|
bus_read[`BUSNOW:0] <= { bus_read[(`BUSNOW-1):0], 1'b0 }; // Drive the d-bus?
|
591 |
9 |
dgisselq |
// Is this a new command? i.e., the start of a transaction?
|
592 |
|
|
bus_new[`BUSNOW:0] <= { bus_new[(`BUSNOW-1):0], 1'b0 };
|
593 |
13 |
dgisselq |
// Will this position on the bus get a wishbone acknowledgement?
|
594 |
|
|
bus_ack[`BUSNOW:0] <= { bus_ack[(`BUSNOW-1):0], 1'b0 };
|
595 |
3 |
dgisselq |
//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
|
596 |
2 |
dgisselq |
bus_subaddr[8] <= bus_subaddr[7];
|
597 |
|
|
bus_subaddr[7] <= bus_subaddr[6];
|
598 |
|
|
bus_subaddr[6] <= bus_subaddr[5];
|
599 |
|
|
bus_subaddr[5] <= bus_subaddr[4];
|
600 |
|
|
bus_subaddr[4] <= bus_subaddr[3];
|
601 |
|
|
bus_subaddr[3] <= bus_subaddr[2];
|
602 |
|
|
bus_subaddr[2] <= bus_subaddr[1];
|
603 |
|
|
bus_subaddr[1] <= bus_subaddr[0];
|
604 |
|
|
bus_subaddr[0] <= 2'h3;
|
605 |
13 |
dgisselq |
|
606 |
|
|
bus_ack[5] <= (bus_ack[4])&&
|
607 |
|
|
((bus_subaddr[5] != bus_subaddr[4])
|
608 |
|
|
||(bus_new[4]));
|
609 |
7 |
dgisselq |
if (w_this_rw_move)
|
610 |
2 |
dgisselq |
begin
|
611 |
|
|
bus_active[3:0]<= 4'hf; // Once per clock
|
612 |
|
|
bus_subaddr[3] <= 2'h0;
|
613 |
|
|
bus_subaddr[2] <= 2'h1;
|
614 |
|
|
bus_subaddr[1] <= 2'h2;
|
615 |
9 |
dgisselq |
bus_new[{ 2'b0, rw_sub }] <= 1'b1;
|
616 |
14 |
dgisselq |
bus_ack[3:0] <= 4'h0;
|
617 |
13 |
dgisselq |
bus_ack[{ 2'b0, rw_sub }] <= 1'b1;
|
618 |
4 |
dgisselq |
|
619 |
9 |
dgisselq |
bus_read[3:0] <= (rw_we)? 4'h0:4'hf;
|
620 |
13 |
dgisselq |
end else if ((s_pending)&&(!pipe_stall))
|
621 |
|
|
begin
|
622 |
|
|
if (bus_subaddr[3] == s_sub)
|
623 |
|
|
bus_ack[4] <= 1'b1;
|
624 |
|
|
if (bus_subaddr[2] == s_sub)
|
625 |
|
|
bus_ack[3] <= 1'b1;
|
626 |
|
|
if (bus_subaddr[1] == s_sub)
|
627 |
|
|
bus_ack[2] <= 1'b1;
|
628 |
14 |
dgisselq |
if (bus_subaddr[0] == s_sub)
|
629 |
|
|
bus_ack[1] <= 1'b1;
|
630 |
2 |
dgisselq |
end
|
631 |
|
|
end
|
632 |
|
|
|
633 |
13 |
dgisselq |
// Need to set o_wb_dqs high one clock prior to any read.
|
634 |
2 |
dgisselq |
always @(posedge i_clk)
|
635 |
13 |
dgisselq |
drive_dqs <= (|bus_active[`BUSREG:(`BUSREG-1)])
|
636 |
|
|
&&(~(|bus_read[`BUSREG:(`BUSREG-1)]));
|
637 |
2 |
dgisselq |
|
638 |
|
|
//
|
639 |
|
|
//
|
640 |
|
|
// Now, let's see, can we issue a read command?
|
641 |
|
|
//
|
642 |
|
|
//
|
643 |
14 |
dgisselq |
reg pre_valid;
|
644 |
|
|
always @(posedge i_clk)
|
645 |
|
|
if ((refresh_ztimer)&&(refresh_instruction[`DDR_NEEDREFRESH]))
|
646 |
|
|
pre_valid <= 1'b0;
|
647 |
|
|
else if (need_refresh)
|
648 |
|
|
pre_valid <= 1'b0;
|
649 |
|
|
else if (w_this_rw_move)
|
650 |
|
|
pre_valid <= 1'b0;
|
651 |
|
|
else if (bus_active[0])
|
652 |
|
|
pre_valid <= 1'b0;
|
653 |
|
|
else
|
654 |
|
|
pre_valid <= 1'b1;
|
655 |
|
|
|
656 |
|
|
assign w_r_valid = (pre_valid)&&(r_pending)
|
657 |
|
|
&&(bank_status[r_bank][1])
|
658 |
|
|
&&(bank_address[r_bank]==r_row)
|
659 |
|
|
&&((r_we)||(bank_wr_ckzro[r_bank]));
|
660 |
|
|
assign w_s_valid = (pre_valid)&&(s_pending)
|
661 |
|
|
&&(bank_status[s_bank][1])
|
662 |
|
|
&&(bank_address[s_bank]==s_row)
|
663 |
|
|
&&((s_we)||(bank_wr_ckzro[s_bank]));
|
664 |
9 |
dgisselq |
assign w_s_match = (s_pending)&&(r_pending)&&(r_we == s_we)
|
665 |
|
|
&&(r_row == s_row)&&(r_bank == s_bank)
|
666 |
|
|
&&(r_col == s_col)
|
667 |
|
|
&&(r_sub > s_sub);
|
668 |
14 |
dgisselq |
|
669 |
9 |
dgisselq |
reg pipe_stall;
|
670 |
2 |
dgisselq |
always @(posedge i_clk)
|
671 |
|
|
begin
|
672 |
9 |
dgisselq |
r_pending <= (i_wb_stb)&&(~o_wb_stall)
|
673 |
|
|
||(r_pending)&&(pipe_stall);
|
674 |
|
|
if (~pipe_stall)
|
675 |
|
|
s_pending <= r_pending;
|
676 |
|
|
if (~pipe_stall)
|
677 |
2 |
dgisselq |
begin
|
678 |
9 |
dgisselq |
pipe_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
679 |
|
|
o_wb_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
680 |
|
|
end else begin // if (pipe_stall)
|
681 |
|
|
pipe_stall <= (s_pending)&&((!w_s_valid)||(valid_bank)||(r_move)||(last_valid_bank));
|
682 |
|
|
o_wb_stall <= (s_pending)&&((!w_s_valid)||(valid_bank)||(r_move)||(last_valid_bank));
|
683 |
|
|
end
|
684 |
|
|
if (need_refresh)
|
685 |
2 |
dgisselq |
o_wb_stall <= 1'b1;
|
686 |
|
|
|
687 |
9 |
dgisselq |
if (~pipe_stall)
|
688 |
2 |
dgisselq |
begin
|
689 |
|
|
r_we <= i_wb_we;
|
690 |
|
|
r_addr <= i_wb_addr;
|
691 |
|
|
r_data <= i_wb_data;
|
692 |
5 |
dgisselq |
r_row <= i_wb_addr[25:12];
|
693 |
|
|
r_bank <= i_wb_addr[11:9];
|
694 |
|
|
r_col <= { i_wb_addr[8:2], 3'b000 }; // 9:2
|
695 |
2 |
dgisselq |
r_sub <= i_wb_addr[1:0];
|
696 |
|
|
|
697 |
|
|
// pre-emptive work
|
698 |
6 |
dgisselq |
r_nxt_row <= (i_wb_addr[11:9]==3'h7)?i_wb_addr[25:12]+14'h1:i_wb_addr[25:12];
|
699 |
5 |
dgisselq |
r_nxt_bank <= i_wb_addr[11:9]+3'h1;
|
700 |
2 |
dgisselq |
end
|
701 |
9 |
dgisselq |
|
702 |
|
|
if (~pipe_stall)
|
703 |
|
|
begin
|
704 |
|
|
// Moving one down the pipeline
|
705 |
|
|
s_we <= r_we;
|
706 |
|
|
s_addr <= r_addr;
|
707 |
|
|
s_data <= r_data;
|
708 |
|
|
s_row <= r_row;
|
709 |
|
|
s_bank <= r_bank;
|
710 |
|
|
s_col <= r_col;
|
711 |
|
|
s_sub <= r_sub;
|
712 |
|
|
|
713 |
|
|
// pre-emptive work
|
714 |
|
|
s_nxt_row <= r_nxt_row;
|
715 |
|
|
s_nxt_bank <= r_nxt_bank;
|
716 |
|
|
|
717 |
10 |
dgisselq |
// s_match <= w_s_match;
|
718 |
9 |
dgisselq |
end
|
719 |
2 |
dgisselq |
end
|
720 |
|
|
|
721 |
14 |
dgisselq |
assign w_need_close_this_bank = (r_pending)
|
722 |
|
|
&&(bank_open[r_bank])
|
723 |
12 |
dgisselq |
&&(bank_wr_ckzro[r_bank])
|
724 |
9 |
dgisselq |
&&(r_row != bank_address[r_bank])
|
725 |
14 |
dgisselq |
||(pipe_stall)&&(s_pending)&&(bank_open[s_bank])
|
726 |
9 |
dgisselq |
&&(s_row != bank_address[s_bank]);
|
727 |
14 |
dgisselq |
assign w_need_open_bank = (r_pending)&&(bank_closed[r_bank])
|
728 |
|
|
||(pipe_stall)&&(s_pending)&&(bank_closed[s_bank]);
|
729 |
3 |
dgisselq |
|
730 |
2 |
dgisselq |
always @(posedge i_clk)
|
731 |
|
|
begin
|
732 |
6 |
dgisselq |
need_close_bank <= (w_need_close_this_bank)
|
733 |
10 |
dgisselq |
&&(!need_open_bank)
|
734 |
|
|
&&(!need_close_bank)
|
735 |
14 |
dgisselq |
&&(!w_this_closing_bank);
|
736 |
2 |
dgisselq |
|
737 |
14 |
dgisselq |
maybe_close_next_bank <= (s_pending)
|
738 |
|
|
&&(bank_open[s_nxt_bank])
|
739 |
|
|
&&(bank_wr_ckzro[s_nxt_bank])
|
740 |
|
|
&&(s_nxt_row != bank_address[s_nxt_bank])
|
741 |
6 |
dgisselq |
&&(!w_this_maybe_close)&&(!last_maybe_close);
|
742 |
2 |
dgisselq |
|
743 |
6 |
dgisselq |
close_bank_cmd <= { `DDR_PRECHARGE, r_bank, r_row[13:11], 1'b0, r_row[9:0] };
|
744 |
|
|
maybe_close_cmd <= { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[13:11], 1'b0, r_nxt_row[9:0] };
|
745 |
2 |
dgisselq |
|
746 |
|
|
|
747 |
6 |
dgisselq |
need_open_bank <= (w_need_open_bank)
|
748 |
14 |
dgisselq |
&&(!w_this_opening_bank);
|
749 |
6 |
dgisselq |
last_open_bank <= (w_this_opening_bank);
|
750 |
2 |
dgisselq |
|
751 |
14 |
dgisselq |
maybe_open_next_bank <= (s_pending)
|
752 |
|
|
&&(!need_close_bank)
|
753 |
|
|
&&(!need_open_bank)
|
754 |
|
|
&&(bank_closed[s_nxt_bank])
|
755 |
|
|
&&(!w_this_maybe_open); // &&(!last_maybe_open);
|
756 |
2 |
dgisselq |
|
757 |
6 |
dgisselq |
activate_bank_cmd<= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
|
758 |
|
|
maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
|
759 |
2 |
dgisselq |
|
760 |
|
|
|
761 |
|
|
|
762 |
14 |
dgisselq |
valid_bank <= ((w_r_valid)||((pipe_stall)&&(w_s_valid)))
|
763 |
|
|
&&(!last_valid_bank)&&(!r_move)
|
764 |
|
|
&&(!w_this_rw_move);
|
765 |
6 |
dgisselq |
last_valid_bank <= r_move;
|
766 |
2 |
dgisselq |
|
767 |
9 |
dgisselq |
if ((s_pending)&&(pipe_stall))
|
768 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
|
769 |
|
|
else if (r_pending)
|
770 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (r_we)?`DDR_WRITE:`DDR_READ;
|
771 |
|
|
else
|
772 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= `DDR_NOOP;
|
773 |
|
|
if ((s_pending)&&(pipe_stall))
|
774 |
|
|
rw_cmd[`DDR_WEBIT-1:0] <= { s_bank, 3'h0, 1'b0, s_col };
|
775 |
|
|
else
|
776 |
|
|
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 3'h0, 1'b0, r_col };
|
777 |
|
|
if ((s_pending)&&(pipe_stall))
|
778 |
|
|
rw_sub <= 2'b11 - s_sub;
|
779 |
|
|
else
|
780 |
|
|
rw_sub <= 2'b11 - r_sub;
|
781 |
|
|
if ((s_pending)&&(pipe_stall))
|
782 |
|
|
rw_we <= s_we;
|
783 |
|
|
else
|
784 |
|
|
rw_we <= r_we;
|
785 |
|
|
|
786 |
2 |
dgisselq |
end
|
787 |
|
|
|
788 |
|
|
//
|
789 |
|
|
//
|
790 |
|
|
// Okay, let's look at the last assignment in our chain. It should look
|
791 |
|
|
// something like:
|
792 |
|
|
always @(posedge i_clk)
|
793 |
4 |
dgisselq |
if (i_reset)
|
794 |
|
|
o_ddr_reset_n <= 1'b0;
|
795 |
|
|
else if (reset_ztimer)
|
796 |
|
|
o_ddr_reset_n <= reset_instruction[`DDR_RSTBIT];
|
797 |
2 |
dgisselq |
always @(posedge i_clk)
|
798 |
4 |
dgisselq |
if (i_reset)
|
799 |
|
|
o_ddr_cke <= 1'b0;
|
800 |
|
|
else if (reset_ztimer)
|
801 |
|
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
802 |
6 |
dgisselq |
|
803 |
9 |
dgisselq |
always @(posedge i_clk)
|
804 |
|
|
if (i_reset)
|
805 |
|
|
maintenance_override <= 1'b1;
|
806 |
|
|
else
|
807 |
|
|
maintenance_override <= (reset_override)||(need_refresh);
|
808 |
7 |
dgisselq |
|
809 |
9 |
dgisselq |
initial maintenance_cmd = { `DDR_NOOP, 17'h00 };
|
810 |
|
|
always @(posedge i_clk)
|
811 |
|
|
if (i_reset)
|
812 |
|
|
maintenance_cmd <= { `DDR_NOOP, 17'h00 };
|
813 |
|
|
else
|
814 |
|
|
maintenance_cmd <= (reset_override)?reset_cmd:refresh_cmd;
|
815 |
|
|
|
816 |
|
|
assign w_this_closing_bank = (!maintenance_override)
|
817 |
6 |
dgisselq |
&&(need_close_bank);
|
818 |
9 |
dgisselq |
assign w_this_opening_bank = (!maintenance_override)
|
819 |
6 |
dgisselq |
&&(!need_close_bank)&&(need_open_bank);
|
820 |
9 |
dgisselq |
assign w_this_rw_move = (!maintenance_override)
|
821 |
7 |
dgisselq |
&&(!need_close_bank)&&(!need_open_bank)
|
822 |
14 |
dgisselq |
&&(valid_bank);
|
823 |
9 |
dgisselq |
assign w_this_maybe_close = (!maintenance_override)
|
824 |
6 |
dgisselq |
&&(!need_close_bank)&&(!need_open_bank)
|
825 |
14 |
dgisselq |
&&(!valid_bank)
|
826 |
6 |
dgisselq |
&&(maybe_close_next_bank);
|
827 |
9 |
dgisselq |
assign w_this_maybe_open = (!maintenance_override)
|
828 |
6 |
dgisselq |
&&(!need_close_bank)&&(!need_open_bank)
|
829 |
14 |
dgisselq |
&&(!valid_bank)
|
830 |
6 |
dgisselq |
&&(!maybe_close_next_bank)
|
831 |
|
|
&&(maybe_open_next_bank);
|
832 |
2 |
dgisselq |
always @(posedge i_clk)
|
833 |
|
|
begin
|
834 |
6 |
dgisselq |
last_opening_bank <= 1'b0;
|
835 |
|
|
last_closing_bank <= 1'b0;
|
836 |
|
|
last_maybe_open <= 1'b0;
|
837 |
|
|
last_maybe_close <= 1'b0;
|
838 |
2 |
dgisselq |
r_move <= 1'b0;
|
839 |
9 |
dgisselq |
if (maintenance_override) // Command from either reset or
|
840 |
|
|
cmd <= maintenance_cmd; // refresh logic
|
841 |
|
|
else if (need_close_bank)
|
842 |
2 |
dgisselq |
begin
|
843 |
|
|
cmd <= close_bank_cmd;
|
844 |
6 |
dgisselq |
last_closing_bank <= 1'b1;
|
845 |
|
|
end else if (need_open_bank)
|
846 |
|
|
begin
|
847 |
2 |
dgisselq |
cmd <= activate_bank_cmd;
|
848 |
6 |
dgisselq |
last_opening_bank <= 1'b1;
|
849 |
14 |
dgisselq |
end else if (valid_bank)
|
850 |
2 |
dgisselq |
begin
|
851 |
|
|
cmd <= rw_cmd;
|
852 |
|
|
r_move <= 1'b1;
|
853 |
6 |
dgisselq |
end else if (maybe_close_next_bank)
|
854 |
|
|
begin
|
855 |
|
|
cmd <= maybe_close_cmd;
|
856 |
|
|
last_maybe_close <= 1'b1;
|
857 |
|
|
end else if (maybe_open_next_bank)
|
858 |
|
|
begin
|
859 |
|
|
cmd <= maybe_open_cmd;
|
860 |
|
|
last_maybe_open <= 1'b1;
|
861 |
2 |
dgisselq |
end else
|
862 |
4 |
dgisselq |
cmd <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
863 |
2 |
dgisselq |
end
|
864 |
|
|
|
865 |
14 |
dgisselq |
`define LGFIFOLN 4
|
866 |
|
|
`define FIFOLEN 16
|
867 |
7 |
dgisselq |
reg [(`LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
|
868 |
|
|
reg [31:0] bus_fifo_data [0:(`FIFOLEN-1)];
|
869 |
|
|
reg [1:0] bus_fifo_sub [0:(`FIFOLEN-1)];
|
870 |
|
|
reg bus_fifo_new [0:(`FIFOLEN-1)];
|
871 |
|
|
reg pre_ack;
|
872 |
3 |
dgisselq |
|
873 |
7 |
dgisselq |
// The bus R/W FIFO
|
874 |
|
|
wire w_bus_fifo_read_next_transaction;
|
875 |
13 |
dgisselq |
assign w_bus_fifo_read_next_transaction = (bus_ack[`BUSREG]);
|
876 |
7 |
dgisselq |
always @(posedge i_clk)
|
877 |
|
|
begin
|
878 |
|
|
pre_ack <= 1'b0;
|
879 |
|
|
o_ddr_dm <= 1'b0;
|
880 |
13 |
dgisselq |
if (reset_override)
|
881 |
7 |
dgisselq |
begin
|
882 |
13 |
dgisselq |
bus_fifo_head <= {(`LGFIFOLN){1'b0}};
|
883 |
|
|
bus_fifo_tail <= {(`LGFIFOLN){1'b0}};
|
884 |
7 |
dgisselq |
o_ddr_dm <= 1'b0;
|
885 |
|
|
end else begin
|
886 |
13 |
dgisselq |
if ((s_pending)&&(!pipe_stall))
|
887 |
|
|
bus_fifo_head <= bus_fifo_head + 1'b1;
|
888 |
7 |
dgisselq |
|
889 |
|
|
o_ddr_dm <= (bus_active[`BUSREG])&&(!bus_read[`BUSREG]);
|
890 |
|
|
if (w_bus_fifo_read_next_transaction)
|
891 |
|
|
begin
|
892 |
13 |
dgisselq |
bus_fifo_tail <= bus_fifo_tail + 1'b1;
|
893 |
7 |
dgisselq |
pre_ack <= 1'b1;
|
894 |
|
|
o_ddr_dm <= 1'b0;
|
895 |
|
|
end
|
896 |
|
|
end
|
897 |
9 |
dgisselq |
bus_fifo_data[bus_fifo_head] <= s_data;
|
898 |
|
|
bus_fifo_sub[bus_fifo_head] <= s_sub;
|
899 |
7 |
dgisselq |
bus_fifo_new[bus_fifo_head] <= w_this_rw_move;
|
900 |
13 |
dgisselq |
|
901 |
|
|
//
|
902 |
|
|
// if ((s_pending)&&(!pipe_stall)&&(!nxt_valid))
|
903 |
|
|
// nxt_fifo_data <= s_data;
|
904 |
|
|
// nxt_fifo_sub <= s_sub;
|
905 |
|
|
// nxt_fifo_new <= w_this_rw_move;
|
906 |
|
|
// nxt_valid <= 1'b1;
|
907 |
|
|
// bus_fifo_head <= bus_fifo_head+1;
|
908 |
|
|
// bus_fifo_tail <= bus_fifo_tail+1;
|
909 |
|
|
// else if (w_bus_fifo_read_next_transaction)
|
910 |
|
|
// nxt_fifo_data <= bus_fifo_data[bus_fifo_tail]
|
911 |
|
|
// nxt_fifo_sub <= bus_fifo_data[bus_fifo_tail]
|
912 |
|
|
// nxt_fifo_new <= bus_fifo_data[bus_fifo_tail]
|
913 |
|
|
// nxt_valid <= (bus_fifo_tail+1 == bus_fifo_head);
|
914 |
|
|
//
|
915 |
|
|
// if ((!valid)||(w_bus_fifo_next_read_transaction))
|
916 |
|
|
// nxt_ <= bus_fifo_x
|
917 |
7 |
dgisselq |
end
|
918 |
|
|
|
919 |
|
|
|
920 |
3 |
dgisselq |
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
|
921 |
|
|
assign o_ddr_ras_n = cmd[`DDR_RASBIT];
|
922 |
|
|
assign o_ddr_cas_n = cmd[`DDR_CASBIT];
|
923 |
|
|
assign o_ddr_we_n = cmd[`DDR_WEBIT];
|
924 |
2 |
dgisselq |
assign o_ddr_dqs = drive_dqs;
|
925 |
3 |
dgisselq |
assign o_ddr_addr = cmd[(`DDR_ADDR_BITS-1):0];
|
926 |
|
|
assign o_ddr_ba = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
|
927 |
7 |
dgisselq |
always @(posedge i_clk)
|
928 |
|
|
o_ddr_data <= bus_fifo_data[bus_fifo_tail];
|
929 |
3 |
dgisselq |
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
930 |
2 |
dgisselq |
&&(o_ddr_addr[10]); // 5 bits
|
931 |
|
|
|
932 |
13 |
dgisselq |
assign o_ddr_bus_oe = drive_dqs; // ~bus_read[`BUSNOW];
|
933 |
2 |
dgisselq |
|
934 |
4 |
dgisselq |
// ODT must be in high impedence while reset_n=0, then it can be set
|
935 |
13 |
dgisselq |
// to low or high. As per spec, ODT = 0 during reads
|
936 |
|
|
always @(posedge i_clk)
|
937 |
|
|
o_ddr_odt <= (bus_active[`BUSREG-3])&&(!bus_read[`BUSREG-3])
|
938 |
|
|
||(bus_active[`BUSREG-4])&&(!bus_read[`BUSREG-4])
|
939 |
|
|
||((w_this_rw_move)&&(rw_we));
|
940 |
2 |
dgisselq |
|
941 |
7 |
dgisselq |
always @(posedge i_clk)
|
942 |
|
|
o_wb_ack <= pre_ack;
|
943 |
|
|
always @(posedge i_clk)
|
944 |
|
|
o_wb_data <= i_ddr_data;
|
945 |
4 |
dgisselq |
|
946 |
2 |
dgisselq |
endmodule
|