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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbddrsdram.v
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//
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dgisselq |
// Project: A wishbone controlled DDR3 SDRAM memory controller.
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// Used in: OpenArty, an entirely open SoC based upon the Arty platform
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dgisselq |
//
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dgisselq |
// Purpose: To control a DDR3-1333 (9-9-9) memory from a wishbone bus.
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// In our particular implementation, there will be two command
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// clocks (2.5 ns) per FPGA clock (i_clk) at 5 ns, and 64-bits transferred
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// per FPGA clock. However, since the memory is focused around 128-bit
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// word transfers, attempts to transfer other than adjacent 64-bit words
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// will (of necessity) suffer stalls. Please see the documentation for
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// more details of how this controller works.
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dgisselq |
//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Possible commands to the DDR3 memory. These consist of settings for the
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// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
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`define DDR_MRSET 4'b0000
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`define DDR_REFRESH 4'b0001
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`define DDR_PRECHARGE 4'b0010
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`define DDR_ACTIVATE 4'b0011
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`define DDR_WRITE 4'b0100
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`define DDR_READ 4'b0101
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dgisselq |
`define DDR_ZQS 4'b0110
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dgisselq |
`define DDR_NOOP 4'b0111
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//`define DDR_DESELECT 4'b1???
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//
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// In this controller, 24-bit commands tend to be passed around. These
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// 'commands' are bit fields. Here we specify the bits associated with
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// the bit fields.
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dgisselq |
`define DDR_RSTDONE 24 // End the reset sequence?
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`define DDR_RSTTIMER 23 // Does this reset command take multiple clocks?
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`define DDR_RSTBIT 22 // Value to place on reset_n
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`define DDR_CKEBIT 21 // Should this reset command set CKE?
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dgisselq |
//
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// Refresh command bit fields
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`define DDR_PREREFRESH_STALL 24
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`define DDR_NEEDREFRESH 23
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`define DDR_RFTIMER 22
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`define DDR_RFBEGIN 21
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//
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`define DDR_CMDLEN 21
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`define DDR_CSBIT 20
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`define DDR_RASBIT 19
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`define DDR_CASBIT 18
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`define DDR_WEBIT 17
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`define DDR_NOPTIMER 16 // Steal this from BA bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_ADDR_BITS 14
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//
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dgisselq |
//
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dgisselq |
module wbddrsdram(i_clk, i_reset,
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dgisselq |
// Wishbone inputs
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_sel,
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// Wishbone outputs
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o_wb_ack, o_wb_stall, o_wb_data,
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// Memory command wires
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o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
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o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_cmd_c, o_ddr_cmd_d,
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// And the data wires to go with them ....
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o_ddr_data, i_ddr_data, o_bus);
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// These parameters are not really meant for adjusting from the
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// top level. These are more internal variables, recorded here
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// so that things can be automatically adjusted without much
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// problem.
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dgisselq |
parameter CKRP = 0;
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parameter BUSNOW = 2, BUSREG = BUSNOW-1;
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// The commands (above) include (in this order):
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// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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// o_ddr_dqs, o_ddr_dm, o_ddr_odt
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input i_clk, // *MUST* be at 200 MHz for this to work
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i_reset;
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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// The bus address needs to identify a single 128-bit word of interest
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input [23:0] i_wb_addr;
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input [127:0] i_wb_data;
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input [15:0] i_wb_sel;
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dgisselq |
// Wishbone responses/outputs
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output reg o_wb_ack, o_wb_stall;
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output reg [127:0] o_wb_data;
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// DDR memory command wires
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output reg o_ddr_reset_n, o_ddr_cke;
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output reg [1:0] o_ddr_bus_oe;
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dgisselq |
// CMDs are:
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// 4 bits of CS, RAS, CAS, WE
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// 3 bits of bank
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// 14 bits of Address
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// 1 bit of DQS (strobe active, or not)
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// 4 bits of mask (one per byte)
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// 1 bit of ODT
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// ----
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// 27 bits total
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dgisselq |
output wire [26:0] o_ddr_cmd_a, o_ddr_cmd_b,
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o_ddr_cmd_c, o_ddr_cmd_d;
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output reg [127:0] o_ddr_data;
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input [127:0] i_ddr_data;
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output reg o_bus;
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reg [2:0] cmd_pipe;
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reg [1:0] nxt_pipe;
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dgisselq |
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always @(posedge i_clk)
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o_bus <= (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall);
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dgisselq |
//////////
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dgisselq |
//
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//
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dgisselq |
// Reset Logic
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dgisselq |
//
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//
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dgisselq |
//////////
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//
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//
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dgisselq |
// Reset logic should be simple, and is given as follows:
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// memory: reset_address. Each memory location provides either a "command" to
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// timer commands indicate whether or not the command during the timer is to
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// be set to idle, or whether the command is instead left as it was.
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dgisselq |
reg reset_override, reset_ztimer, maintenance_override;
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reg [3:0] reset_address;
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd_a, cmd_b, cmd_c, cmd_d,
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refresh_cmd, maintenance_cmd;
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dgisselq |
reg [24:0] reset_instruction;
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reg [16:0] reset_timer;
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reg r_move;
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initial reset_override = 1'b1;
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initial reset_address = 4'h0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_override <= 1'b1;
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reset_cmd <= { `DDR_NOOP, reset_instruction[16:0]};
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end else if ((reset_ztimer)&&(reset_override))
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dgisselq |
begin
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if (reset_instruction[`DDR_RSTDONE])
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reset_override <= 1'b0;
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reset_cmd <= reset_instruction[20:0];
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end
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dgisselq |
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dgisselq |
initial reset_ztimer = 1'b0; // Is the timer zero?
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initial reset_timer = 17'h02;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= 17'd2;
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end else if (!reset_ztimer)
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begin
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reset_ztimer <= (reset_timer == 17'h01);
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reset_timer <= reset_timer - 17'h01;
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end else if (reset_instruction[`DDR_RSTTIMER])
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= reset_instruction[16:0];
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end
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dgisselq |
wire [16:0] w_ckXPR, w_ckRFC_first;
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wire [13:0] w_MR0, w_MR1, w_MR2;
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dgisselq |
assign w_MR0 = 14'h0210;
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assign w_MR1 = 14'h0044;
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assign w_MR2 = 14'h0040;
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assign w_ckXPR = 17'd12; // Table 68, p186: 56 nCK / 4 sys clks= 14(-2)
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assign w_ckRFC_first = 17'd11; // i.e. 52 nCK, or ckREFI
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dgisselq |
always @(posedge i_clk)
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// DONE, TIMER, RESET, CKE,
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dgisselq |
if (i_reset)
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reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
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dgisselq |
// 1. Reset asserted (active low) for 200 us. (@80MHz)
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4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd16_000 };
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dgisselq |
// 2. Reset de-asserted, wait 500 us before asserting CKE
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dgisselq |
4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd40_000 };
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// 3. Assert CKE, wait minimum of Reset CKE Exit time
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dgisselq |
4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
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dgisselq |
// 4. Set MR2. (4 nCK, no TIMER, but needs a NOOP cycle)
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dgisselq |
4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };
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dgisselq |
// 5. Set MR1. (4 nCK, no TIMER, but needs a NOOP cycle)
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dgisselq |
4'h4: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };
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dgisselq |
// 6. Set MR0
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dgisselq |
4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };
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// 7. Wait 12 nCK clocks, or 3 sys clocks
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4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd1 };
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dgisselq |
// 8. Issue a ZQCL command to start ZQ calibration, A10 is high
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dgisselq |
4'h7: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
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dgisselq |
//11.Wait for both tDLLK and tZQinit completed, both are
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// 512 cks. Of course, since every one of these commands takes
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dgisselq |
// two clocks, we wait for one quarter as many clocks (minus
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// two for our timer logic)
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4'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd126 };
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dgisselq |
// 12. Precharge all command
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dgisselq |
4'h9: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
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// 13. Wait 5 memory clocks (8 memory clocks) for the precharge
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// to complete. A single NOOP here will have us waiting
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// 8 clocks, so we should be good here.
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4'ha: reset_instruction <= { 4'h3, `DDR_NOOP, 17'd0 };
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dgisselq |
// 14. A single Auto Refresh commands
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dgisselq |
4'hb: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
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dgisselq |
// 15. Wait for the auto refresh to complete
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dgisselq |
4'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
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4'hd: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd3 };
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dgisselq |
default:
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dgisselq |
reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
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dgisselq |
endcase
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dgisselq |
initial reset_address = 4'h0;
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dgisselq |
always @(posedge i_clk)
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if (i_reset)
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dgisselq |
reset_address <= 4'h0;
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else if ((reset_ztimer)&&(reset_override)&&(!reset_instruction[`DDR_RSTDONE]))
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reset_address <= reset_address + 4'h1;
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dgisselq |
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//////////
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dgisselq |
//
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dgisselq |
//
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// Refresh Logic
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//
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//
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//////////
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//
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//
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//
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// Okay, let's investigate when we need to do a refresh. Our plan will be to
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// do a single refreshes every tREFI seconds. We will not push off refreshes,
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// nor pull them in--for simplicity. tREFI = 7.8us, but it is a parameter
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dgisselq |
// in the number of clocks (2496 nCK). In our case, 7.8us / 12.5ns = 624 clocks
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// (not nCK!)
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dgisselq |
//
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// Note that 160ns are needed between refresh commands (JEDEC, p172), or
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262 |
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dgisselq |
// 52 clocks @320MHz. After this time, no more refreshes will be needed for
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// (2496-52) clocks (@ 320 MHz), or (624-13) clocks (@80MHz).
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dgisselq |
//
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// This logic is very similar to the refresh logic, both use a memory as a
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// script.
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//
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268 |
18 |
dgisselq |
reg need_refresh, pre_refresh_stall;
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269 |
16 |
dgisselq |
reg refresh_ztimer;
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reg [16:0] refresh_counter;
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reg [2:0] refresh_addr;
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18 |
dgisselq |
reg [24:0] refresh_instruction;
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16 |
dgisselq |
always @(posedge i_clk)
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if (reset_override)
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18 |
dgisselq |
refresh_addr <= 3'h0;
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16 |
dgisselq |
else if (refresh_ztimer)
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refresh_addr <= refresh_addr + 3'h1;
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else if (refresh_instruction[`DDR_RFBEGIN])
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refresh_addr <= 3'h0;
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2 |
dgisselq |
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281 |
16 |
dgisselq |
always @(posedge i_clk)
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if (reset_override)
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begin
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284 |
18 |
dgisselq |
refresh_ztimer <= 1'b0;
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refresh_counter <= 17'd4;
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286 |
16 |
dgisselq |
end else if (!refresh_ztimer)
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begin
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refresh_ztimer <= (refresh_counter == 17'h1);
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289 |
|
|
refresh_counter <= (refresh_counter - 17'h1);
|
290 |
|
|
end else if (refresh_instruction[`DDR_RFTIMER])
|
291 |
|
|
begin
|
292 |
|
|
refresh_ztimer <= 1'b0;
|
293 |
|
|
refresh_counter <= refresh_instruction[16:0];
|
294 |
|
|
end
|
295 |
2 |
dgisselq |
|
296 |
16 |
dgisselq |
wire [16:0] w_ckREFI;
|
297 |
|
|
assign w_ckREFI = 17'd1560; // == 6240/4
|
298 |
|
|
|
299 |
|
|
wire [16:0] w_ckREFI_left, w_ckRFC_nxt, w_wait_for_idle,
|
300 |
18 |
dgisselq |
w_pre_stall_counts;
|
301 |
16 |
dgisselq |
|
302 |
|
|
// We need to wait for the bus to become idle from whatever state
|
303 |
|
|
// it is in. The difficult time for this measurement is assuming
|
304 |
|
|
// a write was just given. In that case, we need to wait for the
|
305 |
|
|
// write to complete, and then to wait an additional tWR (write
|
306 |
|
|
// recovery time) or 6 nCK clocks from the end of the write. This
|
307 |
|
|
// works out to seven idle bus cycles from the time of the write
|
308 |
|
|
// command, or a count of 5 (7-2).
|
309 |
18 |
dgisselq |
assign w_pre_stall_counts = 17'd3; //
|
310 |
|
|
assign w_wait_for_idle = 17'd0; //
|
311 |
|
|
assign w_ckREFI_left[16:0] = 17'd624 // The full interval
|
312 |
|
|
-17'd13 // Minus what we've already waited
|
313 |
16 |
dgisselq |
-w_wait_for_idle
|
314 |
18 |
dgisselq |
-17'd19;
|
315 |
|
|
assign w_ckRFC_nxt[16:0] = 17'd12-17'd3;
|
316 |
16 |
dgisselq |
|
317 |
|
|
always @(posedge i_clk)
|
318 |
18 |
dgisselq |
if (reset_override)
|
319 |
|
|
refresh_instruction <= { 4'h2, `DDR_NOOP, 17'd1 };
|
320 |
|
|
else if (refresh_ztimer)
|
321 |
16 |
dgisselq |
case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
|
322 |
|
|
// First, a number of clocks needing no refresh
|
323 |
18 |
dgisselq |
3'h0: refresh_instruction <= { 4'h2, `DDR_NOOP, w_ckREFI_left };
|
324 |
16 |
dgisselq |
// Then, we take command of the bus and wait for it to be
|
325 |
|
|
// guaranteed idle
|
326 |
18 |
dgisselq |
3'h1: refresh_instruction <= { 4'ha, `DDR_NOOP, w_pre_stall_counts };
|
327 |
|
|
3'h2: refresh_instruction <= { 4'hc, `DDR_NOOP, w_wait_for_idle };
|
328 |
16 |
dgisselq |
// Once the bus is idle, all commands complete, and a minimum
|
329 |
|
|
// recovery time given, we can issue a precharge all command
|
330 |
18 |
dgisselq |
3'h3: refresh_instruction <= { 4'hc, `DDR_PRECHARGE, 17'h0400 };
|
331 |
16 |
dgisselq |
// Now we need to wait tRP = 3 clocks (6 nCK)
|
332 |
18 |
dgisselq |
3'h4: refresh_instruction <= { 4'hc, `DDR_NOOP, 17'h00 };
|
333 |
|
|
3'h5: refresh_instruction <= { 4'hc, `DDR_REFRESH, 17'h00 };
|
334 |
|
|
3'h6: refresh_instruction <= { 4'he, `DDR_NOOP, w_ckRFC_nxt };
|
335 |
|
|
3'h7: refresh_instruction <= { 4'h2, `DDR_NOOP, 17'd12 };
|
336 |
|
|
// default:
|
337 |
|
|
// refresh_instruction <= { 4'h1, `DDR_NOOP, 17'h00 };
|
338 |
16 |
dgisselq |
endcase
|
339 |
|
|
|
340 |
|
|
// Note that we don't need to check if (reset_override) here since
|
341 |
|
|
// refresh_ztimer will always be true if (reset_override)--in other
|
342 |
|
|
// words, it will be true for many, many, clocks--enough for this
|
343 |
|
|
// logic to settle out.
|
344 |
|
|
always @(posedge i_clk)
|
345 |
|
|
if (refresh_ztimer)
|
346 |
|
|
refresh_cmd <= refresh_instruction[20:0];
|
347 |
|
|
always @(posedge i_clk)
|
348 |
|
|
if (refresh_ztimer)
|
349 |
|
|
need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
|
350 |
18 |
dgisselq |
always @(posedge i_clk)
|
351 |
|
|
if (refresh_ztimer)
|
352 |
|
|
pre_refresh_stall <= refresh_instruction[`DDR_PREREFRESH_STALL];
|
353 |
16 |
dgisselq |
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
reg [1:0] drive_dqs;
|
357 |
|
|
// Our chosen timing doesn't require any more resolution than one
|
358 |
|
|
// bus clock for ODT. (Of course, this really isn't necessary, since
|
359 |
|
|
// we aren't using ODT as per the MRx registers ... but we keep it
|
360 |
|
|
// around in case we change our minds later.)
|
361 |
18 |
dgisselq |
reg [15:0] ddr_dm;
|
362 |
16 |
dgisselq |
|
363 |
|
|
// The pending transaction
|
364 |
18 |
dgisselq |
reg [127:0] r_data;
|
365 |
16 |
dgisselq |
reg r_pending, r_we;
|
366 |
|
|
reg [13:0] r_row;
|
367 |
|
|
reg [2:0] r_bank;
|
368 |
|
|
reg [9:0] r_col;
|
369 |
18 |
dgisselq |
reg [15:0] r_sel;
|
370 |
16 |
dgisselq |
|
371 |
|
|
// The pending transaction, one further into the pipeline. This is
|
372 |
|
|
// the stage where the read/write command is actually given to the
|
373 |
|
|
// interface if we haven't stalled.
|
374 |
18 |
dgisselq |
reg [127:0] s_data;
|
375 |
|
|
reg s_pending, s_we;
|
376 |
16 |
dgisselq |
reg [13:0] s_row, s_nxt_row;
|
377 |
|
|
reg [2:0] s_bank, s_nxt_bank;
|
378 |
|
|
reg [9:0] s_col;
|
379 |
18 |
dgisselq |
reg [15:0] s_sel;
|
380 |
16 |
dgisselq |
|
381 |
|
|
// Can we preload the next bank?
|
382 |
|
|
reg [13:0] r_nxt_row;
|
383 |
|
|
reg [2:0] r_nxt_bank;
|
384 |
|
|
|
385 |
|
|
reg need_close_bank, need_close_this_bank,
|
386 |
|
|
last_close_bank, maybe_close_next_bank,
|
387 |
|
|
last_maybe_close,
|
388 |
|
|
need_open_bank, last_open_bank, maybe_open_next_bank,
|
389 |
|
|
last_maybe_open,
|
390 |
|
|
valid_bank;
|
391 |
|
|
reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd,
|
392 |
|
|
maybe_close_cmd, maybe_open_cmd, rw_cmd;
|
393 |
|
|
reg rw_we;
|
394 |
|
|
|
395 |
|
|
wire w_this_closing_bank, w_this_opening_bank,
|
396 |
|
|
w_this_maybe_close, w_this_maybe_open,
|
397 |
|
|
w_this_rw_move;
|
398 |
|
|
reg last_closing_bank, last_opening_bank;
|
399 |
|
|
wire w_need_close_this_bank, w_need_open_bank,
|
400 |
18 |
dgisselq |
w_r_valid, w_s_valid;
|
401 |
16 |
dgisselq |
|
402 |
|
|
//////////
|
403 |
2 |
dgisselq |
//
|
404 |
|
|
//
|
405 |
16 |
dgisselq |
// Open Banks
|
406 |
|
|
//
|
407 |
|
|
//
|
408 |
|
|
//////////
|
409 |
|
|
//
|
410 |
|
|
//
|
411 |
|
|
//
|
412 |
2 |
dgisselq |
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
413 |
|
|
//
|
414 |
18 |
dgisselq |
// A precharge requires 1 clocks at 80MHz to complete.
|
415 |
|
|
// An activate also requires 1 clocks at 80MHz to complete.
|
416 |
|
|
// By the time we log these, they will be complete.
|
417 |
16 |
dgisselq |
// Precharges are not allowed until the maximum of:
|
418 |
|
|
// 2 clocks (200 MHz) after a read command
|
419 |
18 |
dgisselq |
// 4 clocks after a write command
|
420 |
2 |
dgisselq |
//
|
421 |
|
|
//
|
422 |
3 |
dgisselq |
wire w_precharge_all;
|
423 |
16 |
dgisselq |
reg [CKRP:0] bank_status [0:7];
|
424 |
6 |
dgisselq |
reg [13:0] bank_address [0:7];
|
425 |
18 |
dgisselq |
reg [1:0] bank_wr_ck [0:7]; // tWTR
|
426 |
12 |
dgisselq |
reg bank_wr_ckzro [0:7]; // tWTR
|
427 |
18 |
dgisselq |
wire [7:0] bank_open;
|
428 |
|
|
wire [7:0] bank_closed;
|
429 |
6 |
dgisselq |
|
430 |
18 |
dgisselq |
wire [1:0] write_recycle_clocks;
|
431 |
|
|
assign write_recycle_clocks = 2'h3;
|
432 |
12 |
dgisselq |
|
433 |
18 |
dgisselq |
genvar k;
|
434 |
|
|
generate
|
435 |
|
|
for(k=0; k<8; k=k+1)
|
436 |
|
|
assign bank_open[k] = bank_status[k][0];
|
437 |
|
|
for(k=0; k<8; k=k+1)
|
438 |
|
|
assign bank_closed[k] = !bank_status[k][0];
|
439 |
|
|
endgenerate
|
440 |
|
|
|
441 |
16 |
dgisselq |
initial bank_open = 0;
|
442 |
14 |
dgisselq |
initial bank_closed = 8'hff;
|
443 |
2 |
dgisselq |
always @(posedge i_clk)
|
444 |
|
|
begin
|
445 |
18 |
dgisselq |
bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-2'h1):2'h0;
|
446 |
|
|
bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-2'h1):2'h0;
|
447 |
|
|
bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-2'h1):2'h0;
|
448 |
|
|
bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-2'h1):2'h0;
|
449 |
|
|
bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-2'h1):2'h0;
|
450 |
|
|
bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-2'h1):2'h0;
|
451 |
|
|
bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-2'h1):2'h0;
|
452 |
|
|
bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-2'h1):2'h0;
|
453 |
12 |
dgisselq |
|
454 |
18 |
dgisselq |
bank_wr_ckzro[0] <= (bank_wr_ck[0][1]==1'b0);
|
455 |
|
|
bank_wr_ckzro[1] <= (bank_wr_ck[1][1]==1'b0);
|
456 |
|
|
bank_wr_ckzro[2] <= (bank_wr_ck[2][1]==1'b0);
|
457 |
|
|
bank_wr_ckzro[3] <= (bank_wr_ck[3][1]==1'b0);
|
458 |
|
|
bank_wr_ckzro[4] <= (bank_wr_ck[4][1]==1'b0);
|
459 |
|
|
bank_wr_ckzro[5] <= (bank_wr_ck[5][1]==1'b0);
|
460 |
|
|
bank_wr_ckzro[6] <= (bank_wr_ck[6][1]==1'b0);
|
461 |
|
|
bank_wr_ckzro[7] <= (bank_wr_ck[7][1]==1'b0);
|
462 |
12 |
dgisselq |
|
463 |
18 |
dgisselq |
// bank_open[0] <= (bank_status[0][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
464 |
|
|
// bank_open[1] <= (bank_status[1][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
465 |
|
|
// bank_open[2] <= (bank_status[2][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
466 |
|
|
// bank_open[3] <= (bank_status[3][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
467 |
|
|
// bank_open[4] <= (bank_status[4][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
468 |
|
|
// bank_open[5] <= (bank_status[5][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
469 |
|
|
// bank_open[6] <= (bank_status[6][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
470 |
|
|
// bank_open[7] <= (bank_status[7][(CKRP-2):0] =={(CKRP-1){1'b1}});
|
471 |
12 |
dgisselq |
|
472 |
18 |
dgisselq |
// bank_closed[0] <= (bank_status[0][(CKRP-3):0] == 0);
|
473 |
|
|
// bank_closed[1] <= (bank_status[1][(CKRP-3):0] == 0);
|
474 |
|
|
// bank_closed[2] <= (bank_status[2][(CKRP-3):0] == 0);
|
475 |
|
|
// bank_closed[3] <= (bank_status[3][(CKRP-3):0] == 0);
|
476 |
|
|
// bank_closed[4] <= (bank_status[4][(CKRP-3):0] == 0);
|
477 |
|
|
// bank_closed[5] <= (bank_status[5][(CKRP-3):0] == 0);
|
478 |
|
|
// bank_closed[6] <= (bank_status[6][(CKRP-3):0] == 0);
|
479 |
|
|
// bank_closed[7] <= (bank_status[7][(CKRP-3):0] == 0);
|
480 |
14 |
dgisselq |
|
481 |
12 |
dgisselq |
if (w_this_rw_move)
|
482 |
18 |
dgisselq |
bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 2'h0
|
483 |
12 |
dgisselq |
: write_recycle_clocks;
|
484 |
|
|
|
485 |
18 |
dgisselq |
if (cmd_pipe[0])
|
486 |
|
|
begin
|
487 |
|
|
bank_status[s_bank] <= 1'b0;
|
488 |
|
|
if (nxt_pipe[1])
|
489 |
|
|
bank_status[s_nxt_bank] <= 1'b1;
|
490 |
|
|
end else begin
|
491 |
|
|
if (cmd_pipe[1])
|
492 |
|
|
bank_status[s_bank] <= 1'b1;
|
493 |
|
|
else if (nxt_pipe[1])
|
494 |
|
|
bank_status[s_nxt_bank] <= 1'b1;
|
495 |
|
|
if (nxt_pipe[0])
|
496 |
|
|
bank_status[s_nxt_bank] <= 1'b0;
|
497 |
|
|
end
|
498 |
|
|
|
499 |
14 |
dgisselq |
if (maintenance_override)
|
500 |
2 |
dgisselq |
begin
|
501 |
18 |
dgisselq |
bank_status[0] <= 1'b0;
|
502 |
|
|
bank_status[1] <= 1'b0;
|
503 |
|
|
bank_status[2] <= 1'b0;
|
504 |
|
|
bank_status[3] <= 1'b0;
|
505 |
|
|
bank_status[4] <= 1'b0;
|
506 |
|
|
bank_status[5] <= 1'b0;
|
507 |
|
|
bank_status[6] <= 1'b0;
|
508 |
|
|
bank_status[7] <= 1'b0;
|
509 |
2 |
dgisselq |
end
|
510 |
18 |
dgisselq |
|
511 |
2 |
dgisselq |
end
|
512 |
|
|
|
513 |
|
|
always @(posedge i_clk)
|
514 |
18 |
dgisselq |
if (cmd_pipe[1])
|
515 |
|
|
bank_address[s_bank] <= s_row;
|
516 |
|
|
else if (nxt_pipe[1])
|
517 |
|
|
bank_address[s_nxt_bank] <= s_nxt_row;
|
518 |
2 |
dgisselq |
|
519 |
16 |
dgisselq |
|
520 |
|
|
//////////
|
521 |
2 |
dgisselq |
//
|
522 |
|
|
//
|
523 |
16 |
dgisselq |
// Data BUS information
|
524 |
2 |
dgisselq |
//
|
525 |
|
|
//
|
526 |
16 |
dgisselq |
//////////
|
527 |
2 |
dgisselq |
//
|
528 |
|
|
//
|
529 |
16 |
dgisselq |
// Our purpose here is to keep track of when the data bus will be
|
530 |
|
|
// active. This is separate from the FIFO which will contain the
|
531 |
|
|
// data to be placed on the bus (when so placed), in that this is
|
532 |
|
|
// a group of shift registers--every position has a location in time,
|
533 |
|
|
// and time always moves forward. The FIFO, on the other hand, only
|
534 |
|
|
// moves forward when data moves onto the bus.
|
535 |
2 |
dgisselq |
//
|
536 |
|
|
//
|
537 |
16 |
dgisselq |
|
538 |
18 |
dgisselq |
reg [BUSNOW:0] bus_active, bus_read, bus_ack;
|
539 |
|
|
reg [BUSNOW:0] bus_subaddr;
|
540 |
3 |
dgisselq |
initial bus_active = 0;
|
541 |
14 |
dgisselq |
initial bus_ack = 0;
|
542 |
2 |
dgisselq |
always @(posedge i_clk)
|
543 |
|
|
begin
|
544 |
16 |
dgisselq |
bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };
|
545 |
|
|
// Drive the d-bus?
|
546 |
|
|
bus_read[BUSNOW:0] <= { bus_read[(BUSNOW-1):0], 1'b0 };
|
547 |
13 |
dgisselq |
// Will this position on the bus get a wishbone acknowledgement?
|
548 |
16 |
dgisselq |
bus_ack[BUSNOW:0] <= { bus_ack[(BUSNOW-1):0], 1'b0 };
|
549 |
|
|
//
|
550 |
|
|
bus_subaddr[BUSNOW:0] <= { bus_subaddr[(BUSNOW-1):0], 1'b1 };
|
551 |
13 |
dgisselq |
|
552 |
18 |
dgisselq |
if (cmd_pipe[2])
|
553 |
2 |
dgisselq |
begin
|
554 |
18 |
dgisselq |
bus_active[0]<= 1'b1; // Data transfers in one clocks
|
555 |
|
|
bus_ack[0] <= 1'b1;
|
556 |
|
|
bus_ack[0] <= 1'b1;
|
557 |
4 |
dgisselq |
|
558 |
18 |
dgisselq |
bus_read[0] <= !(rw_we);
|
559 |
2 |
dgisselq |
end
|
560 |
|
|
end
|
561 |
|
|
|
562 |
|
|
//
|
563 |
|
|
//
|
564 |
|
|
// Now, let's see, can we issue a read command?
|
565 |
|
|
//
|
566 |
|
|
//
|
567 |
18 |
dgisselq |
wire pre_valid;
|
568 |
|
|
assign pre_valid = !maintenance_override;
|
569 |
14 |
dgisselq |
|
570 |
18 |
dgisselq |
reg pipe_stall;
|
571 |
14 |
dgisselq |
assign w_r_valid = (pre_valid)&&(r_pending)
|
572 |
18 |
dgisselq |
&&(bank_status[r_bank][0])
|
573 |
14 |
dgisselq |
&&(bank_address[r_bank]==r_row)
|
574 |
|
|
&&((r_we)||(bank_wr_ckzro[r_bank]));
|
575 |
18 |
dgisselq |
assign w_s_valid = ((pre_valid)&&(s_pending)&&(pipe_stall)
|
576 |
|
|
&&(bank_status[s_bank][0])
|
577 |
14 |
dgisselq |
&&(bank_address[s_bank]==s_row)
|
578 |
18 |
dgisselq |
&&((s_we)||(bank_wr_ckzro[s_bank])));
|
579 |
14 |
dgisselq |
|
580 |
2 |
dgisselq |
always @(posedge i_clk)
|
581 |
|
|
begin
|
582 |
9 |
dgisselq |
r_pending <= (i_wb_stb)&&(~o_wb_stall)
|
583 |
|
|
||(r_pending)&&(pipe_stall);
|
584 |
|
|
if (~pipe_stall)
|
585 |
|
|
s_pending <= r_pending;
|
586 |
|
|
if (~pipe_stall)
|
587 |
2 |
dgisselq |
begin
|
588 |
18 |
dgisselq |
if (r_pending)
|
589 |
|
|
begin
|
590 |
|
|
pipe_stall <= 1'b1;
|
591 |
|
|
o_wb_stall <= 1'b1;
|
592 |
|
|
if (!bank_status[r_bank][0])
|
593 |
|
|
cmd_pipe <= 3'b010;
|
594 |
|
|
else if (bank_address[r_bank] != r_row)
|
595 |
|
|
cmd_pipe <= 3'b001; // Read in two clocks
|
596 |
|
|
else begin
|
597 |
|
|
cmd_pipe <= 3'b100; // Read now
|
598 |
|
|
pipe_stall <= 1'b0;
|
599 |
|
|
o_wb_stall <= 1'b0;
|
600 |
|
|
end
|
601 |
|
|
|
602 |
|
|
if (!bank_status[r_nxt_bank][0])
|
603 |
|
|
nxt_pipe <= 2'b10;
|
604 |
|
|
else if (bank_address[r_nxt_bank] != r_row)
|
605 |
|
|
nxt_pipe <= 2'b01; // Read in two clocks
|
606 |
|
|
else
|
607 |
|
|
nxt_pipe <= 2'b00; // Next is ready
|
608 |
|
|
if (nxt_pipe[1])
|
609 |
|
|
nxt_pipe[1] <= 1'b0;
|
610 |
|
|
end else begin
|
611 |
|
|
cmd_pipe <= 3'b000;
|
612 |
|
|
nxt_pipe <= { nxt_pipe[0], 1'b0 };
|
613 |
|
|
pipe_stall <= 1'b0;
|
614 |
|
|
o_wb_stall <= 1'b0;
|
615 |
|
|
end
|
616 |
9 |
dgisselq |
end else begin // if (pipe_stall)
|
617 |
18 |
dgisselq |
pipe_stall <= (s_pending)&&(cmd_pipe[0]);
|
618 |
|
|
o_wb_stall <= (s_pending)&&(cmd_pipe[0]);
|
619 |
|
|
cmd_pipe <= { cmd_pipe[1:0], 1'b0 };
|
620 |
|
|
|
621 |
|
|
nxt_pipe[0] <= (cmd_pipe[0])&&(nxt_pipe[0]);
|
622 |
|
|
nxt_pipe[1] <= ((cmd_pipe[0])&&(nxt_pipe[0])) ? 1'b0
|
623 |
|
|
: ((cmd_pipe[1])?(|nxt_pipe[1:0]) : nxt_pipe[0]);
|
624 |
9 |
dgisselq |
end
|
625 |
18 |
dgisselq |
if (pre_refresh_stall)
|
626 |
2 |
dgisselq |
o_wb_stall <= 1'b1;
|
627 |
|
|
|
628 |
9 |
dgisselq |
if (~pipe_stall)
|
629 |
2 |
dgisselq |
begin
|
630 |
|
|
r_we <= i_wb_we;
|
631 |
|
|
r_data <= i_wb_data;
|
632 |
18 |
dgisselq |
r_row <= i_wb_addr[23:10]; // 14 bits row address
|
633 |
|
|
r_bank <= i_wb_addr[9:7];
|
634 |
|
|
r_col <= { i_wb_addr[6:0], 3'b000 }; // 10 bits Caddr
|
635 |
16 |
dgisselq |
r_sel <= i_wb_sel;
|
636 |
2 |
dgisselq |
|
637 |
16 |
dgisselq |
// i_wb_addr[0] is the 8-bit byte selector of 16-bits (ignored)
|
638 |
|
|
// i_wb_addr[1] is the 16-bit half-word selector of 32-bits (ignored)
|
639 |
|
|
// i_wb_addr[2] is the 32-bit word selector of 64-bits (ignored)
|
640 |
|
|
// i_wb_addr[3] is the 64-bit long word selector of 128-bits
|
641 |
|
|
|
642 |
2 |
dgisselq |
// pre-emptive work
|
643 |
18 |
dgisselq |
r_nxt_row <= (i_wb_addr[9:7]==3'h7)
|
644 |
|
|
? (i_wb_addr[23:10]+14'h1)
|
645 |
|
|
: i_wb_addr[23:10];
|
646 |
|
|
r_nxt_bank <= i_wb_addr[9:7]+3'h1;
|
647 |
2 |
dgisselq |
end
|
648 |
9 |
dgisselq |
|
649 |
|
|
if (~pipe_stall)
|
650 |
|
|
begin
|
651 |
|
|
// Moving one down the pipeline
|
652 |
|
|
s_we <= r_we;
|
653 |
|
|
s_data <= r_data;
|
654 |
|
|
s_row <= r_row;
|
655 |
|
|
s_bank <= r_bank;
|
656 |
|
|
s_col <= r_col;
|
657 |
18 |
dgisselq |
s_sel <= (r_we)?(~r_sel):16'h00;
|
658 |
9 |
dgisselq |
|
659 |
|
|
// pre-emptive work
|
660 |
|
|
s_nxt_row <= r_nxt_row;
|
661 |
|
|
s_nxt_bank <= r_nxt_bank;
|
662 |
|
|
end
|
663 |
2 |
dgisselq |
end
|
664 |
|
|
|
665 |
18 |
dgisselq |
wire [2:0] this_bank;
|
666 |
|
|
wire [13:0] this_row;
|
667 |
|
|
wire [9:0] this_col;
|
668 |
|
|
assign this_bank = (pipe_stall)?s_bank : r_bank;
|
669 |
|
|
assign this_row = (pipe_stall)?s_row : r_row;
|
670 |
|
|
assign this_col = (pipe_stall)?s_col : r_col;
|
671 |
3 |
dgisselq |
|
672 |
18 |
dgisselq |
assign w_need_close_this_bank = (cmd_pipe == 3'b000);
|
673 |
|
|
wire w_this_bank_valid;
|
674 |
|
|
assign w_this_bank_valid = (cmd_pipe[2]);
|
675 |
2 |
dgisselq |
|
676 |
|
|
//
|
677 |
|
|
//
|
678 |
|
|
// Okay, let's look at the last assignment in our chain. It should look
|
679 |
|
|
// something like:
|
680 |
|
|
always @(posedge i_clk)
|
681 |
4 |
dgisselq |
if (i_reset)
|
682 |
|
|
o_ddr_reset_n <= 1'b0;
|
683 |
|
|
else if (reset_ztimer)
|
684 |
|
|
o_ddr_reset_n <= reset_instruction[`DDR_RSTBIT];
|
685 |
2 |
dgisselq |
always @(posedge i_clk)
|
686 |
4 |
dgisselq |
if (i_reset)
|
687 |
|
|
o_ddr_cke <= 1'b0;
|
688 |
|
|
else if (reset_ztimer)
|
689 |
|
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
690 |
6 |
dgisselq |
|
691 |
9 |
dgisselq |
always @(posedge i_clk)
|
692 |
|
|
if (i_reset)
|
693 |
|
|
maintenance_override <= 1'b1;
|
694 |
|
|
else
|
695 |
|
|
maintenance_override <= (reset_override)||(need_refresh);
|
696 |
7 |
dgisselq |
|
697 |
9 |
dgisselq |
initial maintenance_cmd = { `DDR_NOOP, 17'h00 };
|
698 |
|
|
always @(posedge i_clk)
|
699 |
|
|
if (i_reset)
|
700 |
|
|
maintenance_cmd <= { `DDR_NOOP, 17'h00 };
|
701 |
|
|
else
|
702 |
|
|
maintenance_cmd <= (reset_override)?reset_cmd:refresh_cmd;
|
703 |
|
|
|
704 |
18 |
dgisselq |
assign w_need_open_bank = ((r_pending)||(s_pending))
|
705 |
|
|
&&(bank_closed[this_bank])
|
706 |
|
|
||((pipe_stall)&&(!cmd_b[20]));
|
707 |
|
|
|
708 |
|
|
assign w_this_closing_bank = (!maintenance_override)&&(cmd_pipe[0]);
|
709 |
|
|
assign w_this_opening_bank = (!maintenance_override)&&(cmd_pipe[1]);
|
710 |
|
|
assign w_this_rw_move = (!maintenance_override)&&(cmd_pipe[2]);
|
711 |
|
|
assign w_this_maybe_close = (!maintenance_override)&&(!cmd_pipe[0])&&(nxt_pipe[0]);
|
712 |
|
|
assign w_this_maybe_open = (!maintenance_override)&&(!cmd_pipe[1])&&(nxt_pipe[1]);
|
713 |
|
|
reg [2:0] r_odt;
|
714 |
|
|
|
715 |
2 |
dgisselq |
always @(posedge i_clk)
|
716 |
|
|
begin
|
717 |
6 |
dgisselq |
last_opening_bank <= 1'b0;
|
718 |
|
|
last_closing_bank <= 1'b0;
|
719 |
|
|
last_maybe_open <= 1'b0;
|
720 |
|
|
last_maybe_close <= 1'b0;
|
721 |
16 |
dgisselq |
|
722 |
18 |
dgisselq |
|
723 |
|
|
// We run our commands by timeslots, A, B, C, and D in that
|
724 |
|
|
// order.
|
725 |
|
|
|
726 |
|
|
// Timeslot A always contains any maintenance commands we might
|
727 |
|
|
// have.
|
728 |
|
|
// Timeslot B always contains any precharge command, excluding
|
729 |
|
|
// the maintenance precharge-all command.
|
730 |
|
|
// Timeslot C always contains any activate command
|
731 |
|
|
// Timeslot D always contains any read/write command
|
732 |
|
|
//
|
733 |
|
|
// We can always set these commands to whatever, to reduce the
|
734 |
|
|
// used logic, as long as the top bit (CS_N) is used to select
|
735 |
|
|
// whether or not the command is active. If CS_N is 0 the
|
736 |
|
|
// command will be applied by the chip, if 1 the command turns
|
737 |
|
|
// into a deselect command that the chip will ignore.
|
738 |
|
|
//
|
739 |
|
|
cmd_a <= maintenance_cmd;
|
740 |
|
|
|
741 |
|
|
cmd_b <= { `DDR_PRECHARGE, s_nxt_bank, s_nxt_row[13:11], 1'b0, s_nxt_row[9:0] };
|
742 |
|
|
cmd_b[20] <= 1'b1; // Deactivate, unless ...
|
743 |
|
|
if (cmd_pipe[0])
|
744 |
|
|
cmd_b <= { `DDR_PRECHARGE, s_bank, s_row[13:11], 1'b0, s_row[9:0] };
|
745 |
|
|
cmd_b[20] <= (!cmd_pipe[0])&&(!nxt_pipe[0]);
|
746 |
|
|
|
747 |
|
|
cmd_c <= { `DDR_ACTIVATE, s_nxt_bank, s_nxt_row[13:11], 1'b0, s_nxt_row[9:0] };
|
748 |
|
|
cmd_c[20] <= 1'b1; // Disable command, unless ...
|
749 |
|
|
if (cmd_pipe[1])
|
750 |
|
|
cmd_c <= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
|
751 |
|
|
else if (nxt_pipe[1])
|
752 |
|
|
cmd_c[20] <= 1'b0;
|
753 |
|
|
|
754 |
|
|
if (cmd_pipe[2])
|
755 |
|
|
begin
|
756 |
|
|
cmd_d[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
|
757 |
|
|
cmd_d[(`DDR_WEBIT-1):0] <= { s_bank, 3'h0, 1'b0, s_col };
|
758 |
|
|
end
|
759 |
|
|
cmd_d[20] <= !(cmd_pipe[2]);
|
760 |
|
|
|
761 |
|
|
|
762 |
|
|
if ((s_pending)&&(pipe_stall))
|
763 |
|
|
rw_we <= s_we;
|
764 |
|
|
else
|
765 |
|
|
rw_we <= r_we;
|
766 |
|
|
|
767 |
|
|
r_odt <= { r_odt[2:1], (cmd_pipe[2])&&(s_we) };
|
768 |
|
|
// cmd_d <= rw_cmd;
|
769 |
|
|
r_move <= (!cmd_pipe[2]);
|
770 |
|
|
|
771 |
|
|
// Now, if the maintenance mode must override whatever we are
|
772 |
|
|
// doing, we only need to apply this more complicated logic
|
773 |
|
|
// to the CS_N bit, or bit[20], since this will activate or
|
774 |
|
|
// deactivate the rest of the command--making the rest
|
775 |
|
|
// either relevant (CS_N=0) or irrelevant (CS_N=1) as we need.
|
776 |
16 |
dgisselq |
if (maintenance_override)
|
777 |
18 |
dgisselq |
begin // Over-ride all commands. Make them deselect commands,
|
778 |
|
|
// save for the maintenance timeslot.
|
779 |
|
|
cmd_a[20] <= 1'b0;
|
780 |
|
|
cmd_b[20] <= 1'b1;
|
781 |
|
|
cmd_c[20] <= 1'b1;
|
782 |
|
|
cmd_d[20] <= 1'b1;
|
783 |
2 |
dgisselq |
end else
|
784 |
18 |
dgisselq |
cmd_a[20] <= 1'b1; // Disable maintenance timeslot
|
785 |
2 |
dgisselq |
end
|
786 |
|
|
|
787 |
18 |
dgisselq |
`define LGFIFOLN 3
|
788 |
|
|
`define FIFOLEN 8
|
789 |
7 |
dgisselq |
reg [(`LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
|
790 |
18 |
dgisselq |
reg [127:0] bus_fifo_data [0:(`FIFOLEN-1)];
|
791 |
|
|
reg [15:0] bus_fifo_sel [0:(`FIFOLEN-1)];
|
792 |
7 |
dgisselq |
reg pre_ack;
|
793 |
3 |
dgisselq |
|
794 |
7 |
dgisselq |
// The bus R/W FIFO
|
795 |
|
|
wire w_bus_fifo_read_next_transaction;
|
796 |
16 |
dgisselq |
assign w_bus_fifo_read_next_transaction = (bus_ack[BUSREG]);
|
797 |
7 |
dgisselq |
always @(posedge i_clk)
|
798 |
|
|
begin
|
799 |
|
|
pre_ack <= 1'b0;
|
800 |
13 |
dgisselq |
if (reset_override)
|
801 |
7 |
dgisselq |
begin
|
802 |
13 |
dgisselq |
bus_fifo_head <= {(`LGFIFOLN){1'b0}};
|
803 |
|
|
bus_fifo_tail <= {(`LGFIFOLN){1'b0}};
|
804 |
7 |
dgisselq |
end else begin
|
805 |
13 |
dgisselq |
if ((s_pending)&&(!pipe_stall))
|
806 |
|
|
bus_fifo_head <= bus_fifo_head + 1'b1;
|
807 |
7 |
dgisselq |
|
808 |
|
|
if (w_bus_fifo_read_next_transaction)
|
809 |
|
|
begin
|
810 |
13 |
dgisselq |
bus_fifo_tail <= bus_fifo_tail + 1'b1;
|
811 |
7 |
dgisselq |
pre_ack <= 1'b1;
|
812 |
|
|
end
|
813 |
|
|
end
|
814 |
9 |
dgisselq |
bus_fifo_data[bus_fifo_head] <= s_data;
|
815 |
16 |
dgisselq |
bus_fifo_sel[bus_fifo_head] <= s_sel;
|
816 |
7 |
dgisselq |
end
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
always @(posedge i_clk)
|
820 |
|
|
o_ddr_data <= bus_fifo_data[bus_fifo_tail];
|
821 |
16 |
dgisselq |
always @(posedge i_clk)
|
822 |
|
|
ddr_dm <= (bus_ack[BUSREG])? bus_fifo_sel[bus_fifo_tail]
|
823 |
18 |
dgisselq |
: ((!bus_read[BUSREG])? 16'hffff: 16'h0000);
|
824 |
16 |
dgisselq |
always @(posedge i_clk)
|
825 |
18 |
dgisselq |
begin
|
826 |
|
|
drive_dqs[1] <= (bus_active[(BUSREG)])
|
827 |
|
|
&&(!bus_read[(BUSREG)]);
|
828 |
|
|
drive_dqs[0] <= (bus_active[BUSREG:(BUSREG-1)] != 2'b00)
|
829 |
|
|
&&(bus_read[BUSREG:(BUSREG-1)] == 2'b00);
|
830 |
|
|
//
|
831 |
|
|
// Is the strobe on during the last clock?
|
832 |
|
|
o_ddr_bus_oe[0] <= (|bus_active[BUSREG:(BUSREG-1)])&&(!bus_read[BUSREG]);
|
833 |
|
|
// Is data transmitting the bus throughout?
|
834 |
|
|
o_ddr_bus_oe[1] <= (bus_active[BUSREG])&&(!bus_read[BUSREG]);
|
835 |
|
|
end
|
836 |
2 |
dgisselq |
|
837 |
18 |
dgisselq |
// First command
|
838 |
|
|
assign o_ddr_cmd_a = { cmd_a, drive_dqs[1], ddr_dm[15:12], drive_dqs[0] };
|
839 |
|
|
// Second command (of four)
|
840 |
|
|
assign o_ddr_cmd_b = { cmd_b, drive_dqs[1], ddr_dm[11: 8], drive_dqs[0] };
|
841 |
|
|
// Third command (of four)
|
842 |
|
|
assign o_ddr_cmd_c = { cmd_c, drive_dqs[1], ddr_dm[ 7: 4], drive_dqs[0] };
|
843 |
|
|
// Fourth command (of four)--occupies the last timeslot
|
844 |
|
|
assign o_ddr_cmd_d = { cmd_d, drive_dqs[0], ddr_dm[ 3: 0], drive_dqs[0] };
|
845 |
2 |
dgisselq |
|
846 |
16 |
dgisselq |
assign w_precharge_all = (cmd_a[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
847 |
|
|
&&(cmd_a[10]);
|
848 |
|
|
|
849 |
13 |
dgisselq |
always @(posedge i_clk)
|
850 |
7 |
dgisselq |
o_wb_ack <= pre_ack;
|
851 |
|
|
always @(posedge i_clk)
|
852 |
|
|
o_wb_data <= i_ddr_data;
|
853 |
4 |
dgisselq |
|
854 |
2 |
dgisselq |
endmodule
|