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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbddrsdram.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Possible commands to the DDR3 memory. These consist of settings for the
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// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
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`define DDR_MRSET 4'b0000
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`define DDR_REFRESH 4'b0001
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`define DDR_PRECHARGE 4'b0010
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`define DDR_ACTIVATE 4'b0011
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`define DDR_WRITE 4'b0100
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`define DDR_READ 4'b0101
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`define DDR_NOOP 4'b0111
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//`define DDR_DESELECT 4'b1???
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//
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// In this controller, 24-bit commands tend to be passed around. These
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// 'commands' are bit fields. Here we specify the bits associated with
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// the bit fields.
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`define DDR_RSTDONE 26
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`define DDR_RSTTIMER 25
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`define DDR_RSTBIT 24
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`define DDR_CKEBIT 23
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`define DDR_CSBIT 22
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`define DDR_RASBIT 21
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`define DDR_CASBIT 20
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`define DDR_WEBIT 19
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_ADDR_BITS 16
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module wbddrsdram(i_clk_200mhz,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stb, o_wb_data,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_dir,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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parameter CKREFI4 = 13'd6240; // 4 * 7.8us at 200 MHz clock
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input i_clk_200mhz;
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [25:0] i_wb_addr;
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input [31:0] i_wb_data;
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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// DDR3 RAM Controller
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output wire o_ddr_reset_n;
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output wire o_ddr_reset_cke;
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// Control outputs
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output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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output reg [2:0] o_ddr_dqs;
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// Address outputs
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output reg [13:0] o_ddr_addr;
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output reg [2:0] o_ddr_ba;
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// And the data inputs and outputs
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output reg [31:0] o_ddr_data;
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input i_ddr_data;
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//
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// tWTR = 7.5
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// tRRD = 7.5
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// tREFI= 7.8
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// tFAW = 45
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// tRTP = 7.5
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// tCKE = 5.625
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// tRFC = 160
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// tRP = 13.5
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// tRAS = 36
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// tRCD = 13.5
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//
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// RESET:
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// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
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// Hold cke low during this time as well
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// The clock should be free running into the chip during this time
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// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
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// ODT must be held low
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// 2. Hold cke low for another 500us, or 100,000 clocks
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// 3. Raise CKE, continue outputting a NOOP for
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// tXPR, tDLLk, and tZQInit
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// 4. Load MRS2, wait tMRD
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// 4. Load MRS3, wait tMRD
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// 4. Load MRS1, wait tMOD
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// Before using the SDRAM, we'll need to program at least 3 of the mode
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// registers, if not all 4.
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// tMOD clocks are required to program the mode registers, during which
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// time the RAM must be idle.
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//
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// NOOP: CS low, RAS, CAS, and WE high
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//
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// Reset logic should be simple, and is given as follows:
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// memory: reset_address. Each memory location provides either a "command" to
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// timer commands indicate whether or not the command during the timer is to
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// be set to idle, or whether the command is instead left as it was.
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reg reset_override;
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reg [3:0] reset_address;
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reg [22:0] reset_cmd;
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reg [26:0] reset_instruction;
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initial reset_override <= 1'b1;
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initial reset_address <= 4'h0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_override <= 1'b1;
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reset_cmd <= { `DDR_NOOP_CMD, reset_instruction[18:0]};
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end else if (!reset_ztimer)
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;
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else if (reset_instruction[`DDR_RESET_DONE])
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reset_override <= 1'b0;
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else if (reset_instruction[`DDR_RSTTIMER])
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begin
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if (reset_instruction[29])
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reset_cmd <= { `DDR_NOOP_CMD, reset_instruction[20:0]};
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end else begin
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reset_cmd[CKE] <= reset_instruction[27];
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reset_cmd[~CKE] <= reset_instruction[22:0];
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end
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always @(posedge i_clk)
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if (i_reset)
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o_ddr_cke <= 1'b0;
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else if (reset_override)&&(reset_ztimer)
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o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
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initial reset_ztimer <= 1'b1; // Is the timer zero?
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initial reset_timer <= 17'h00;
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always @(posedge i_clk)
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if (i_reset)
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= 17'h00;
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end else if (!reset_ztimer)
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begin
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reset_ztimer <= (reset_timer == 17'h01);
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reset_timer <= reset_timer - 17'h01;
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end else if (reset_instruction[`DDR_RSTTIMER])
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begin
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reset_ztimer <= 1'b0;
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reset_timer <= reset_instruction[16:0];
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end
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always @(posedge i_clk)
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case(reset_address)
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4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
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4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
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4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
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4'h3: reset_instruction <= { 4'h3, `DDR_MRS, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
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// 4'h5: reset_instruction <= { 4'h3, `DDR_MRS, 3'h3, 13'h0, 2'b00 }; // MRS3
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4'h5: reset_instruction <= { 4'h3, `DDR_MRS, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
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4'h7: reset_instruction <= { 4'h3, `DDR_MRS, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
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default:
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reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
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endcase
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// reset_instruction <= reset_mem[reset_address];
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always @(posedge i_clk)
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if (i_reset)
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reset_address <= 4'h0;
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else if (reset_ztimer)
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reset_addres <= reset_address + 4'h1;
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//
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// initial reset_mem =
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// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
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// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
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// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
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// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
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// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
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// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
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// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
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// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
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// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
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// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
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// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
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// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
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// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
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// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
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// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
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// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
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//
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//
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// Let's keep track of any open banks. There are 8 of them to keep track of.
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//
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// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
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//
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//
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//
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reg [2:0] bank_status[7:0];
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always @(posedge i_clk)
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begin
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bank_status[0] = { bank_status[0][1:0], bank_status[0][0] };
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bank_status[1] = { bank_status[1][1:0], bank_status[1][0] };
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bank_status[2] = { bank_status[2][1:0], bank_status[2][0] };
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bank_status[3] = { bank_status[3][1:0], bank_status[3][0] };
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bank_status[4] = { bank_status[4][1:0], bank_status[4][0] };
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bank_status[5] = { bank_status[5][1:0], bank_status[5][0] };
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bank_status[6] = { bank_status[6][1:0], bank_status[6][0] };
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bank_status[7] = { bank_status[7][1:0], bank_status[7][0] };
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all_banks_closed <= (bank_status[0][1:0] == 2'b00)
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&&(bank_status[1][1:0] == 2'b00)
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&&(bank_status[2][1:0] == 2'b00)
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&&(bank_status[3][1:0] == 2'b00)
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&&(bank_status[4][1:0] == 2'b00)
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&&(bank_status[5][1:0] == 2'b00)
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&&(bank_status[6][1:0] == 2'b00)
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&&(bank_status[7][1:0] == 2'b00);
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if ((!reset_override)&&(need_refresh)||(w_precharge_all))
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begin
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bank_status[0][0] = 1'b0;
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bank_status[1][0] = 1'b0;
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bank_status[2][0] = 1'b0;
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bank_status[3][0] = 1'b0;
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bank_status[4][0] = 1'b0;
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bank_status[5][0] = 1'b0;
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bank_status[6][0] = 1'b0;
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bank_status[7][0] = 1'b0;
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banks_are_closing <= 1'b1;
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end else if (need_close_bank)
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begin
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bank_status[r_bank][0] = 1'b0;
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end else if (need_open_bank)
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begin
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bank_status[r_bank][0] = 1'b1;
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all_banks_closed <= 1'b0;
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banks_are_closing <= 1'b0;
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end
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end
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always @(posedge i_clk)
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if (cmd == OPEN_BANK)
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bank_row[cmd_bank] <= cmd_address[14:0];
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//
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//
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// Okay, let's investigate when we need to do a refresh. Our plan will be to
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// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
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// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
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//
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// Note that 160ns are needed between refresh commands (JEDEC, p172), or
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// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
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// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
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// time, no more refreshes will be needed for 6240 clocks.
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//
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// Let's think this through:
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// REFRESH_COST = (n*(320)+24)/(n*1560)
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//
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//
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//
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reg [12:0] refresh_clk;
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always @(posedge i_clk)
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if ((endrefresh)&&(refresh_clear))
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refresh_clk <= CKREFI4;
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else if (|refresh_clk)
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refresh_clk <= refresh_clk-1;
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always @(posedge i_clk)
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|
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need_refresh <= (refresh_clk == 0)||(midrefresh);
|
299 |
|
|
always @(posedge i_clk)
|
300 |
|
|
if (need_refresh)
|
301 |
|
|
refresh_count <= refresh_count - 1;
|
302 |
|
|
else
|
303 |
|
|
refresh_count <= 0;
|
304 |
|
|
|
305 |
|
|
always @(posedge i_clk)
|
306 |
|
|
if (!need_refresh)
|
307 |
|
|
refresh_cmd <= NOOP;
|
308 |
|
|
else if (~banks_are_closing)
|
309 |
|
|
refresh_cmd <= CLOSE_ALL_BANKS;
|
310 |
|
|
else if (~all_banks_closed)
|
311 |
|
|
refresh_cmd <= NOOP;
|
312 |
|
|
else
|
313 |
|
|
refresh_cmd <= REFRESH;
|
314 |
|
|
always @(posedge i_clk)
|
315 |
|
|
midrefresh <= (need_refresh)&&(all_banks_closed)&&(~endrefresh);
|
316 |
|
|
|
317 |
|
|
always @(posedge i_clk)
|
318 |
|
|
if (!mid_refresh)
|
319 |
|
|
midrefresh_hctr <= 3'h4;
|
320 |
|
|
else if ((midrefresh_lctr == 0)&&(|midrefresh_hctr))
|
321 |
|
|
midrefresh_hctr <= midrefresh_hctr - 1;
|
322 |
|
|
always @(posedge i_clk)
|
323 |
|
|
if (!need_refresh)||(!mid_refresh)
|
324 |
|
|
endrefresh <= 1'b0;
|
325 |
|
|
else if (midrefresh_hctr == 3'h0)
|
326 |
|
|
endrefresh <= 1'b1;
|
327 |
|
|
always @(posedge i_clk)
|
328 |
|
|
if (!mid_refresh)
|
329 |
|
|
midrefresh_lctr <= CKRFC;
|
330 |
|
|
else if (midrefresh_lctr == 0)
|
331 |
|
|
midrefresh_lctr <= 0;
|
332 |
|
|
else
|
333 |
|
|
midrefresh_lctr <= CKRFC;
|
334 |
|
|
|
335 |
|
|
always @(posedge i_clk)
|
336 |
|
|
refresh_clear <= (needrefresh)&&(endrefresh)&&(midrefresh_lctr == 0);
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
//
|
340 |
|
|
//
|
341 |
|
|
// Let's track: when will our bus be active? When will we be reading or
|
342 |
|
|
// writing?
|
343 |
|
|
//
|
344 |
|
|
//
|
345 |
|
|
reg [8:0] bus_active, bus_read, bus_mask, bus_ack;
|
346 |
|
|
reg [1:0] bus_subaddr [8:0];
|
347 |
|
|
assign pre_cmd = (~reset_override)&&(~need_refresh)&&(valid_bank)
|
348 |
|
|
&&(bus_active[2:0]==3'h0)
|
349 |
|
|
initial bus_active <= 0;
|
350 |
|
|
always @(posedge i_clk)
|
351 |
|
|
begin
|
352 |
|
|
bus_active[8:0] <= { bus_active[7:0], 1'b0 };
|
353 |
|
|
bus_read[8:0] <= { bus_read[7:0], 1'b0 }; // Drive the d-bus?
|
354 |
|
|
bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
|
355 |
|
|
bus_subaddr[8] <= bus_subaddr[7];
|
356 |
|
|
bus_subaddr[7] <= bus_subaddr[6];
|
357 |
|
|
bus_subaddr[6] <= bus_subaddr[5];
|
358 |
|
|
bus_subaddr[5] <= bus_subaddr[4];
|
359 |
|
|
bus_subaddr[4] <= bus_subaddr[3];
|
360 |
|
|
bus_subaddr[3] <= bus_subaddr[2];
|
361 |
|
|
bus_subaddr[2] <= bus_subaddr[1];
|
362 |
|
|
bus_subaddr[1] <= bus_subaddr[0];
|
363 |
|
|
bus_subaddr[0] <= 2'h3;
|
364 |
|
|
if (cmd == READ)
|
365 |
|
|
begin
|
366 |
|
|
bus_active[3:0]<= 4'hf; // Once per clock
|
367 |
|
|
bus_read[3:0] <= 4'hf; // These will be reads
|
368 |
|
|
bus_subaddr[3] <= 2'h0;
|
369 |
|
|
bus_subaddr[2] <= 2'h1;
|
370 |
|
|
bus_subaddr[1] <= 2'h2;
|
371 |
|
|
bus_ack[r_sub] <= 1'b1;
|
372 |
|
|
end else if (cmd == WRITE)
|
373 |
|
|
begin
|
374 |
|
|
bus_active[3:0] <= 4'hf;
|
375 |
|
|
// bus_read[7:4] = 4'h0;
|
376 |
|
|
bus_subaddr[3] <= 2'h0;
|
377 |
|
|
bus_subaddr[2] <= 2'h1;
|
378 |
|
|
bus_subaddr[1] <= 2'h2;
|
379 |
|
|
bus_ack[r_sub] <= 1'b1;
|
380 |
|
|
bus_mask[r_sub] <= 1'b0;
|
381 |
|
|
bus_data[r_sub] <= r_data;
|
382 |
|
|
end
|
383 |
|
|
end
|
384 |
|
|
|
385 |
|
|
always @(posedge i_clk)
|
386 |
|
|
drive_dqs <= (~bus_read[8])&&(|busactive[8:7]);
|
387 |
|
|
|
388 |
|
|
//
|
389 |
|
|
//
|
390 |
|
|
// Now, let's see, can we issue a read command?
|
391 |
|
|
//
|
392 |
|
|
//
|
393 |
|
|
always @(posedge i_clk)
|
394 |
|
|
begin
|
395 |
|
|
if ((i_wb_stb)&&(~o_wb_stall))
|
396 |
|
|
begin
|
397 |
|
|
pending <= 1'b1;
|
398 |
|
|
o_wb_stall <= 1'b1;
|
399 |
|
|
end else if ((r_move)||(m_move))
|
400 |
|
|
begin
|
401 |
|
|
pending <= 1'b0;
|
402 |
|
|
o_wb_stall <= 1'b0;
|
403 |
|
|
end
|
404 |
|
|
|
405 |
|
|
if (~o_wb_stall)
|
406 |
|
|
begin
|
407 |
|
|
r_we <= i_wb_we;
|
408 |
|
|
r_addr <= i_wb_addr;
|
409 |
|
|
r_data <= i_wb_data;
|
410 |
|
|
r_row <= i_wb_addr[25:11];
|
411 |
|
|
r_bank <= i_wb_addr[10:8];
|
412 |
|
|
r_col <= { i_wb_addr[7:2], 2'b00 }; // 9:2
|
413 |
|
|
r_sub <= i_wb_addr[1:0];
|
414 |
|
|
|
415 |
|
|
// pre-emptive work
|
416 |
|
|
r_nxt_row <= i_wb_addr[25:11]+15'h1;
|
417 |
|
|
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
|
418 |
|
|
end
|
419 |
|
|
end
|
420 |
|
|
|
421 |
|
|
reg need_close_bank, last_close_bank,
|
422 |
|
|
need_open_bank, last_open_bank;
|
423 |
|
|
always @(posedge i_clk)
|
424 |
|
|
begin
|
425 |
|
|
need_close_bank <= (r_pending)&&(bank_active[r_bank][0])
|
426 |
|
|
&&(r_row != bank_address[r_bank])&&(!last_close_bank);
|
427 |
|
|
need_close_this_bank <= (r_pending)&&(bank_active[r_bank][0])
|
428 |
|
|
&&(r_row != bank_address[r_bank]);
|
429 |
|
|
last_close_bank <= need_close_bank;
|
430 |
|
|
|
431 |
|
|
maybe_close_next_bank <= (r_pending)
|
432 |
|
|
&&(bank_active[r_nxt_bank][0])
|
433 |
|
|
&&(r_nxt_row != bank_address[r_nxt_bank])
|
434 |
|
|
&&(!need_close_this_bank);
|
435 |
|
|
|
436 |
|
|
close_bank_cmd <= (maybe_close_next_bank)
|
437 |
|
|
? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[15:11], 1'b0, r_nxt_row[9:0] };
|
438 |
|
|
: { `DDR_PRECHARGE, r_bank, r_row[15:11], 1'b0, r_row[9:0] };
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
need_open_bank <= (r_pending)&&(bank_active[r_bank]==2'b00)
|
442 |
|
|
&&(!last_open_bank);
|
443 |
|
|
last_open_bank <= need_open_bank;
|
444 |
|
|
|
445 |
|
|
maybe_open_next_bank <= (r_pending)
|
446 |
|
|
&&(bank_active[r_nxt_bank] == 2'b00)
|
447 |
|
|
&&(!need_open_bank)&&(!need_close_bank);
|
448 |
|
|
|
449 |
|
|
activate_bank_cmd <= (maybe_open_next_bank)
|
450 |
|
|
? { `DDR_ACTIVATE,r_nxt_bank,r_nxt_row[15:10] };
|
451 |
|
|
: { `DDR_ACTIVATE, r_bank, r_row[15:10] };
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
valid_bank <= (r_pending)&&(bank_active[r_bank]==2'b11)
|
456 |
|
|
&&(bank_address[r_bank]==r_row)
|
457 |
|
|
&&(!last_valid_bank);
|
458 |
|
|
last_valid_bank <= need_valid_bank;
|
459 |
|
|
|
460 |
|
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (~r_pending)?`DDR_NOOP:((r_we)?`DDR_WRITE:`DDR_READ);
|
461 |
|
|
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col }
|
462 |
|
|
end
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
// Match registers, to see if we can move forward without sending a
|
466 |
|
|
// new command
|
467 |
|
|
always @(posedge i_clk)
|
468 |
|
|
begin
|
469 |
|
|
if (r_move)
|
470 |
|
|
begin
|
471 |
|
|
m_pending <= r_pending;
|
472 |
|
|
m_we <= r_we;
|
473 |
|
|
m_addr <= r_addr;
|
474 |
|
|
m_row <= r_row;
|
475 |
|
|
m_bank <= r_bank;
|
476 |
|
|
m_col <= r_col;
|
477 |
|
|
m_sub <= r_sub;
|
478 |
|
|
end else if (m_match)
|
479 |
|
|
m_sub <= r_sub;
|
480 |
|
|
|
481 |
|
|
m_match <= (m_pending)&&(pending)&&(r_we == m_we)
|
482 |
|
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
483 |
|
|
&&(r_col == m_col)
|
484 |
|
|
&&(r_sub > m_sub);
|
485 |
|
|
m_continue <= (m_pending)&&(pending)&&(r_we == m_we)
|
486 |
|
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
487 |
|
|
&&(r_col == m_col+8'h1)
|
488 |
|
|
m_nextbank <= (m_pending)&&(pending)&&(r_we == m_we)
|
489 |
|
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
490 |
|
|
end
|
491 |
|
|
|
492 |
|
|
//
|
493 |
|
|
//
|
494 |
|
|
// Okay, let's look at the last assignment in our chain. It should look
|
495 |
|
|
// something like:
|
496 |
|
|
always @(posedge i_clk)
|
497 |
|
|
o_ddr_reset_n <= (~reset_override)||(reset_cmd[DDR_RSTBIT]);
|
498 |
|
|
always @(posedge i_clk)
|
499 |
|
|
o_ddr_cke <= (~reset_override)||(reset_cmd[DDR_CKEBIT]);
|
500 |
|
|
always @(posedge i_clk)
|
501 |
|
|
begin
|
502 |
|
|
r_move <= 1'b0;
|
503 |
|
|
if (reset_override)
|
504 |
|
|
cmd <= reset_command[DDR_CSBIT:0];
|
505 |
|
|
else if (need_refresh)
|
506 |
|
|
begin
|
507 |
|
|
cmd <= refresh_cmd; // The command from the refresh logc
|
508 |
|
|
end else if (need_close_bank)
|
509 |
|
|
cmd <= close_bank_cmd;
|
510 |
|
|
else if (need_open_bank)
|
511 |
|
|
cmd <= activate_bank_cmd;
|
512 |
|
|
else if ((valid_bank)&&(bus_active[2:0]==3'h0))
|
513 |
|
|
begin
|
514 |
|
|
cmd <= rw_cmd;
|
515 |
|
|
r_move <= 1'b1;
|
516 |
|
|
end else
|
517 |
|
|
cmd <= noop;
|
518 |
|
|
end
|
519 |
|
|
|
520 |
|
|
assign o_ddr_cs_n = cmd[DDR_CSBIT];
|
521 |
|
|
assign o_ddr_ras_n = cmd[DDR_RASBIT];
|
522 |
|
|
assign o_ddr_cas_n = cmd[DDR_CASBIT];
|
523 |
|
|
assign o_ddr_we_n = bus_read[8];
|
524 |
|
|
assign o_ddr_dqs = drive_dqs;
|
525 |
|
|
assign o_ddr_addr = cmd[(DDR_ADDR_BITS-1):0];
|
526 |
|
|
assign o_ddr_ba = cmd[DDR_BABITS+DDR_ADDR_BITS-1:DDR_ADDR_BITS];
|
527 |
|
|
assign o_ddr_data = bus_data[8];
|
528 |
|
|
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
529 |
|
|
assign w_precharge_all = (cmd[DDR_CSBIT:DDR_WEBIT]==`DDR_PRECHARGE)
|
530 |
|
|
&&(o_ddr_addr[10]); // 5 bits
|
531 |
|
|
|
532 |
|
|
// Need to set o_wb_dqs high one clock prior to any read.
|
533 |
|
|
// As per spec, ODT = 0 during reads
|
534 |
|
|
assign o_ddr_odt = o_ddr_bus_dir;
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
endmodule
|