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///////////////////////////////////////////////////////////////////////////////

//

// Filename:    wbddrsdram.v

//

// Project:     ZipVersa, Versa Brd implementation using ZipCPU infrastructure

//

// Purpose:     To control a DDR3-1333 (9-9-9) memory from a wishbone bus.

//              In our particular implementation, there will be two command

//      clocks (2.5 ns) per FPGA clock (i_clk) at 5 ns, and 64-bits transferred

//      per FPGA clock.  However, since the memory is focused around 128-bit

//      word transfers, attempts to transfer other than adjacent 64-bit words

//      will (of necessity) suffer stalls.  Please see the documentation for

//      more details of how this controller works.

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2019, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

`default_nettype none

//

module  wbddrsdram(i_clk, i_reset,

                // Wishbone inputs

                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,

                        i_wb_sel,

                // Wishbone outputs

                o_wb_ack, o_wb_stall, o_wb_data,

                // Memory command wires

                o_ddr_reset_n, o_ddr_cke, // o_ddr_bus_oe,

                o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_cmd_c, o_ddr_cmd_d,

                // And the data wires to go with them ....

                o_ddr_data, i_ddr_data);

        // These parameters are not really meant for adjusting from the

        // top level.  These are more internal variables, recorded here

        // so that things can be automatically adjusted without much

        // problem.

        parameter       CKRP = 0;

        parameter       BUSNOW = 2, BUSREG = BUSNOW-1;

        localparam      AW = 24;

        localparam      CMDW = 28;

        localparam      LANES = 2;

        localparam      DW = LANES * 8 * 8;

        localparam      DDRDW = LANES * 8 * 8; // 8b per lane, 2 side ea of 4cyc

        //

        // Possible commands to the DDR3 memory.  These consist of settings

        // for the bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n,

        // respectively.

        localparam [3:0] DDR_MRSET     = 4'b0000;

        localparam [3:0] DDR_REFRESH   = 4'b0001;

        localparam [3:0] DDR_PRECHARGE = 4'b0010;

        localparam [3:0] DDR_ACTIVATE  = 4'b0011;

        localparam [3:0] DDR_WRITE     = 4'b0100;

        localparam [3:0] DDR_READ      = 4'b0101;

        localparam [3:0] DDR_ZQS       = 4'b0110;

        localparam [3:0] DDR_NOOP      = 4'b0111;

        // localparam [3:0] DDR_DESELECT = 4'b1???;

        //

        // In this controller, 24-bit commands tend to be passed around.  These 

        // 'commands' are bit fields.  Here we specify the bits associated with

        // the bit fields.

        localparam      DDR_RSTDONE  = 24;// End the reset sequence?

        localparam      DDR_RSTTIMER = 23;// Does this reset command take multiple clocks?

        localparam      DDR_RSTBIT   = 22;// Value to place on reset_n

        localparam      DDR_CKEBIT   = 21;// Should this reset command set CKE?

        //

        // Refresh command bit fields

        localparam      DDR_PREREFRESH_STALL = 24;

        localparam      DDR_NEEDREFRESH = 23;

        localparam      DDR_RFTIMER = 22;

        localparam      DDR_RFBEGIN = 21;

        //

        localparam      DDR_CMDLEN   = 21;

        localparam      DDR_CSBIT    = 20;

        localparam      DDR_RASBIT   = 19;

        localparam      DDR_CASBIT   = 18;

        localparam      DDR_WEBIT    = 17;

        localparam      DDR_NOPTIMER = 16;      // Steal this from BA bits

        localparam      DDR_BABITS   = 3;       // BABITS are really from 18:16, they are 3 bits

        localparam      DDR_ADDR_BITS = 14;

        //

        localparam      LGNROWS = 14,

                        LGNBANKS= 3;

        localparam      LGFIFOLN = 3;

        localparam      FIFOLEN  = 8;

        //

        // The commands (above) include (in this order):

        //      o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,

        //      o_ddr_dqs, o_ddr_dm, o_ddr_odt

        input   wire    i_clk,  // *MUST* be at 200 MHz for this to work

                        i_reset;

        // Wishbone inputs

        input   wire            i_wb_cyc, i_wb_stb, i_wb_we;

        // The bus address needs to identify a single 128-bit word of interest

        input   wire    [AW-1:0] i_wb_addr;

        input   wire    [DW-1:0] i_wb_data;

        input   wire    [DW/8-1:0]       i_wb_sel;

        // Wishbone responses/outputs

        output  reg                     o_wb_ack, o_wb_stall;

        output  reg     [DW-1:0] o_wb_data;

        // DDR memory command wires

        output  reg             o_ddr_reset_n, o_ddr_cke;

        // CMDs are:

        //       4 bits of CS, RAS, CAS, WE

        //       3 bits of bank

        //      14 bits of Address

        //       1 bit  of DQS (strobe active, or not)

        //       4 bits of mask (one per byte)

        //       1 bit  of ODT

        //      ----

        //      27 bits total

        output  wire    [CMDW-1:0]       o_ddr_cmd_a, o_ddr_cmd_b,

                                        o_ddr_cmd_c, o_ddr_cmd_d;

        output  reg     [DDRDW-1:0]      o_ddr_data;

        input   wire    [DDRDW-1:0]      i_ddr_data;

        integer                 ik, jk;

        ////////

        //

        (* keep *) reg          reset_override, reset_ztimer,

                                maintenance_override;

        ////////

        //

        reg     [3:0]                    reset_address;

        reg     [DDR_CMDLEN-1:0] reset_cmd, cmd_a, cmd_b, cmd_c, cmd_d,

                                        refresh_cmd, maintenance_cmd;

        reg     [24:0]           reset_instruction;

        reg     [16:0]           reset_timer;

        wire    [16:0]           w_ckXPR, w_ckRFC_first;

        wire    [13:0]           w_MR0, w_MR1, w_MR2;

        ////////

        //

        reg                     need_refresh, pre_refresh_stall;

        reg                     refresh_ztimer;

        reg     [16:0]           refresh_counter;

        reg     [2:0]            refresh_addr;

        reg     [24:0]           refresh_instruction;

        reg     [2:0]            cmd_pipe;

        reg     [1:0]            nxt_pipe;

        // Our chosen timing doesn't require any more resolution than one

        // bus clock for ODT.  (Of course, this really isn't necessary, since

        // we aren't using ODT as per the MRx registers ... but we keep it

        // around in case we change our minds later.)

        reg     [2:0]            drive_dqs;

        reg     [5:0]            dqs_pattern;

        reg     [8*LANES-1:0]    ddr_dm;

        reg                     pipe_stall;

        // The pending transaction

        reg     [DW-1:0] r_data;

        reg                     r_pending, r_we;

        reg     [LGNROWS-1:0]    r_row;

        reg     [LGNBANKS-1:0]   r_bank;

        reg     [9:0]            r_col;

        reg     [DW/8-1:0]       r_sel;

        // The pending transaction, one further into the pipeline.  This is

        // the stage where the read/write command is actually given to the

        // interface if we haven't stalled.

        reg     [DW-1:0] s_data;

        reg                     s_pending, s_we;

        reg     [LGNROWS-1:0]    s_row, s_nxt_row;

        reg     [LGNBANKS-1:0]   s_bank, s_nxt_bank;

        reg     [9:0]            s_col;

        reg     [DW/8-1:0]       s_sel;

        // Can we preload the next bank?

        reg     [LGNROWS-1:0]    r_nxt_row;

        reg     [LGNBANKS-1:0]   r_nxt_bank;

        // wire w_precharge_all;

        reg     [(1<<LGNBANKS)-1:0]      bank_status;

        reg     [LGNROWS-1:0]            bank_address    [0:7];

        reg     [(LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;

        reg     [DW-1:0]         bus_fifo_data   [0:BUSNOW];

        reg     [DW/8-1:0]               bus_fifo_sel    [0:BUSNOW];

        reg                             pre_ack;

        reg     [BUSNOW:0]       bus_active, bus_read, bus_ack;

        reg     dir_stall;

        ////////////////////////////////////////////////////////////////////////

        //

        //

        //      Reset Logic

        //

        //

        ////////////////////////////////////////////////////////////////////////

        //

        //

        // Reset logic should be simple, and is given as follows:

        // note that it depends upon a ROM memory, reset_mem, and an address

        // into that memory: reset_address.  Each memory location provides

        // either a "command" to the DDR3 SDRAM, or a timer to wait until

        // the next command.  Further, the timer commands indicate whether

        // or not the command during the timer is to be set to idle, or whether

        // the command is instead left as it was.

        //

        parameter [24:0] INITIAL_RESET_INSTRUCTION = { 4'h4, DDR_NOOP, 17'd40_000 };

        //

        //

        initial reset_override = 1'b1;

        initial reset_address  = 4'h0;

        initial reset_cmd <= { DDR_NOOP, INITIAL_RESET_INSTRUCTION[16:0]};

        always @(posedge i_clk)

        if (i_reset)

        begin

                reset_override <= 1'b1;

                reset_cmd <= { DDR_NOOP, INITIAL_RESET_INSTRUCTION[16:0]};

        end else if ((reset_ztimer)&&(reset_override))

        begin

                if (reset_instruction[DDR_RSTDONE])

                        reset_override <= 1'b0;

                reset_cmd <= reset_instruction[20:0];

        end

        initial reset_ztimer = 1'b0;    // Is the timer zero?

        initial reset_timer = 17'h02;

        always @(posedge i_clk)

        if (i_reset)

        begin

                reset_ztimer <= 1'b0;

                reset_timer  <= 17'd2;

        end else if (reset_override)

        begin

                if (!reset_ztimer)

                begin

                        reset_ztimer <= (reset_timer == 17'h01);

                        reset_timer  <= reset_timer - 17'h01;

                end else if (reset_instruction[DDR_RSTTIMER])

                begin

                        reset_ztimer <= (reset_instruction[16:0]==0);

                        reset_timer  <= reset_instruction[16:0];

                end

        end else

                reset_ztimer <= 1'b1;

        assign  w_MR0 = 14'h0210;

        assign  w_MR1 = 14'h0044;

        assign  w_MR2 = 14'h0040;

        assign  w_ckXPR = 17'd12;// Table 68, p186: 56 nCK / 4 sys clks= 14(-2)

        assign  w_ckRFC_first = 17'd11; // i.e. 52 nCK, or ckREFI

        function [24:0]  get_reset_instruction;

                input   [3:0]    i_addr;

        // DONE, TIMER, RESET, CKE, 

        case(i_addr) // RSTDONE, TIMER, CKE, ??

        //

        // 1. Reset asserted (active low) for 200 us. (@80MHz)

        // INITIAL_RESET_INSTRUCTION = { 4'h4, DDR_NOOP, 17'd40_000 };

        4'h0: get_reset_instruction = { 4'h4, DDR_NOOP, 17'd16_000 };

        //

        // 2. Reset de-asserted, wait 500 us before asserting CKE

        4'h1: get_reset_instruction = { 4'h6, DDR_NOOP, 17'd40_000 };

        //

        // 3. Assert CKE, wait minimum of Reset CKE Exit time

        4'h2: get_reset_instruction = { 4'h7, DDR_NOOP, w_ckXPR };

        //

        // 4. Set MR2.  (4 nCK, no TIMER, but needs a NOOP cycle)

        4'h3: get_reset_instruction = { 4'h3, DDR_MRSET, 3'h2, w_MR2 };

        //

        // 5. Set MR1.  (4 nCK, no TIMER, but needs a NOOP cycle)

        4'h4: get_reset_instruction = { 4'h3, DDR_MRSET, 3'h1, w_MR1 };

        //

        // 6. Set MR0

        4'h5: get_reset_instruction = { 4'h3, DDR_MRSET, 3'h0, w_MR0 };

        //

        // 7. Wait 12 nCK clocks, or 3 sys clocks

        4'h6: get_reset_instruction = { 4'h7, DDR_NOOP,  17'd1 };

        //

        // 8. Issue a ZQCL command to start ZQ calibration, A10 is high

        4'h7: get_reset_instruction = { 4'h3, DDR_ZQS, 6'h0, 1'b1, 10'h0};

        //

        // 9. Wait for both tDLLK and tZQinit completed, both are

        // 512 cks. Of course, since every one of these commands takes

        // two clocks, we wait for one quarter as many clocks (minus

        // two for our timer logic)

        4'h8: get_reset_instruction = { 4'h7, DDR_NOOP, 17'd126 };

        //

        // 10. Precharge all command

        4'h9: get_reset_instruction = { 4'h3, DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };

        //

        // 11. Wait 5 memory clocks (8 memory clocks) for the precharge

        // to complete.  A single NOOP here will have us waiting

        // 8 clocks, so we should be good here.

        4'ha: get_reset_instruction = { 4'h3, DDR_NOOP, 17'd0 };

        //

        // 12. A single Auto Refresh commands

        4'hb: get_reset_instruction = { 4'h3, DDR_REFRESH, 17'h00 };

        //

        // 13. Wait for the auto refresh to complete

        4'hc: get_reset_instruction = { 4'h7, DDR_NOOP, w_ckRFC_first };

        4'hd: get_reset_instruction = { 4'h7, DDR_NOOP, 17'd3 };

        default:

                get_reset_instruction ={4'hb, DDR_NOOP, 17'd00_000 };

        endcase

        endfunction

        initial reset_instruction = INITIAL_RESET_INSTRUCTION;

        always @(posedge i_clk)

        if (i_reset)

                reset_instruction <= INITIAL_RESET_INSTRUCTION;

        else if (reset_ztimer)

                reset_instruction <= get_reset_instruction(reset_address);

        initial reset_address = 4'h0;

        always @(posedge i_clk)

        if (i_reset)

                reset_address <= 4'h0;

        else if (reset_ztimer && reset_override &&

                                !reset_instruction[DDR_RSTDONE])

                reset_address <= reset_address + 4'h1;

        ////////////////////////////////////////////////////////////////////////

        //

        //

        //      Refresh Logic

        //

        //

        ////////////////////////////////////////////////////////////////////////

        //

        //

        //

        // Okay, let's investigate when we need to do a refresh.  Our plan

        // will be to do a single refreshes every tREFI seconds.  We will not

        // push off refreshes, nor pull them in--for simplicity.

        // tREFI = 7.8us, but it is a parameter in the number of clocks

        //      (2496 nCK).  In our case,

        // 7.8us / 12.5ns = 624 clocks (not nCK!)

        //

        // Note that 160ns are needed between refresh commands (JEDEC, p172),

        // or 52 clocks @320MHz.  After this time, no more refreshes will be

        // needed for (2496-52) clocks (@ 320 MHz), or (624-13) clocks (@80MHz).

        //

        // This logic is very similar to the refresh logic, both use a memory

        // as a script.

        //

        initial refresh_addr = 3'h0;

        always @(posedge i_clk)

        if (reset_override)

                refresh_addr <= 3'h0;

        else if (refresh_ztimer)

                refresh_addr <= refresh_addr + 3'h1;

        else if (refresh_instruction[DDR_RFBEGIN])

                refresh_addr <= 3'h0;

        initial refresh_ztimer  = 1'b0;

        initial refresh_counter = 17'd4;

        always @(posedge i_clk)

        if (reset_override)

        begin

                refresh_ztimer  <= 1'b0;

                refresh_counter <= 17'd4;

        end else if (!refresh_ztimer)

        begin

                refresh_ztimer  <= (refresh_counter == 17'h1);

                refresh_counter <= (refresh_counter - 17'h1);

        end else if (refresh_instruction[DDR_RFTIMER])

        begin

                refresh_ztimer <= (refresh_instruction[16:0] == 0);

                refresh_counter <= refresh_instruction[16:0];

        end

        // We need to wait for the bus to become idle from whatever state

        // it is in.  The difficult time for this measurement is assuming

        // a write was just given.  In that case, we need to wait for the

        // write to complete, and then to wait an additional tWR (write

        // recovery time) or 6 nCK clocks from the end of the write.  This

        // works out to seven idle bus cycles from the time of the write

        // command, or a count of 5 (7-2).

        localparam [16:0]        PRE_STALL_COUNTS = 17'd3;

        localparam [16:0]        WAIT_FOR_IDLE    = 0;

        localparam [16:0]        PRIOR_WAIT       = 13;

        localparam [16:0]        REFRESH_INTERVAL = 624;

        localparam [16:0] w_ckREFI_left = REFRESH_INTERVAL

                                - PRIOR_WAIT // Minus what we've already waited

                                - WAIT_FOR_IDLE

                                -17'd19;

        localparam [16:0] w_ckRFC_nxt = 17'd12-17'd3;

        localparam      w_wait_for_idle    = WAIT_FOR_IDLE;

        localparam      w_pre_stall_counts = PRE_STALL_COUNTS;

        parameter [24:0] INITIAL_REFRESH_INSTRUCTION = { 4'h2, DDR_NOOP, 17'd1 };

        function [24:0] get_refresh_instruction;

                input   [2:0]    i_refaddr;

                case(i_refaddr)

                // Bit fields are:

                //      NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)

                //      DDR_PREREFRESH_STALL = 24;

                //      DDR_NEEDREFRESH = 23;

                //      DDR_RFTIMER = 22;

                //      DDR_RFBEGIN = 21;

                //      Command, 20:17

                //      timer value, 16:0

                //

                // First, a number of clocks needing no refresh

                3'h0: get_refresh_instruction = { 4'h2, DDR_NOOP, w_ckREFI_left };

                // Then, we take command of the bus and wait for it to be

                // guaranteed idle

                3'h1: get_refresh_instruction = { 4'ha, DDR_NOOP, w_pre_stall_counts };

                3'h2: get_refresh_instruction = { 4'hc, DDR_NOOP, w_wait_for_idle };

                // Once the bus is idle, all commands complete, and a minimum

                // recovery time given, we can issue a precharge all command

                3'h3: get_refresh_instruction = { 4'hc, DDR_PRECHARGE, 17'h0400 };

                // Now we need to wait tRP = 3 clocks (6 nCK)

                3'h4: get_refresh_instruction = { 4'hc, DDR_NOOP, 17'h00 };

                3'h5: get_refresh_instruction = { 4'hc, DDR_REFRESH, 17'h00 };

                3'h6: get_refresh_instruction = { 4'he, DDR_NOOP, w_ckRFC_nxt };

                3'h7: get_refresh_instruction = { 4'h2, DDR_NOOP, 17'd12 };

                // default:

                        // refresh_instruction = { 4'h1, DDR_NOOP, 17'h00 };

                endcase

        endfunction

        initial refresh_instruction = INITIAL_REFRESH_INSTRUCTION;

        always @(posedge i_clk)

        if (reset_override)

                // refresh_instruction <= { 4'h2, DDR_NOOP, 17'd1 };

                refresh_instruction <= INITIAL_REFRESH_INSTRUCTION;

        else if (refresh_ztimer)

                refresh_instruction <= get_refresh_instruction(refresh_addr);

        // Note that we don't need to check if (reset_override) here since

        // refresh_ztimer will always be true if (reset_override)--in other

        // words, it will be true for many, many, clocks--enough for this

        // logic to settle out.

        initial refresh_cmd = INITIAL_REFRESH_INSTRUCTION[20:0];

        always @(posedge i_clk)

        if (reset_override)

                refresh_cmd <= INITIAL_REFRESH_INSTRUCTION[20:0];

        else if (refresh_ztimer)

                refresh_cmd <= refresh_instruction[20:0];

        initial need_refresh = INITIAL_REFRESH_INSTRUCTION[DDR_NEEDREFRESH];

        always @(posedge i_clk)

        if (reset_override)

                need_refresh <= INITIAL_REFRESH_INSTRUCTION[DDR_NEEDREFRESH];

        else if (refresh_ztimer)

                need_refresh <= refresh_instruction[DDR_NEEDREFRESH];

        initial pre_refresh_stall = 1'b0;

        always @(posedge i_clk)

        if (reset_override)

                pre_refresh_stall <= 1'b0;

        else if (refresh_ztimer)

                pre_refresh_stall <= refresh_instruction[DDR_PREREFRESH_STALL];

        ////////////////////////////////////////////////////////////////////////

        //

        //

        //      Open Banks

        //

        //

        ////////////////////////////////////////////////////////////////////////

        //

        //

        //

        // Let's keep track of any open banks.  There are 8 of them to keep

        // track of.

        //

        // A precharge requires 1 clocks at 80MHz to complete.

        // An activate also requires 1 clocks at 80MHz to complete.

        // By the time we log these, they will be complete.

        // Precharges are not allowed until the maximum of:

        //      2 clocks (200 MHz) after a read command

        //      4 clocks after a write command

        //

        //

        initial begin

                for(ik=0; ik< (1<<LGNBANKS); ik=ik+1)

                begin

                        bank_status[ik] = 0;

                        bank_address[ik] = 0;

                end

        end

        always @(posedge i_clk)

        begin

                if (cmd_pipe[0])

                begin

                        bank_status[s_bank] <= 1'b0;

                        if (nxt_pipe[1])

                                bank_status[s_nxt_bank] <= 1'b1;

                end else begin

                        if (cmd_pipe[1])

                                bank_status[s_bank] <= 1'b1;

                        else if (nxt_pipe[1])

                                bank_status[s_nxt_bank] <= 1'b1;

                        if (nxt_pipe[0])

                                bank_status[s_nxt_bank] <= 1'b0;

                end

                if (i_reset || maintenance_override)

                begin

                        // All banks get precharged on any refresh

                        // (or reset) event

                        //

                        for(ik = 0; ik < (1<<LGNBANKS); ik = ik+1)

                                bank_status[ik] <= 0;

                end

        end

`ifdef  FORMAL

always @(*)

assert(nxt_pipe != 2'b11);

`endif

        always @(posedge i_clk)

        if (cmd_pipe[1])

                bank_address[s_bank] <= s_row;

        else if (nxt_pipe[1])

                bank_address[s_nxt_bank] <= s_nxt_row;

        ////////////////////////////////////////////////////////////////////////

        //

        //

        //      Data BUS information

        //

        //

        ////////////////////////////////////////////////////////////////////////

        //

        //

        // Our purpose here is to keep track of when the data bus will be

        // active.  This is separate from the FIFO which will contain the

        // data to be placed on the bus (when so placed), in that this is

        // a group of shift registers--every position has a location in

        // time, and time always moves forward.  The FIFO, on the other

        // hand, only moves forward when data moves onto the bus.

        //

        //

        initial bus_active = 0;

        initial bus_ack = 0;

        always @(posedge i_clk)

        begin

                bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };

                // Drive the d-bus?

                bus_read[BUSNOW:0]   <= { bus_read[(BUSNOW-1):0], 1'b0 };

                // Will this position on the bus get a wishbone acknowledgement?

                bus_ack[BUSNOW:0]   <= { bus_ack[(BUSNOW-1):0], 1'b0 };

                if (cmd_pipe[2]) // && !i_reset && i_wb_cyc)

                begin

                        bus_active[0]<= 1'b1; // Data transfers in one clocks

                        bus_ack[0] <= 1'b1;

                        bus_read[0] <= !s_we;

                end

                if (i_reset || !i_wb_cyc)

                        bus_ack <= 0;

        end

        //

        //

        // Can we issue a read command?

        //

        //

        initial { r_pending, s_pending, pipe_stall, o_wb_stall } = 4'b0001;

        initial nxt_pipe = 0;

        initial cmd_pipe = 0;

        initial dir_stall = 0;

        always @(posedge i_clk)

        begin

                r_pending <= (i_wb_stb)&&(!o_wb_stall)

                                ||(r_pending)&&(pipe_stall);

                dir_stall <= (i_wb_stb && !o_wb_stall && r_pending

                                && r_we != i_wb_we);

                if (pipe_stall && dir_stall)

                        dir_stall <= 1;

                if (!pipe_stall && !dir_stall)