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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename: spec.tex
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%%
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%% Project: Wishbone scope
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%%
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%% Purpose: This LaTeX file contains all of the documentation/description
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%% currently provided with this Wishbone scope core. It's not
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%% nearly as interesting as the PDF file it creates, so I'd
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%% recommend reading that before diving into this file. You
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%% should be able to find the PDF file in the SVN distribution
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%% together with this PDF file and a copy of the GPL-3.0 license
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%% this file is distributed under. If not, just type 'make'
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%% in the doc directory and it (should) build without a problem.
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%%
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%%
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%% Creator: Dan Gisselquist
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%% Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015,2017, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program. (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.) If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License: GPL, v3, as defined and found on www.gnu.org,
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%% http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass{gqtekspec}
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\project{Wishbone Scope}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) ieee.org}
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\revision{Rev.~0.4}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\titlepage
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a
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copy.
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\end{license}
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\begin{revisionhistory}
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0.4 & 6/2/2017 & Gisselquist & Added Compressed scope and TB's\\\hline
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0.3 & 6/22/2015 & Gisselquist & Minor updates to enhance readability \\\hline
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0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline
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0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline
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\end{revisionhistory}
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% Revision History
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% Table of Contents, named Contents
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\tableofcontents
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% \listoffigures
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\listoftables
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\begin{preface}
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This project began, years ago, for all the wrong reasons. Rather than pay a
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high price to purchase a Verilog simulator and then to learn how to use it,
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I took working Verilog code, to include a working bus, added features and
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used the FPGA system as my testing platform. I arranged the FPGA to step
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internal registers upon command, and to make many of those registers
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available via the bus.
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When I then needed to make the project run in real-time, as opposed to the
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manually stepped approach, I generated a scope like this one. I had already
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bench tested the components on the hardware itself. Thus, testing and
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development continued on the hardware, and the scope helped me see what was
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going right or wrong. The great advantage of the approach was that, at the
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end of the project, I didn't need to switch from simulation to hardware in the
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loop testing, since all my testing had been done with the hardware in the loop.
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When I left that job, I took this concept with me and rebuilt this piece of
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infrastructure using a Wishbone Bus. I am not going to recommend that others
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use this approach for bench testing, but I have found it very valuable for
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debugging on the hardware.
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\end{preface}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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The Wishbone Scope is a debugging tool for reading results from the chip after
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events have taken place. It designed to be a peripheral on an already
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existing wishbone bus--pushing the complicated task of getting a bus up
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and running elsewhere. In general, the scope records data until some
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some (programmable) holdoff number of data samples after a trigger has taken
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place. Once the holdoff has been reached, the scope stops recording and
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asserts an interrupt. At this time, data may be read from the scope in order
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from oldest to most recent. That's the basics, now for two extra details.
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First, the trigger and the data that the scope records are both implementation
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dependent. The scope itself is designed to be easily reconfigurable from one
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build to the next so that the actual configuration may even be build dependent.
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Second, the scope is built to be able to run synchronously with the bus clock,
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or off of a separate data clock. Whether or not the two are synchronous is
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controlled by the ``SYNCHRONOUS'' parameter. When running off of two
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clocks, the actions associated with commands issued to the scope,
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such as manual triggering, as well as disabling or releasing the trigger, will
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not act synchronously with the scope itself--but this is to be expected.
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Third, the data clock associated with the scope has a clock enable line
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associated with it. Depending on how often the clock enable line is enabled
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may determine how fast the scope is {\tt PRIMED}, {\tt TRIGGERED}, and then
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eventually completes its collection.
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Finally, and in conclusion, this scope has been an invaluable tool for
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testing, for figuring out what is going on internal to a chip, and for fixing
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such things. I have diagnosed PS/2 interactions, Internal
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Configuration Access Port (ICAPE2) interfaces, mouse controller interactions,
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bus errors, quad-SPI flash interactions, SD--card interface, VGA, HDMI, and
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even the internals of a CPU all using this scope.
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\chapter{Architecture}
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The wishbone scope package comes with two separate scopes: the regular scope,
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and a run-length encoded scope.
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Both scopes are designed to be a component of a larger design. They depend upon
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the existence of a reliable wishbone bus which can be accessed independent of
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the portion of the design under test.
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Both scopes exist as a slave peripheral on this wishbone bus.
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The bus master still needs to interact with this slave to first configure it,
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and second to read any data off of it.
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Interaction with the scopes is identical, save for two differences. First, the
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run-length encoded scope uses the high order bit to specify the number of
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times to repeat the last data item. This means that the run-length encoded
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scope can only store 31~bits per time interval, versus the 32~bits per time
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interval of the regular scope.
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Since the two scopes are so similar, they will collectively be called the
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Wishbone Scope, and differences will only be mentioned where appropriate.
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\chapter{Operation}
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So how shall one use the scope? The scope itself supports a series of
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states:
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\begin{enumerate}
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\item {\tt RESET}
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Any write to the control register, without setting the high order bit,
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will automatically reset the scope. Once reset, the scope will
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immediately start collecting.
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\item {\tt PRIMED}
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Following a reset, once the scope has filled its memory, it enters the
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{\tt PRIMED} state. Once it reaches this state, it will be sensitive
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to a trigger.
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\item {\tt TRIGGERED}
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The scope may be {\tt TRIGGERED} either automatically, via an input port to
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the core, or manually, via a wishbone bus command. Once a trigger
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has been received, the core will record a user configurable number of
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further samples before stopping.
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\item {\tt STOPPED}
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Once the core has {\tt STOPPED}, the data within it may be read back off.
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\end{enumerate}
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Let's go through that list again. First, before using the scope, the holdoff
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needs to be set. The scope is designed so that setting the scope control value
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to the holdoff alone, with all other bits set to zero, will reset the scope
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from whatever condition it was in,
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freeing it to run. Once running, then upon every clock enabled clock, one
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sample of data is read into the scope and recorded. Once every memory value
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is filled, the scope has been {\tt PRIMED}. Once the scope has been
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{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
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active on an input clock with the clock--enable line set, the scope will then
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be {\tt TRIGGERED}. It
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will then count for the number of clocks in the holdoff before stopping
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collection, placing it in the {\tt STOPPED} state.\footnote{You can even
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change the holdoff while the scope is running by writing a new holdoff value
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together with setting the {\tt RESET\_n} bit of the control register. However,
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if you do this after the core has triggered it may stop at some other
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non--holdoff value!} If the holdoff is zero, the last sample in the buffer
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will be the sample containing the trigger. Likewise if the holdoff is one
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less than the size of the memory, the first sample in the buffer will be the
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one containing the trigger.
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There are two further commands that will affect the operation of the scope. The
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first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
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the holdoff to the control register while setting this bit high. This will
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cause the scope to trigger as soon as it is primed. If the {\tt RESET\_n}
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bit is also set so as to prevent an internal reset, and if the scope was already
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primed, then manual trigger command will cause it to trigger immediately.
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The last command that can affect the operation of the scope is the {\tt DISABLE}
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command/bit in the control register. Setting this bit will prevent the scope
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from triggering, or if {\tt TRIGGERED}, it will prevent the scope from
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generating an interrupt.
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Finally, be careful how you set the clock enable line. If the clock enable
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line leaves the clock too often disabled, the scope might never prime in any
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reasonable amount of time.
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So, in summary, to use this scope you first set the holdoff value in the
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control register. Second, you wait until the scope has been {\tt TRIGGERED}
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and {\tt STOPPED}. Finally, you read from the data register once for every
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memory value in the buffer and you can then sit back, relax, and study what
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took place within the FPGA. Additional modes allow you to manually trigger
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the scope, or to disable the automatic trigger entirely.
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\chapter{Registers}
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This scope core supports two registers, as listed in
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Tbl.~\ref{tbl:reglist}: a control register and a data register.
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\begin{table}[htbp]
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\begin{center}
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\begin{reglist}
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CONTROL & 0 & 32 & R/W & Configuration, control, and status of the
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scope.\\\hline
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DATA & 4 & 32 & R(/W) & Read out register, to read out the data
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from the core. Writes to this register reset the read address
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to the beginning of the buffer, but are otherwise ignored.
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\\\hline
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\end{reglist}\caption{List of Registers}\label{tbl:reglist}
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\end{center}\end{table}
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Each register will be discussed in detail in this chapter.
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\section{Control Register}
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The bits in the control register are defined in Tbl.~\ref{tbl:control}.
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\begin{table}[htbp]
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\begin{center}
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\begin{bitlist}
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31 & R/W & {\tt RESET\_n}. Write a `0' to this register to command a reset.
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Reading a `1' from this register means the reset has not finished
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crossing clock domains and is still pending.\\\hline
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30 & R & {\tt STOPPED}, indicates that all collection has stopped.\\\hline
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29 & R & {\tt TRIGGERED}, indicates that a trigger has been recognized, and that
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the scope is counting for holdoff samples before stopping.\\\hline
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28 & R & {\tt PRIMED}, indicates that the memory has been filled, and that the
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scope is now waiting on a trigger.\\\hline
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27 & R/W & {\tt MANUAL}, set to invoke a manual trigger.\\\hline
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26 & R/W & {\tt DISABLE}, set to disable the internal trigger. The scope may still
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be {\tt TRIGGERED} manually.\\\hline
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25 & R & {\tt RZERO}, this will be true whenever the scope's internal address
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register is pointed at the beginning of the memory.\\\hline
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20--24 & R & {\tt LGMEMLEN}, the base two logarithm of the memory length. Thus,
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the memory internal to the scope is given by 1$<<$LGMEMLEN. \\\hline
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0--19 & R/W & Unsigned holdoff\\\hline
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\end{bitlist}
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\caption{Control Register}\label{tbl:control}
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\end{center}\end{table}
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The register has been designed so that one need only write the holdoff value to
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it, while leaving the other bits zero, to get the scope going. On such a write,
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the RESET\_n bit will be a zero, causing the scope to internally reset itself.
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Further, during normal operation, the high order nibble will go from 4'h8
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(a nearly instantaneous reset state) to 4'h0 (running), to 4'h1 ({\tt PRIMED}),
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to 4'h3 ({\tt TRIGGERED}), and then stop at 4'h7 ({\tt PRIMED}, {\tt TRIGGERED},
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and {\tt STOPPED}).
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Finally, user's are cautioned not to adjust the holdoff between the time the
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scope triggers and the time it stops--just to guarantee data coherency.
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The scope also has some other capabilities. For example,
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if you set the {\tt MANUAL} bit, the scope will trigger as soon as it is {\tt PRIMED}.
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If you set the {\tt MANUAL} bit and the {\tt RESET\_n} bit, it will trigger
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immediately if the scope was already {\tt PRIMED}. However, if the
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{\tt RESET\_n} bit was not also set, a reset will take place and the scope
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will start over by first collecting enough data to be {\tt PRIMED}, and only
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then will the {\tt MANUAL} trigger take effect.
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A second optional capability is to disable the scope entirely. This might be
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useful if, for example, certain irrelevant things might trigger the scope.
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By setting the {\tt DISABLE} bit, the scope will not automatically trigger. It
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will still record into its memory, and it will still prime itself, it will just
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not trigger automatically. The scope may still be manually {\tt TRIGGERED}
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while the {\tt DISABLE} bit is set. Likewise, if the {\tt DISABLE} bit is set
|
297 |
|
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after the scope has been {\tt TRIGGERED}, the scope will continue to its
|
298 |
|
|
natural stopped state--it just won't generate an interrupt.
|
299 |
4 |
dgisselq |
|
300 |
5 |
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There are two other interesting bits in this control register. The {\tt RZERO}
|
301 |
|
|
bit indicates that the next read from the data register will read from the first
|
302 |
|
|
value in the memory, while the {\tt LGMEMLEN} bits indicate how long the memory is. Thus, if {\tt LGMEMLEN} is 10, the FIFO will be (1$<<$10) or 1024 words
|
303 |
|
|
long, whereas if {\tt LGMEMLEN} is 14, the FIFO will be (1$<<$14) or 16,384 words
|
304 |
|
|
long.
|
305 |
4 |
dgisselq |
|
306 |
2 |
dgisselq |
\section{Data Register}
|
307 |
|
|
|
308 |
|
|
This is perhaps the simplest register to explain. Before the core stops
|
309 |
|
|
recording, reads from this register will produce reads of the bits going into
|
310 |
|
|
the core, save only that they have not been protected from any meta-stability
|
311 |
13 |
dgisselq |
issues. This may be useful for reading what's going on when the various lines
|
312 |
|
|
are stuck, although there are potential race conditions when using this feature.
|
313 |
|
|
After the core stops recording, reads from this register return values
|
314 |
5 |
dgisselq |
from the stored memory, beginning at the oldest and ending with the value
|
315 |
|
|
holdoff clocks after the trigger. Further, after recording has stopped, every
|
316 |
|
|
read increments an internal memory address, so that after (1$<<$LGMEMLEN)
|
317 |
|
|
reads (for however long the internal memory is), the entire memory has been
|
318 |
|
|
returned over the bus.
|
319 |
2 |
dgisselq |
If you would like some assurance that you are reading from the beginning of the
|
320 |
4 |
dgisselq |
memory, you may either check the control register's {\tt RZERO} flag which will
|
321 |
|
|
be `1' for the first value in the buffer, or you may write to the data register.
|
322 |
|
|
Such writes will be ignored, save that they will reset the read address back
|
323 |
|
|
to the beginning of the buffer.
|
324 |
13 |
dgisselq |
|
325 |
|
|
If the holdoff is set to zero, the last data value will be the value recorded
|
326 |
|
|
when the trigger took place. As the holdoff increases, the trigger will move
|
327 |
|
|
earlier and earlier into the buffer.
|
328 |
|
|
|
329 |
|
|
The data register for the compressed scope will indicate the presence of a
|
330 |
|
|
run in the high order bit. If the high order bit is set, the last value
|
331 |
|
|
will be repeated one plus the value held in the register. Hence, a
|
332 |
|
|
data value of {\tt 0x80000000} indicates a value repeated once, while
|
333 |
|
|
{\tt 0x80000001 } indicates the value has been repeated twice and so on.
|
334 |
4 |
dgisselq |
|
335 |
2 |
dgisselq |
\chapter{Clocks}
|
336 |
|
|
|
337 |
|
|
This scope supports two clocks: a wishbone bus clock, and a data clock.
|
338 |
|
|
If the internal parameter ``SYNCHRONOUS'' is set to zero, proper transfers
|
339 |
|
|
will take place between these two clocks. Setting this parameter to a one
|
340 |
4 |
dgisselq |
will save some flip flops and logic in implementation. The speeds of the
|
341 |
|
|
respective clocks are based upon the speed of your device, and not specific
|
342 |
|
|
to this core.
|
343 |
13 |
dgisselq |
|
344 |
|
|
That said, I have run the core up to 200~MHz on a Xilinx Artix-7, and so
|
345 |
|
|
it has been modified to match that speed.
|
346 |
4 |
dgisselq |
|
347 |
2 |
dgisselq |
\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
348 |
|
|
Tbl.~\ref{tbl:wishbone}
|
349 |
|
|
\begin{table}[htbp]
|
350 |
|
|
\begin{center}
|
351 |
|
|
\begin{wishboneds}
|
352 |
|
|
Revision level of wishbone & WB B4 spec \\\hline
|
353 |
|
|
Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
|
354 |
|
|
Port size & 32--bit \\\hline
|
355 |
|
|
Port granularity & 32--bit \\\hline
|
356 |
|
|
Maximum Operand Size & 32--bit \\\hline
|
357 |
|
|
Data transfer ordering & (Irrelevant) \\\hline
|
358 |
|
|
Clock constraints & None.\\\hline
|
359 |
|
|
Signal Names & \begin{tabular}{ll}
|
360 |
|
|
Signal Name & Wishbone Equivalent \\\hline
|
361 |
|
|
{\tt i\_wb\_clk} & {\tt CLK\_I} \\
|
362 |
|
|
{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
|
363 |
|
|
{\tt i\_wb\_stb} & {\tt STB\_I} \\
|
364 |
|
|
{\tt i\_wb\_we} & {\tt WE\_I} \\
|
365 |
|
|
{\tt i\_wb\_addr} & {\tt ADR\_I} \\
|
366 |
|
|
{\tt i\_wb\_data} & {\tt DAT\_I} \\
|
367 |
|
|
{\tt o\_wb\_ack} & {\tt ACK\_O} \\
|
368 |
|
|
{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
369 |
|
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
370 |
|
|
\end{tabular}\\\hline
|
371 |
|
|
\end{wishboneds}
|
372 |
|
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
373 |
|
|
\end{center}\end{table}
|
374 |
|
|
is required by the wishbone specification, and so
|
375 |
|
|
it is included here. The big thing to notice is that this core
|
376 |
|
|
acts as a wishbone slave, and that all accesses to the wishbone scope
|
377 |
4 |
dgisselq |
registers become 32--bit reads and writes to this interface. You may also wish
|
378 |
|
|
to note that the scope supports pipeline reads from the data port, to speed
|
379 |
|
|
up reading the results out.
|
380 |
6 |
dgisselq |
|
381 |
13 |
dgisselq |
The {\tt o\_wb\_stall} line is tied to zero.
|
382 |
|
|
|
383 |
|
|
The {\tt i\_wb\_cyc} line is assumed any time {\tt i\_wb\_stb} is high, and so
|
384 |
|
|
the core ignores {\tt i\_wb\_cyc}.
|
385 |
|
|
|
386 |
|
|
The core does not implement the {\tt i\_wb\_sel} lines. Writes to the core
|
387 |
|
|
of values less than a word are undefined. Reads of less than a word in
|
388 |
|
|
size will act as whole word reads.
|
389 |
|
|
|
390 |
|
|
|
391 |
12 |
dgisselq |
\chapter{I/O Ports}\label{ch:ioports}
|
392 |
2 |
dgisselq |
|
393 |
13 |
dgisselq |
The external I/O ports for both cores are listed in Table.~\ref{tbl:ioports}.
|
394 |
2 |
dgisselq |
\begin{table}[htbp]
|
395 |
|
|
\begin{center}
|
396 |
|
|
\begin{portlist}
|
397 |
13 |
dgisselq |
{\tt i\_data\_clk} & 1 & Input & The clock the data lines, clock enable, and
|
398 |
|
|
trigger are synchronous to. \\\hline
|
399 |
5 |
dgisselq |
{\tt i\_ce} & 1 & Input & Clock Enable. Set this high to clock data in and
|
400 |
13 |
dgisselq |
out. No data will move through the core if this is low. \\\hline
|
401 |
5 |
dgisselq |
{\tt i\_trigger} & 1 & Input & An active high trigger line. If this trigger is
|
402 |
4 |
dgisselq |
set to one on any clock enabled data clock cycle, once
|
403 |
5 |
dgisselq |
the scope has been {\tt PRIMED}, it will then enter into its
|
404 |
|
|
{\tt TRIGGERED} state.
|
405 |
4 |
dgisselq |
\\\hline
|
406 |
13 |
dgisselq |
{\tt i\_data} & 32 & Input & \parbox{3.3in}{{\tt WBSCOPE ONLY: } 32--wires of
|
407 |
|
|
... whatever you
|
408 |
|
|
are interested in recording and later examining. These can be anything,
|
409 |
|
|
only they should be synchronous with the data clock.
|
410 |
|
|
|
411 |
|
|
{\tt WBSCOPC: } The data width is only 31 wide instead of 32}
|
412 |
4 |
dgisselq |
\\\hline
|
413 |
5 |
dgisselq |
{\tt i\_wb\_clk} & 1 & Input & The clock that the wishbone interface runs on.
|
414 |
2 |
dgisselq |
\\\hline
|
415 |
5 |
dgisselq |
{\tt i\_wb\_cyc} & 1 & Input & Indicates a wishbone bus cycle is active when
|
416 |
|
|
high. \\\hline
|
417 |
|
|
{\tt i\_wb\_stb} & 1 & Input & Indicates a wishbone bus cycle for this
|
418 |
|
|
peripheral when high. (See the wishbone spec for more details) \\\hline
|
419 |
|
|
{\tt i\_wb\_we} & 1 & Input & Write enable, allows indicates a write to one of
|
420 |
|
|
the two registers when {\tt i\_wb\_stb} is also high.
|
421 |
4 |
dgisselq |
\\\hline
|
422 |
5 |
dgisselq |
{\tt i\_wb\_addr} & 1 & Input & A single address line, set to zero to access the
|
423 |
|
|
configuration and control register, to one to access the data
|
424 |
2 |
dgisselq |
register. \\\hline
|
425 |
5 |
dgisselq |
{\tt i\_wb\_data} & 32 & Input & Data used when writing to the control register,
|
426 |
2 |
dgisselq |
ignored otherwise. \\\hline
|
427 |
5 |
dgisselq |
{\tt o\_wb\_ack} & 1 & Output & Wishbone acknowledgement. This line will go
|
428 |
13 |
dgisselq |
high two clocks after any wishbone access, as long as the
|
429 |
5 |
dgisselq |
wishbone {\tt i\_wb\_cyc} line remains high (i.e., no ack's if
|
430 |
|
|
you terminate the cycle early).
|
431 |
2 |
dgisselq |
\\\hline
|
432 |
5 |
dgisselq |
{\tt o\_wb\_stall} & 1 & Output & Required by the wishbone spec, but always
|
433 |
|
|
set to zero in this implementation.
|
434 |
2 |
dgisselq |
\\\hline
|
435 |
5 |
dgisselq |
{\tt o\_wb\_data} & 32 & Output & Values read, either control or data, headed
|
436 |
|
|
back to the wishbone bus. These values will be valid during any
|
437 |
4 |
dgisselq |
read cycle when the {\tt i\_wb\_ack} line is high.
|
438 |
|
|
\\\hline
|
439 |
2 |
dgisselq |
\end{portlist}
|
440 |
|
|
\caption{List of IO ports}\label{tbl:ioports}
|
441 |
|
|
\end{center}\end{table}
|
442 |
4 |
dgisselq |
At this point, most of these ports should have been well defined and described
|
443 |
|
|
earlier in this document. The only new things are the data clock, {\tt i\_clk},
|
444 |
|
|
the clock enable for the data, {\tt i\_ce}, the trigger, {\tt i\_trigger}, and
|
445 |
|
|
the data of interest itself, {\tt i\_data}. Hopefully these are fairly self
|
446 |
|
|
explanatory by this point. If not, just remember the data, {\tt i\_data},
|
447 |
|
|
are synchronous to the clock, {\tt i\_clk}. On every clock where the clock
|
448 |
|
|
enable line is high, {\tt i\_ce}, the data will be recorded until the scope
|
449 |
|
|
has stopped. Further, the scope will stop some programmable holdoff number
|
450 |
|
|
of clock enabled data clocks after {\tt i\_trigger} goes high. Further,
|
451 |
|
|
{\tt i\_trigger} need only be high for one clock cycle to be noticed by the
|
452 |
|
|
scope.
|
453 |
|
|
|
454 |
2 |
dgisselq |
% Appendices
|
455 |
|
|
% Index
|
456 |
|
|
\end{document}
|
457 |
|
|
|
458 |
|
|
|