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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename: spec.tex
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%%
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%% Project: Wishbone scope
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%%
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%% Purpose: This LaTeX file contains all of the documentation/description
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%% currently provided with this Wishbone scope core. It's not
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%% nearly as interesting as the PDF file it creates, so I'd
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%% recommend reading that before diving into this file. You
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%% should be able to find the PDF file in the SVN distribution
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%% together with this PDF file and a copy of the GPL-3.0 license
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%% this file is distributed under. If not, just type 'make'
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%% in the doc directory and it (should) build without a problem.
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%%
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%%
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%% Creator: Dan Gisselquist
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%% Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program. (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.) If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License: GPL, v3, as defined and found on www.gnu.org,
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%% http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass{gqtekspec}
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\project{Wishbone Scope}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.1}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\titlepage
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
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copy.
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\end{license}
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\begin{revisionhistory}
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0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline
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0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline
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\end{revisionhistory}
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% Revision History
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% Table of Contents, named Contents
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\tableofcontents
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% \listoffigures
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\listoftables
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\begin{preface}
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This project began, years ago, for all the wrong reasons. Rather than pay a
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high price to purchase a Verilog simulator and then to learn how to use it,
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I took working Verilog code, to include a working bus, added features and
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used the FPGA system as my testing platform. I arranged the FPGA to step
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internal registers upon command, and to make many of those registers
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available via the bus.
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When I then needed to make the project run in real-time, as opposed to the
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manually stepped approach, I generated a scope like this one. I had already
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bench tested the components on the hardware itself. Thu, testing and
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development continued on the hardware, and the scope helped me see what was
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going right or wrong. The great advantage of the approach was that, at the
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end of the project, I didn't need to do any hardware in the loop testing.
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All of the testing that had been accomplished prior to that date was already
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hardware in the loop testing.
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When I left that job, I took this concept with me and rebuilt this piece of
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infrastructure using a Wishbone Bus.
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\end{preface}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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The wishbone Scope is a debugging tool for reading results from the chip after
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events have taken place. In general, the scope records data until some
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some (programmable) holdoff number of data samples after a trigger has taken
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place. Once the holdoff has been reached, the scope stops recording and
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asserts an interrupt. At this time, data may be read from the scope in order
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from oldest to most recent. That's the basics, now for two extra details.
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First, the trigger and the data that the scope records are both implementation
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dependent. The scope itself is designed to be easily reconfigurable from one
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build to the next so that the actual configuration may even be build dependent.
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Second, the scope is built to be able to run off of a separate clock from the
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bus that commands and controls it. This is configurable, set the parameter
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``SYNCHRONOUS'' to `1' to run off of a single clock. When running off of two
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clocks, it means that actions associated with commands issued to the scope,
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such as manual triggering or being disabled or released, will not act
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synchronously with the scope itself--but this is to be expected.
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Third, the data clock associated with the scope has a clock enable line
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associated with it. Depending on how often the clock enable line is enabled
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may determine how fast the scope is primed, triggered, and eventually completes
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its collection.
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Finally, and in conclusion, this scope has been an invaluable tool for
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testing, for figuring out what is going on internal to a chip, and for fixing
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such things. I have fixed interactions over a PS/2 connection, Internal
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Configuration Access Port (ICAPE2) interfaces, mouse controller interactions,
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bus errors, quad-SPI flash interactions, and more using this scope.
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% \chapter{Architecture}
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\chapter{Operation}
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So how shall one use the scope? The scope itself supports a series of
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states:
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\begin{enumerate}
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\item RESET
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Any write to the control register, without setting the high order bit,
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will automatically reset the scope.
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\item PRIMED
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Following a reset, once the scope has filled its memory, it enters the
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PRIMED state. Once it reaches this state, it will be sensitive to a
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trigger.
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\item TRIGGERED
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The scope may be triggered either automatically, via an input port to
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the core, or manually, via a wishbone bus command. Once a trigger
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has been received, the core will record a user configurable number of
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further samples before stopping.
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\item STOPPED
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Once the core has stopped, the data within it may be read back off.
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\end{enumerate}
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Let's go through that list again. First, before using the scope, the holdoff
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needs to be set. The scope is designed so that setting the scope control value
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to the holdoff alone will reset the scope from whatever condition it was in,
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freeing it to run. Once running, then upon every clock enabled clock, one
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sample of data is read into the scope and recorded. Once every memory value
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is filled, the scope has been {\tt PRIMED}. Once the scope has been
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{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
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active on a clock--enabled input, the scope will then be {\tt TRIGGERED}. It
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will then count for the number of clocks in the holdoff before stopping
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collection, placing it in the {\tt STOPPED} state. If the holdoff is zero,
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the last sample in the buffer will be the sample containing the trigger.
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Likewise if the holdoff is one less than the size of the memory, the first
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sample in the buffer will be the one containing the trigger.
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There are two further commands that will affect the operation of the scope. The
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first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
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the holdoff to the control register while setting this bit high. This will
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cause the scope to trigger immediately. If coupled with a {\tt RESET} command,
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that is if the RESET_n bit isn't also set, then the trigger will first wait
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until the scope enters its {\tt PRIMED} state before the manual trigger takes
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effect.
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The last command that can affect the operation of the scope is the {\tt DISABLE}
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command/bit in the control register. Setting this bit will prevent the scope
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from triggering, or if triggered, it will prevent the scope from generating an
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interrupt.
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Finally, be careful how you set the clock enable line. If the clock enable
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line leaves the clock too often disabled, the scope might never prime in any
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reasonable amount of time.
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So, in summary, to use this scope you first set the holdoff value in the
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control register. Second, you wait until the scope has been triggered and
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stopped. Finally, you read from the data register once for every memory value
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in the buffer and you can then sit back, relax, and study what took place
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within the FPGA.
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\chapter{Registers}
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This scope core supports two registers, as listed in
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Tbl.~\ref{tbl:reglist}: a control register and a data register.
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\begin{table}[htbp]
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\begin{center}
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\begin{reglist}
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WBSCOPE & 0 & 32 & R/W & Configuration, control, and status of the
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scope.\\\hline
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WBSCOPEDATA & 1 & 32 & R/W & Read out register, to read out the data
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from the core. Writes to this register reset the read address
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to the beginning of the buffer, but are otherwise ignored.
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\\\hline
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\end{reglist}\caption{List of Registers}\label{tbl:reglist}
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\end{center}\end{table}
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Each register will be discussed in detail in this chapter.
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\section{Control Register}
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The bits in the control register are defined in Tbl.~\ref{tbl:control}.
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\begin{table}[htbp]
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\begin{center}
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\begin{bitlist}
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31 & R/W & RESET\_n. Write a `0' to this register to command a reset.
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Reading a `1' from this register means the reset has not finished
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crossing clock domains and is still pending.\\\hline
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30 & R & STOPPED, indicates that all collection has stopped.\\\hline
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29 & R & TRIGGERRED, indicates that a trigger has been recognized, and that
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the scope is counting for holdoff samples before stopping.\\\hline
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28 & R & PRIMED, indicates that the memory has been filled, and that the
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scope is now waiting on a trigger.\\\hline
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27 & R/W & MANUAL, set to invoke a manual trigger.\\\hline
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26 & R/W & DISABLE, set to disable the internal trigger. The scope may still
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be triggered manually.\\\hline
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25 & R & RZERO, this will be true whenever the scope's internal address
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register is pointed at the beginning of the memory.\\\hline
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20--24 & R & LGMEMLEN, the base two logarithm of the memory length. Thus,
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the memory internal to the scope is given by 1<<LGMEMLEN. \\\hline
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0--19 & R/W & Unsigned holdoff\\\hline
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\end{bitlist}
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\caption{Control Register}\label{tbl:control}
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\end{center}\end{table}
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The register has been designed so that one need only write the holdoff value to
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it, while leaving the other bits zero, to get the scope going. On such a write,
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the RESET\_n bit will be a zero, causing the scope to internally reset itself.
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Further, during normal operation, the high order nibble will go from 4'h8
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(a nearly instantaneous reset state) to 4'h0 (running), to 4'h1 (primed),
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to 4'h3 (triggered), and then stop at 4'h7 (primed, triggered, and stopped).
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Finally, user's are cautioned not to adjust the holdoff between the time the
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scope triggers and the time it stops--just to guarantee data coherency.
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While this approach works, the scope has some other capabilities. For example,
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if you set the MANUAL bit, the scope will trigger as soon as it is primed.
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If you set the MANUAL bit and the RESET\_n bit, it will trigger immediately
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if the scope was already primed. If not, a reset will take place, the scope
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will collect enough data to be primed, and then immediately trigger.
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A second optional capability is to disable the scope entirely. This might be
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useful if, for example, certain irrelevant things might trigger the scope.
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By setting the DISABLE bit, the scope will not automatically trigger. It will
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still record into its memory, and it will still prime itself, it will just
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not trigger automatically. The scope may still be manually triggered while
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the DISABLE bit is set. Likewise, if the DISABLE bit is set after the scope
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has been triggered, the scope will continue to its natural stopped state--it
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just won't generate an interrupt.
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There are two other interesting bits in this control register. The RZERO bit
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indicates that the next read from the data register will read from the first
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value in the memory, while the LGMEMLEN bits indicate how long the memory is.
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Thus, if LGMEMLEN is 10, the FIFO will be (1<<10) or 1024 words long, whereas
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if LGMEMLEN is 14, the FIFO will be (1<<14) or 16384 words long.
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\section{Data Register}
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This is perhaps the simplest register to explain. Before the core stops
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recording, reads from this register will produce reads of the bits going into
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the core, save only that they have not been protected from any meta-stability
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issues. This is useful for reading what's going on when the various lines are
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stuck. After the core stops recording, reads from this register return values
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from the stored memory. Further, after recording has stopped, every read
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increments an internal memory address, so that after $N$ reads (for however
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long the internal memory is), the entire memory has been returned over the bus.
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If you would like some assurance that you are reading from the beginning of the
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memory, you may either check the control register's {\tt RZERO} flag which will
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be `1' for the first value in the buffer, or you may write to the data register.
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Such writes will be ignored, save that they will reset the read address back
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to the beginning of the buffer.
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\chapter{Clocks}
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This scope supports two clocks: a wishbone bus clock, and a data clock.
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If the internal parameter ``SYNCHRONOUS'' is set to zero, proper transfers
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will take place between these two clocks. Setting this parameter to a one
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will save some flip flops and logic in implementation. The speeds of the
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respective clocks are based upon the speed of your device, and not specific
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to this core.
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\chapter{Wishbone Datasheet}\label{chap:wishbone}
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Tbl.~\ref{tbl:wishbone}
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\begin{table}[htbp]
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\begin{center}
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\begin{wishboneds}
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Revision level of wishbone & WB B4 spec \\\hline
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Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
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Port size & 32--bit \\\hline
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Port granularity & 32--bit \\\hline
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Maximum Operand Size & 32--bit \\\hline
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Data transfer ordering & (Irrelevant) \\\hline
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Clock constraints & None.\\\hline
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Signal Names & \begin{tabular}{ll}
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Signal Name & Wishbone Equivalent \\\hline
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{\tt i\_wb\_clk} & {\tt CLK\_I} \\
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{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
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{\tt i\_wb\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_we} & {\tt WE\_I} \\
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{\tt i\_wb\_addr} & {\tt ADR\_I} \\
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{\tt i\_wb\_data} & {\tt DAT\_I} \\
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{\tt o\_wb\_ack} & {\tt ACK\_O} \\
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{\tt o\_wb\_stall} & {\tt STALL\_O} \\
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{\tt o\_wb\_data} & {\tt DAT\_O}
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\end{tabular}\\\hline
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\end{wishboneds}
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\caption{Wishbone Datasheet}\label{tbl:wishbone}
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\end{center}\end{table}
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is required by the wishbone specification, and so
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it is included here. The big thing to notice is that this core
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acts as a wishbone slave, and that all accesses to the wishbone scope
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registers become 32--bit reads and writes to this interface. You may also wish
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to note that the scope supports pipeline reads from the data port, to speed
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up reading the results out.
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|
|
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\chapter{IO Ports}
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|
|
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The ports are listed in Table.~\ref{tbl:ioports}.
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\begin{table}[htbp]
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\begin{center}
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\begin{portlist}
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|
i\_clk & 1 & Input & \\\hline
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i\_ce & 1 & Input & Clock Enable. Set this high to clock data in and
|
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out.\\\hline
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i\_trigger & 1 & Input & An active high trigger line. If this trigger is
|
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set to one on any clock enabled data clock cycle, once
|
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the scope has been primed, it will then enter into its
|
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TRIGGERED state.
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\\\hline
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i\_data & 32 & Input & 32--wires of ... whatever you are interested in
|
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|
|
recording and later examining. These can be anything, only
|
343 |
|
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they should be synchronous with the data clock.
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|
\\\hline
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i\_wb\_clk & 1 & Input & The clock that the wishbone interface runs on.
|
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|
|
\\\hline
|
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|
|
i\_wb\_cyc & 1 & Input & Indicates a wishbone bus cycle is active when high.
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|
|
\\\hline
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|
i\_wb\_stb & 1 & Input & Indicates a wishbone bus cycle for this peripheral
|
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when high. (See the wishbone spec for more details) \\\hline
|
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|
|
i\_wb\_we & 1 & Input & Write enable, allows indicates a write to one of the
|
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two registers when i\_wb\_stb is also high.
|
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|
|
\\\hline
|
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i\_wb\_addr & 1 & Input & A single address line, set to zero to access the
|
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|
|
configuration and control regiseter, to one to access the data
|
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|
|
register. \\\hline
|
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|
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i\_wb\_data & 32 & Input & Data used when writing to the control register,
|
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|
|
ignored otherwise. \\\hline
|
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|
|
o\_wb\_ack & 1 & Output & Wishbone acknowledgement. This line will go high
|
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|
|
on the clock after any wishbone access, as long as the wishbone
|
361 |
|
|
{\tt i\_wb\_cyc} line remains high (i.e., no ack's if you
|
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|
|
terminate the cycle early).
|
363 |
|
|
\\\hline
|
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|
|
o\_wb\_stall & 1 & Output & Required by the wishbone spec, but always set to
|
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|
|
zero in this implementation.
|
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|
|
\\\hline
|
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|
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o\_wb\_data & 32 & Output & Values read, either control or data, headed back
|
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to the wishbone bus. These values will be valid during any
|
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|
|
read cycle when the {\tt i\_wb\_ack} line is high.
|
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|
|
\\\hline
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\end{portlist}
|
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|
|
\caption{List of IO ports}\label{tbl:ioports}
|
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|
|
\end{center}\end{table}
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At this point, most of these ports should have been well defined and described
|
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|
|
earlier in this document. The only new things are the data clock, {\tt i\_clk},
|
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|
|
the clock enable for the data, {\tt i\_ce}, the trigger, {\tt i\_trigger}, and
|
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|
|
the data of interest itself, {\tt i\_data}. Hopefully these are fairly self
|
378 |
|
|
explanatory by this point. If not, just remember the data, {\tt i\_data},
|
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|
|
are synchronous to the clock, {\tt i\_clk}. On every clock where the clock
|
380 |
|
|
enable line is high, {\tt i\_ce}, the data will be recorded until the scope
|
381 |
|
|
has stopped. Further, the scope will stop some programmable holdoff number
|
382 |
|
|
of clock enabled data clocks after {\tt i\_trigger} goes high. Further,
|
383 |
|
|
{\tt i\_trigger} need only be high for one clock cycle to be noticed by the
|
384 |
|
|
scope.
|
385 |
|
|
|
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% Appendices
|
387 |
|
|
% Index
|
388 |
|
|
\end{document}
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|
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|