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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbscopc.v
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//
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dgisselq |
// Project: WBScope, a wishbone hosted scope
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//
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// Purpose: This scope is identical in function to the wishbone scope
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dgisselq |
// found in wbscope, save that the output is compressed via a run-length
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// encoding scheme and that (as a result) it can only handle recording
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// 31 bits at a time. This allows the top bit to indicate the presence
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// of an 'address difference' rather than actual incoming recorded data.
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//
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// Reading/decompressing the output of this scope works in this fashion:
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// Once the scope has stopped, read from the port. Any time the high
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// order bit is set, the other 31 bits tell you how many times to repeat
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// the last value. If the high order bit is not set, then the value
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// is a new data value.
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//
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// Previous versions of the compressed scope have had some fundamental
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// flaws: 1) it was impossible to know when the trigger took place, and
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// 2) if things never changed, the scope would never fill or complete
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// its capture. These two flaws have been fixed with this release.
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dgisselq |
//
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// When dealing with a slow interface such as the PS/2 interface, or even
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// the 16x2 LCD interface, it is often true that things can change _very_
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// slowly. They could change so slowly that the standard wishbone scope
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// doesn't work. This scope then gives you a working scope, by sampling
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// at diverse intervals, and only capturing anything that changes within
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// those intervals.
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//
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// Indeed, I'm finding this compressed scope very valuable for evaluating
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// the timing associated with a GPS PPS and associated NMEA stream. I
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// need to collect over a seconds worth of data, and I don't have enough
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// memory to handle one memory value per clock, yet I still want to know
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// exactly when the GPS PPS goes high, when it goes low, when I'm
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// adjusting my clock, and when the clock's PPS output goes high. Did I
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// synchronize them well? Oh, and when does the NMEA time string show up
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// when compared with the PPS? All of those are valuable, but could never
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// be done if the scope wasn't compressed.
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dgisselq |
//
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// Creator: Dan Gisselquist, Ph.D.
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dgisselq |
// Gisselquist Technology, LLC
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dgisselq |
//
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////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module wbscopc(i_data_clk, i_ce, i_trigger, i_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_interrupt);
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parameter [4:0] LGMEM = 5'd10;
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parameter BUSW = 32, NELM=(BUSW-1);
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parameter [0:0] SYNCHRONOUS=1;
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parameter HOLDOFFBITS=20;
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parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
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parameter STEP_BITS=BUSW-1;
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parameter [(STEP_BITS-1):0] MAX_STEP= {(STEP_BITS){1'b1}};
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// The input signals that we wish to record
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input wire i_data_clk, i_ce, i_trigger;
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input wire [(NELM-1):0] i_data;
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// The WISHBONE bus for reading and configuring this scope
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input wire i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input wire i_wb_addr; // One address line only
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input wire [(BUSW-1):0] i_wb_data;
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output wire o_wb_ack, o_wb_stall;
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output reg [(BUSW-1):0] o_wb_data;
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// And, finally, for a final flair --- offer to interrupt the CPU after
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// our trigger has gone off. This line is equivalent to the scope
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// being stopped. It is not maskable here.
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output wire o_interrupt;
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reg [(LGMEM-1):0] raddr;
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reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
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// Our status/config register
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wire bw_reset_request, bw_manual_trigger,
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bw_disable_trigger, bw_reset_complete;
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reg [2:0] br_config;
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reg [(HOLDOFFBITS-1):0] br_holdoff;
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initial br_config = 3'b0;
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initial br_holdoff = DEFAULT_HOLDOFF;
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always @(posedge i_wb_clk)
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if ((i_wb_stb)&&(!i_wb_addr))
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begin
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if (i_wb_we)
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begin
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br_config <= { i_wb_data[31],
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i_wb_data[27],
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i_wb_data[26] };
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br_holdoff <= i_wb_data[(HOLDOFFBITS-1):0];
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end
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end else if (bw_reset_complete)
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br_config[2] <= 1'b1;
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assign bw_reset_request = (!br_config[2]);
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assign bw_manual_trigger = (br_config[1]);
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assign bw_disable_trigger = (br_config[0]);
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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generate
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if (SYNCHRONOUS > 0)
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begin
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assign dw_reset = bw_reset_request;
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assign dw_manual_trigger = bw_manual_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign bw_reset_complete = bw_reset_request;
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end else begin
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reg r_reset_complete;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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reg [2:0] r_iflags;
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// Resets are synchronous to the bus clock, not the data clock
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// so do a clock transfer here
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initial q_iflags = 3'b000;
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initial r_reset_complete = 1'b0;
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always @(posedge i_data_clk)
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begin
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q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
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r_iflags <= q_iflags;
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r_reset_complete <= (dw_reset);
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end
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assign dw_reset = r_iflags[2];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_disable_trigger = r_iflags[0];
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(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
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reg qq_reset_complete;
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// Pass an acknowledgement back from the data clock to the bus
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// clock that the reset has been accomplished
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initial q_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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always @(posedge i_wb_clk)
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begin
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q_reset_complete <= r_reset_complete;
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qq_reset_complete <= q_reset_complete;
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end
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assign bw_reset_complete = qq_reset_complete;
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end endgenerate
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//
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// Set up the trigger
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//
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//
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// Write with the i-clk, or input clock. All outputs read with the
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// WISHBONE-clk, or i_wb_clk clock.
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reg dr_triggered, dr_primed;
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wire dw_trigger;
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assign dw_trigger = (dr_primed)&&(
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((i_trigger)&&(!dw_disable_trigger))
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||(dw_manual_trigger));
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initial dr_triggered = 1'b0;
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always @(posedge i_data_clk)
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if (dw_reset)
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dr_triggered <= 1'b0;
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else if ((i_ce)&&(dw_trigger))
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dr_triggered <= 1'b1;
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//
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// Determine when memory is full and capture is complete
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//
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// Writes take place on the data clock
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// The counter is unsigned
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(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] holdoff_counter;
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reg dr_stopped;
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initial dr_stopped = 1'b0;
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initial holdoff_counter = 0;
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always @(posedge i_data_clk)
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if (dw_reset)
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holdoff_counter <= 0;
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else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
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begin
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holdoff_counter <= holdoff_counter + 1'b1;
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end
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always @(posedge i_data_clk)
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if ((!dr_triggered)||(dw_reset))
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dr_stopped <= 1'b0;
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else if ((i_ce)&&(!dr_stopped))
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begin
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if (HOLDOFFBITS > 1) // if (i_ce)
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dr_stopped <= (holdoff_counter >= br_holdoff);
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else if (HOLDOFFBITS <= 1)
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dr_stopped <= ((i_ce)&&(dw_trigger));
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end
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localparam DLYSTOP=5;
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reg [(DLYSTOP-1):0] dr_stop_pipe;
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always @(posedge i_data_clk)
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if (dw_reset)
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dr_stop_pipe <= 0;
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else if (i_ce)
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dr_stop_pipe <= { dr_stop_pipe[(DLYSTOP-2):0], dr_stopped };
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wire dw_final_stop;
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assign dw_final_stop = dr_stop_pipe[(DLYSTOP-1)];
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// A big part of this scope is the run length of any particular
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// data value. Hence, when the address line (i.e. data[31])
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// is high on decompression, the run length field will record an
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dgisselq |
// address difference.
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//
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dgisselq |
// To implement this, we set our run length to zero any time the
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dgisselq |
// data changes, but increment it on all other clocks. Should the
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// address difference get to our maximum value, we let it saturate
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// rather than overflow.
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dgisselq |
reg [(STEP_BITS-1):0] ck_addr;
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reg [(NELM-1):0] qd_data;
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reg dr_force_write, dr_run_timeout,
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new_data;
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//
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// The "dr_force_write" logic here is designed to make sure we write
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// at least every MAX_STEP samples, and that we stop as soon as
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// we are able. Hence, if an interface is slow
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// and idle, we'll at least prime the scope, and even if the interface
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// doesn't have enough transitions to fill our buffer, we'll at least
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// fill the buffer with repeats.
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//
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249 |
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reg dr_force_inhibit;
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dgisselq |
initial ck_addr = 0;
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dgisselq |
initial dr_force_write = 1'b0;
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always @(posedge i_data_clk)
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if (dw_reset)
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begin
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255 |
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dr_force_write <= 1'b1;
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256 |
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dr_force_inhibit <= 1'b0;
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257 |
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end else if (i_ce)
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258 |
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begin
|
259 |
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dr_force_inhibit <= (dr_force_write);
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260 |
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if ((dr_run_timeout)&&(!dr_force_write)&&(!dr_force_inhibit))
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261 |
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dr_force_write <= 1'b1;
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262 |
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else if (((dw_trigger)&&(!dr_triggered))||(!dr_primed))
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263 |
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dr_force_write <= 1'b1;
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264 |
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else
|
265 |
|
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dr_force_write <= 1'b0;
|
266 |
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end
|
267 |
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|
268 |
|
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//
|
269 |
|
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// Keep track of how long it has been since the last write
|
270 |
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//
|
271 |
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always @(posedge i_data_clk)
|
272 |
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if (dw_reset)
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273 |
3 |
dgisselq |
ck_addr <= 0;
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274 |
13 |
dgisselq |
else if (i_ce)
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275 |
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begin
|
276 |
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if ((dr_force_write)||(new_data)||(dr_stopped))
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277 |
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ck_addr <= 0;
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278 |
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else
|
279 |
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ck_addr <= ck_addr + 1'b1;
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280 |
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end
|
281 |
3 |
dgisselq |
|
282 |
13 |
dgisselq |
always @(posedge i_data_clk)
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283 |
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if (dw_reset)
|
284 |
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dr_run_timeout <= 1'b1;
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285 |
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else if (i_ce)
|
286 |
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dr_run_timeout <= (ck_addr >= MAX_STEP-1'b1);
|
287 |
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|
288 |
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always @(posedge i_data_clk)
|
289 |
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if (dw_reset)
|
290 |
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new_data <= 1'b1;
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291 |
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else if (i_ce)
|
292 |
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new_data <= (i_data != qd_data);
|
293 |
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|
294 |
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always @(posedge i_data_clk)
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295 |
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if (i_ce)
|
296 |
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qd_data <= i_data;
|
297 |
|
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|
298 |
12 |
dgisselq |
wire [(BUSW-2):0] w_data;
|
299 |
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generate
|
300 |
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if (NELM == BUSW-1)
|
301 |
13 |
dgisselq |
assign w_data = qd_data;
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302 |
12 |
dgisselq |
else
|
303 |
13 |
dgisselq |
assign w_data = { {(BUSW-NELM-1){1'b0}}, qd_data };
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304 |
12 |
dgisselq |
endgenerate
|
305 |
13 |
dgisselq |
|
306 |
6 |
dgisselq |
//
|
307 |
13 |
dgisselq |
// To do our RLE compression, we keep track of two registers: the most
|
308 |
6 |
dgisselq |
// recent data to the device (imm_ prefix) and the data from one
|
309 |
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// clock ago. This allows us to suppress writes to the scope which
|
310 |
|
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// would otherwise be two address writes in a row.
|
311 |
|
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reg imm_adr, lst_adr; // Is this an address (1'b1) or data value?
|
312 |
8 |
dgisselq |
reg [(BUSW-2):0] lst_val, // Data for the scope, delayed by one
|
313 |
6 |
dgisselq |
imm_val; // Data to write to the scope
|
314 |
3 |
dgisselq |
initial lst_adr = 1'b1;
|
315 |
|
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initial imm_adr = 1'b1;
|
316 |
13 |
dgisselq |
always @(posedge i_data_clk)
|
317 |
|
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if (dw_reset)
|
318 |
3 |
dgisselq |
begin
|
319 |
|
|
imm_val <= 31'h0;
|
320 |
|
|
imm_adr <= 1'b1;
|
321 |
|
|
lst_val <= 31'h0;
|
322 |
|
|
lst_adr <= 1'b1;
|
323 |
13 |
dgisselq |
end else if (i_ce)
|
324 |
3 |
dgisselq |
begin
|
325 |
13 |
dgisselq |
if ((new_data)||(dr_force_write)||(dr_stopped))
|
326 |
|
|
begin
|
327 |
|
|
imm_val <= w_data;
|
328 |
|
|
imm_adr <= 1'b0; // Last thing we wrote was data
|
329 |
|
|
lst_val <= imm_val;
|
330 |
|
|
lst_adr <= imm_adr;
|
331 |
|
|
end else begin
|
332 |
|
|
imm_val <= ck_addr; // Minimum value here is '1'
|
333 |
|
|
imm_adr <= 1'b1; // This (imm) is an address
|
334 |
|
|
lst_val <= imm_val;
|
335 |
|
|
lst_adr <= imm_adr;
|
336 |
|
|
end
|
337 |
3 |
dgisselq |
end
|
338 |
|
|
|
339 |
6 |
dgisselq |
//
|
340 |
|
|
// Here's where we suppress writing pairs of address words to the
|
341 |
|
|
// scope at once.
|
342 |
|
|
//
|
343 |
13 |
dgisselq |
reg record_ce;
|
344 |
3 |
dgisselq |
reg [(BUSW-1):0] r_data;
|
345 |
13 |
dgisselq |
initial record_ce = 1'b0;
|
346 |
|
|
always @(posedge i_data_clk)
|
347 |
|
|
record_ce <= (i_ce)&&((!lst_adr)||(!imm_adr))&&(!dr_stop_pipe[2]);
|
348 |
|
|
always @(posedge i_data_clk)
|
349 |
|
|
r_data <= ((!lst_adr)||(!imm_adr))
|
350 |
3 |
dgisselq |
? { lst_adr, lst_val }
|
351 |
13 |
dgisselq |
: { {(32 - NELM){1'b0}}, qd_data };
|
352 |
3 |
dgisselq |
|
353 |
13 |
dgisselq |
//
|
354 |
|
|
// Actually do our writes to memory. Record, via 'primed' when
|
355 |
|
|
// the memory is full.
|
356 |
|
|
//
|
357 |
|
|
// The 'waddr' address that we are using really crosses two clock
|
358 |
|
|
// domains. While writing and changing, it's in the data clock
|
359 |
|
|
// domain. Once stopped, it becomes part of the bus clock domain.
|
360 |
|
|
// The clock transfer on the stopped line handles the clock
|
361 |
|
|
// transfer for these signals.
|
362 |
|
|
//
|
363 |
|
|
reg [(LGMEM-1):0] waddr;
|
364 |
|
|
initial waddr = {(LGMEM){1'b0}};
|
365 |
|
|
initial dr_primed = 1'b0;
|
366 |
|
|
always @(posedge i_data_clk)
|
367 |
|
|
if (dw_reset) // For simulation purposes, supply a valid value
|
368 |
|
|
begin
|
369 |
|
|
waddr <= 0; // upon reset.
|
370 |
|
|
dr_primed <= 1'b0;
|
371 |
|
|
end else if (record_ce)
|
372 |
|
|
begin
|
373 |
|
|
// mem[waddr] <= i_data;
|
374 |
|
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
375 |
|
|
dr_primed <= (dr_primed)||(&waddr);
|
376 |
|
|
end
|
377 |
|
|
always @(posedge i_data_clk)
|
378 |
|
|
if (record_ce)
|
379 |
|
|
mem[waddr] <= r_data;
|
380 |
11 |
dgisselq |
|
381 |
13 |
dgisselq |
|
382 |
6 |
dgisselq |
//
|
383 |
11 |
dgisselq |
//
|
384 |
13 |
dgisselq |
//
|
385 |
|
|
// Bus response
|
386 |
|
|
//
|
387 |
|
|
//
|
388 |
11 |
dgisselq |
|
389 |
13 |
dgisselq |
//
|
390 |
|
|
// Clock transfer of the status signals
|
391 |
|
|
//
|
392 |
|
|
wire bw_stopped, bw_triggered, bw_primed;
|
393 |
|
|
generate
|
394 |
|
|
if (SYNCHRONOUS > 0)
|
395 |
|
|
begin
|
396 |
|
|
assign bw_stopped = dw_final_stop;
|
397 |
|
|
assign bw_triggered = dr_triggered;
|
398 |
|
|
assign bw_primed = dr_primed;
|
399 |
|
|
end else begin
|
400 |
|
|
// These aren't a problem, since none of these are strobe
|
401 |
|
|
// signals. They goes from low to high, and then stays high
|
402 |
|
|
// for many clocks. Swapping is thus easy--two flip flops to
|
403 |
|
|
// protect against meta-stability and we're done.
|
404 |
|
|
//
|
405 |
|
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
|
406 |
|
|
reg [2:0] r_oflags;
|
407 |
|
|
initial q_oflags = 3'h0;
|
408 |
|
|
initial r_oflags = 3'h0;
|
409 |
|
|
always @(posedge i_wb_clk)
|
410 |
|
|
if (bw_reset_request)
|
411 |
|
|
begin
|
412 |
|
|
q_oflags <= 3'h0;
|
413 |
|
|
r_oflags <= 3'h0;
|
414 |
|
|
end else begin
|
415 |
|
|
q_oflags <= { dw_final_stop, dr_triggered, dr_primed };
|
416 |
|
|
r_oflags <= q_oflags;
|
417 |
|
|
end
|
418 |
11 |
dgisselq |
|
419 |
13 |
dgisselq |
assign bw_stopped = r_oflags[2];
|
420 |
|
|
assign bw_triggered = r_oflags[1];
|
421 |
|
|
assign bw_primed = r_oflags[0];
|
422 |
|
|
end endgenerate
|
423 |
|
|
|
424 |
|
|
|
425 |
11 |
dgisselq |
//
|
426 |
13 |
dgisselq |
// Reads use the bus clock
|
427 |
6 |
dgisselq |
//
|
428 |
13 |
dgisselq |
reg br_wb_ack, br_pre_wb_ack;
|
429 |
|
|
initial br_wb_ack = 1'b0;
|
430 |
|
|
wire bw_cyc_stb;
|
431 |
|
|
assign bw_cyc_stb = (i_wb_stb);
|
432 |
|
|
initial br_pre_wb_ack = 1'b0;
|
433 |
|
|
initial br_wb_ack = 1'b0;
|
434 |
|
|
always @(posedge i_wb_clk)
|
435 |
|
|
begin
|
436 |
|
|
if ((bw_reset_request)
|
437 |
|
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
438 |
|
|
raddr <= 0;
|
439 |
|
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
|
440 |
|
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
441 |
|
|
|
442 |
|
|
br_pre_wb_ack <= bw_cyc_stb;
|
443 |
|
|
br_wb_ack <= (br_pre_wb_ack)&&(i_wb_cyc);
|
444 |
|
|
end
|
445 |
|
|
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
reg [(LGMEM-1):0] this_addr;
|
449 |
|
|
always @(posedge i_wb_clk)
|
450 |
|
|
if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we))
|
451 |
|
|
this_addr <= raddr + waddr + 1'b1;
|
452 |
|
|
else
|
453 |
|
|
this_addr <= raddr + waddr;
|
454 |
|
|
|
455 |
|
|
reg [31:0] nxt_mem;
|
456 |
|
|
always @(posedge i_wb_clk)
|
457 |
|
|
nxt_mem <= mem[this_addr];
|
458 |
|
|
|
459 |
|
|
wire [19:0] full_holdoff;
|
460 |
|
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
461 |
|
|
generate if (HOLDOFFBITS < 20)
|
462 |
|
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
463 |
|
|
endgenerate
|
464 |
|
|
|
465 |
|
|
wire [4:0] bw_lgmem;
|
466 |
|
|
assign bw_lgmem = LGMEM;
|
467 |
|
|
always @(posedge i_wb_clk)
|
468 |
|
|
if (!i_wb_addr) // Control register read
|
469 |
|
|
o_wb_data <= { bw_reset_request,
|
470 |
|
|
bw_stopped,
|
471 |
|
|
bw_triggered,
|
472 |
|
|
bw_primed,
|
473 |
|
|
bw_manual_trigger,
|
474 |
|
|
bw_disable_trigger,
|
475 |
|
|
(raddr == {(LGMEM){1'b0}}),
|
476 |
|
|
bw_lgmem,
|
477 |
|
|
full_holdoff };
|
478 |
|
|
else if (!bw_stopped) // read, prior to stopping
|
479 |
|
|
o_wb_data <= {1'b0, w_data };// Violates clk tfr rules
|
480 |
|
|
else // if (i_wb_addr) // Read from FIFO memory
|
481 |
|
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
482 |
|
|
|
483 |
|
|
assign o_wb_stall = 1'b0;
|
484 |
|
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
485 |
|
|
|
486 |
|
|
reg br_level_interrupt;
|
487 |
|
|
initial br_level_interrupt = 1'b0;
|
488 |
|
|
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
|
489 |
|
|
&&(!br_level_interrupt);
|
490 |
|
|
always @(posedge i_wb_clk)
|
491 |
14 |
dgisselq |
if ((bw_reset_complete)||(bw_reset_request))
|
492 |
|
|
br_level_interrupt<= 1'b0;
|
493 |
|
|
else
|
494 |
|
|
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
|
495 |
13 |
dgisselq |
|
496 |
|
|
// Make Verilator happy
|
497 |
|
|
// verilator lint_off UNUSED
|
498 |
14 |
dgisselq |
wire [3+6+(20-HOLDOFFBITS)-1:0] unused;
|
499 |
13 |
dgisselq |
assign unused = { i_wb_data[30:28], i_wb_data[25:HOLDOFFBITS] };
|
500 |
|
|
// verilator lint_on UNUSED
|
501 |
|
|
|
502 |
3 |
dgisselq |
endmodule
|