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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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// Filename: cfgscope.cpp
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//
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// Project: FPGA library development (Basys-3 development board)
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//
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// Purpose: To read out, and decompose, the results of the wishbone scope
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// as applied to the ICAPE2 interaction.
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//
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// This is provided together with the wbscope project as an
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// example of what might be done with the wishbone scope.
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// The intermediate details, though, between this and the
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// wishbone scope are not part of the wishbone scope project.
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//
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// Using this particular scope made it a *lot* easier to get the
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// ICAPE2 interface up and running, since I was able to see what
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// was going right (or wrong) with the interface as I was
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// developing it. Sure, it would've been better to get it to work
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// under a simulator instead of with the scope, but not being
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// certain of how the interface was supposed to work made building
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// a simulator difficult.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <strings.h>
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#include <ctype.h>
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#include <string.h>
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#include <signal.h>
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#include <assert.h>
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#include "port.h"
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#include "llcomms.h" // This defines how we talk to the device over wishbone
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#include "regdefs.h"
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// Here are the two registers needed for accessing our scope: A control register
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// and a data register.
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#define WBSCOPE R_CFGSCOPE
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#define WBSCOPEDATA R_CFGSCOPED
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//
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// The DEVBUS structure encapsulates wishbone accesses, so that this code can
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// access the wishbone bus on the FPGA.
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DEVBUS *m_fpga;
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void closeup(int v) {
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m_fpga->kill();
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exit(0);
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}
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int main(int argc, char **argv) {
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// Open up a port to talk to the FPGA ...
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#ifndef FORCE_UART
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m_fpga = new FPGA(new NETCOMMS("lazarus",PORT));
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#else
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m_fpga = new FPGA(new TTYCOMMS("/dev/ttyUSB2"));
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#endif
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signal(SIGSTOP, closeup);
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signal(SIGHUP, closeup);
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// Check to see whether or not the scope has captured the data we need
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// yet or not. If not, exit kindly.
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unsigned v, lgln, scoplen;
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v = m_fpga->readio(WBSCOPE);
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if (0x60000000 != (v & 0x60000000)) {
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printf("Scope is not yet ready:\n");
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printf("\tRESET:\t\t%s\n", (v&0x80000000)?"Ongoing":"Complete");
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printf("\tSTOPPED:\t%s\n", (v&0x40000000)?"Yes":"No");
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printf("\tTRIGGERED:\t%s\n", (v&0x20000000)?"Yes":"No");
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printf("\tPRIMED:\t\t%s\n", (v&0x10000000)?"Yes":"No");
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printf("\tMANUAL:\t\t%s\n", (v&0x08000000)?"Yes":"No");
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printf("\tDISABLED:\t%s\n", (v&0x04000000)?"Yes":"No");
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printf("\tZERO:\t\t%s\n", (v&0x02000000)?"Yes":"No");
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exit(0);
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}
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// Since the length of the scope memory is a configuration parameter
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// internal to the scope, we read it here to find out how it was
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// configured.
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lgln = (v>>20) & 0x1f;
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scoplen = (1<<lgln);
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DEVBUS::BUSW *buf;
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buf = new DEVBUS::BUSW[scoplen];
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// There are two means of reading from a DEVBUS interface: The first
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// is a vector read, optimized so that the address and read command
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// only needs to be sent once. This is the optimal means. However,
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// if the bus isn't (yet) trustworthy, it may be more reliable to access
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// the port by reading one register at a time--hence the second method.
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// If the bus works, you'll want to use readz(): read scoplen values
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// into the buffer, from the address WBSCOPEDATA, without incrementing
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// the address each time (hence the 'z' in readz--for zero increment).
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if (true) {
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m_fpga->readz(WBSCOPEDATA, scoplen, buf);
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printf("Vector read complete\n");
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} else {
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for(int i=0; i<scoplen; i++)
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buf[i] = m_fpga->readio(WBSCOPEDATA);
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}
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// Now, let's decompose our 32-bit wires into something ... meaningful.
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// This section will change from project to project, scope to scope,
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// depending on what wires are placed into the scope.
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for(int i=0; i<scoplen; i++) {
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if ((i>0)&&(buf[i] == buf[i-1])&&
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(i<scoplen-1)&&(buf[i] == buf[i+1]))
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continue;
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printf("%6d %08x:", i, buf[i]);
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printf("%s %s ", (buf[i]&0x80000000)?" ":"CS",
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(buf[i]&0x40000000)?"RD":"WR");
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unsigned cw = (buf[i]>>24)&0x03f;
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switch(cw) {
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case 0x20: printf("DUMMY"); break;
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case 0x10: printf("NOOP "); break;
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case 0x08: printf("SYNC "); break;
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case 0x04: printf("CMD "); break;
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case 0x02: printf("IPROG"); break;
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case 0x01: printf("DSYNC"); break;
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default: printf("OTHER"); break;
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}
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printf(" -> %02x\n", buf[i] & 0x0ffffff);
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}
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// Clean up our interface, now, and we're done.
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delete m_fpga;
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}
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