- uartsim defines a C++ class that can be used for simulating a UART within
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Verilator. This class can be used both to generate valid UART signaling,
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to determine if your configuration can receive it properly, as well as to decode
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valid UART signaling to determine if your configuration is properly setting the
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UART signaling wire.
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- speech.txt, and the associated speech.hex file, is the text that speechfifo
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will transmit. It is currently set to the Gettysburg Address. While you are welcome to change this, the length of this file is hard coded within the verilog file that references it.
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- mkspeech, a Verilog hex file generator--although it also converts newlines to
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carriage-return newline pairs
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- Demonstration projects using these:
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-- helloworld, exercises and tests the helloworld.v test bench
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-- linetest, exercises and tests the linetest.v test bench. This also creates a .VCD file which can be viewed via GTKwave
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-- speechtest, exercises and tests the speechfifo test bench. When run with the -i option, speechtest will also generate a .VCD file for use with GTKwave.
