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[/] [wbuart32/] [trunk/] [bench/] [verilog/] [echotest.v] - Blame information for rev 15

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1 6 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    echotest.v
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//
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// Project:     wbuart32, a full featured UART with simulator
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//
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// Purpose:     To test that the txuart and rxuart modules work properly, by
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//              echoing the input directly to the output.
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//
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//      This module may be run as either a DUMBECHO, simply forwarding the input
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//      wire to the output with a touch of clock in between, or it can run as
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//      a smarter echo routine that decodes text before returning it.  The
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//      difference depends upon whether or not OPT_DUMBECHO is defined, as 
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//      discussed below.
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//
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//      With some modifications (discussed below), this RTL should be able to
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//      run as a top-level testing file, requiring only the transmit and receive
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//      UART pins and the clock to work.
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//
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//      DON'T FORGET TO TURN OFF HARDWARE FLOW CONTROL!  ... or this'll never
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//      work.  If you want to run with hardware flow control on, add another
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//      wire to this module in order to set o_cts to 1'b1.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Uncomment the next line defining OPT_DUMBECHO in order to test the wires
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// and external functionality of any UART, independent of the UART protocol.
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//
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`define OPT_DUMBECHO
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//
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//
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// One issue with the design is how to set the values of the setup register.
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// (*This is a comment, not a verilator attribute ... )  Verilator needs to
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// know/set those values in order to work.  However, this design can also be
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// used as a stand-alone top level configuration file.  In this latter case,
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// the setup register needs to be set internal to the file.  Here, we use
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// OPT_STANDALONE to distinguish between the two.  If set, the file runs under
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// external environment.  If not, it must be set internally.
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//
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`endif
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//
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//
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// Two versions of the UART can be found in the rtl directory: a full featured
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// UART, and a LITE UART that only handles 8N1 -- no break sending, break
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// detection, parity error detection, etc.  If we set USE_LITE_UART here, those
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// simplified UART modules will be used.
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//
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// `define      USE_LITE_UART
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//
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//
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module  echotest(i_clk,
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`ifndef OPT_STANDALONE
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                        i_setup,
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`endif
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                        i_uart_rx, o_uart_tx);
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        input           i_clk;
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`ifndef OPT_STANDALONE
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        input   [30:0]   i_setup;
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`endif
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        input           i_uart_rx;
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        output  wire    o_uart_tx;
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`ifdef  OPT_DUMBECHO
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        reg     r_uart_tx;
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        initial r_uart_tx = 1'b1;
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        always @(posedge i_clk)
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                r_uart_tx <= i_uart_rx;
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        assign  o_uart_tx = r_uart_tx;
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`else
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        // This is the "smart" echo verion--one that decodes, and then
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        // re-encodes, values over the UART.  There is a risk, though, doing
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        // things in this manner that the receive UART might run *just* a touch
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        // faster than the transmitter, and hence drop a bit every now and
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        // then.  Hence, it works nicely for hand-testing, but not as nicely
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        // for high-speed UART testing.
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        // If i_setup isnt set up as an input parameter, it needs to be set.
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        // We do so here, to a setting appropriate to create a 115200 Baud
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        // comms system from a 100MHz clock.  This also sets us to an 8-bit
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        // data word, 1-stop bit, and no parity.
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        //
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        // This code only applies if OPT_DUMBECHO is not defined.
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`ifdef  OPT_STANDALONE
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        wire    [30:0]   i_setup;
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        assign          i_setup = 31'd868;      // 115200 Baud, if clk @ 100MHz
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`endif
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        // Create a reset line that will always be true on a power on reset
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        reg     pwr_reset;
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        initial pwr_reset = 1'b1;
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        always @(posedge i_clk)
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                pwr_reset = 1'b0;
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        // The UART Receiver
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        //
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        // This is where everything begins, by reading data from the UART.
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        //
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        // Data (rx_data) is present when rx_stb is true.  Any parity or
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        // frame errors will also be valid at that time.  Finally, we'll ignore
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        // errors, and even the clocked uart input distributed from here.
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        //
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        // This code only applies if OPT_DUMBECHO is not defined.
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        wire    rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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        wire    [7:0]    rx_data;
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`ifdef  USE_LITE_UART
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        //
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        // NOTE: this depends upon the Verilator implementation using a setup
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        // of 868, since we cannot change the setup of the RXUARTLITE module.
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        //
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        rxuartlite      #(24'd868)
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                receiver(i_clk, i_uart_rx, rx_stb, rx_data);
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`else
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        rxuart  receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
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                        rx_break, rx_perr, rx_ferr, rx_ignored);
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`endif
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        // Bypass any transmit hardware flow control.
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        wire    cts_n;
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        assign cts_n = 1'b0;
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        wire    tx_busy;
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`ifdef  USE_LITE_UART
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        //
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        // NOTE: this depends upon the Verilator implementation using a setup
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        // of 868, since we cannot change the setup of the TXUARTLITE module.
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        //
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        txuartlite #(24'd868)
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                transmitter(i_clk, rx_stb, rx_data, o_uart_tx, tx_busy);
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`else
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        txuart  transmitter(i_clk, pwr_reset, i_setup, rx_break,
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                        rx_stb, rx_data, rts, o_uart_tx, tx_busy);
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`endif
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`endif
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endmodule
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