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\documentclass{gqtekspec}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename: spec.tex
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%%
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%% Project: wbuart32, a full featured UART with simulator
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%%
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%% Purpose: To describe, for LaTeX, how to build the specification file
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%% for the wbuart32 core(s). This file is not nearly as
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%% interesting as the file it creates, so I suggest you read spec.pdf
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%% first, before deciding you are really interested in this file.
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%%
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%% Creator: Dan Gisselquist, Ph.D.
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%% Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015-2016, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program. (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.) If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License: GPL, v3, as defined and found on www.gnu.org,
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%% http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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\usepackage{import}
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\usepackage{bytefield}
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\usepackage{amsmath}
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\project{WBUART32}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.1}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\titlepage
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC.
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
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\end{license}
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\begin{revisionhistory}
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0.1 & 8/26/2016 & D. Gisselquist & Initial Draft Specification\\\hline
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\end{revisionhistory}
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% Revision History
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% Table of Contents, named Contents
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\tableofcontents
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\listoffigures
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\listoftables
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\begin{preface}
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It may be that building a UART is a mandatory coming of age task for any HDL
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designer. The task is simple, easy, and there's not all that much to it.
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This project comes out of some of my first experiences with Verilog.
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Since then, it has been augmented with a very useful capability for
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simulating a UART connection when using Verilator. It is this, perhaps
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unusual, addition to the core set that makes this core worth taking note of.
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I hope you find it useful.
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\end{preface}
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\chapter{Introduction}\label{ch:intro}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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%
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% Introduction
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%
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% This section contains the introduction to the core, describing both its
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% use and its features.
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%
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% What is old
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The Universal Asynchronous Serial Transport, or UART, has become quite the
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common protocol between devices. It is simple to wire up, easy to use, and
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easy to process. This core provides one implementation of the logic necessary
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to use such a communications scheme.
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% What does the old lack?
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% What is new
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% What does the new have that the old lacks
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% What performance gain can be expected?
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While you are likely to find many UART examples out there, this particular
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UART implementation offers something many of these other examples do not: a
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Verilator simulation capability. This will allow the user to connect, via
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a TCP/IP port or a telnet application, to the UART of their desired chip. As
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a result, full two-way interaction can be had between a simulation and a
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terminal or other port. Indeed, this may even be sufficient to connect a
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CPU, capable of running Linux, to a terminal to verify that yes it can truly
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run Linux--all within Verilator.
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\chapter{Architecture}\label{ch:arch}
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The HDL portion of the core itself consists of three files: {\tt rxuart.v},
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{\tt txuart.v}, and {\tt wbuart-insert.v}. These are, respectively, the
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receive UART code, the transmit UART code, and an example of how the receiver
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and transmitter may be connected to a Wishbone bus.
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Each of the core files, {\tt rxuart.v} and {\tt txuart.v}, are fully capable.
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They each accept a 29--bit setup value specifying baud rate, the number of bits
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per byte (between 5 and 8), whether or not parity is used, whether that parity
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is even, odd, or fixed mark or fixed space. This setup register will be
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discussed further in Chap.\ref{ch:registers}.
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A further note on the {\tt rxuart.v} module is in order. This module double
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latches the input, in the proper two buffer fashion to avoid problems with
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metastability. Then, upon the detection of the start bit (i.e. a high to low
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transition), the port waits a half of a baud, and then starts its baud clock
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so as to sample in the middle of every baud following. The result of this is
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a timing requirement: after $N+2$ baud intervals ($N+3$ if parity is used),
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where $N$ is the number of bits per byte, this calculated middle sample must
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still lie within the associated bit period. This leaves us with the criteria
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that,
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\begin{eqnarray}
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\left|\left(N+2\right)
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\left(\frac{f_{\mbox{\tiny SYS}}}{f_{\mbox{\tiny BAUD}}}
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-{\mbox{\tt CKS}}\right)\right|
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&<& \frac{f_{\mbox{\tiny SYS}}}{2f_{\mbox{\tiny BAUD}}},
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\label{eqn:baudlimit}.
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\end{eqnarray}
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where $f_{\mbox{\tiny SYS}}$ is the system clock frequency,
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$f_{\mbox{\tiny BAUD}}$ is the baud rate or frequency,
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{\tt CKS} is the number of clocks per baud as set in the configuration
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register, and $N$ is the number of bits per byte. What this means is that,
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for transmission rates where $f_{\mbox{\tiny BAUD}}$ approaches
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$f_{\mbox{\tiny SYS}}$, the number of data rates that can actually be
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synthesized becomes limited.
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Connecting to either {\tt txuart.v} or {\tt rxuart.v} is quite simple. Both
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files have a data port and a strobe. To transmit, set the data and strobe
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lines. Drop the strobe line as soon as the strobe is asserted and the busy line
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is not. Likewise, to connect to the {\tt rxuart.v} port, there is a data
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and a strobe. This time, though, these two wires are outputs of the port as
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opposed to inputs.
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When the strobe is high, the data is valid. It will only be high for one
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clock period. If you wish to connect this output to a bus, a register will be
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needed to hold the strobe high until the data is read. Also, while the strobe
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is high, the {\tt o\_break} line will indicate whether the receiver is in a
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``break'' state, {\tt o\_frame\_err} will indicate whether or not there was a
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framing error (i.e., no stop bit), and {\tt o\_parity\_err} will indicate
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wheher or not the parity matched.
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The {\tt tx\_busy} line may be inverted and connected to a transmit interrupt
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line. In a similar fashion, the {\tt rx\_stb} line, or the bus equivalent of
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{\tt rx\_ready}, may be used for receive interrupt lines.
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An example of how to put this configuration together is found in
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{\tt wbuart-insert.v}. In this example given, the {\tt rx\_data} register
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will have only the lower eight bits set if the data is valid, higher bits will
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be set upon error conditions, and cleared automatically upon the next byte read.
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In a similar fashion, the {\tt tx\_data} register can be written to with a byte
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in order to transmit that byte. Writing bit nine will place the transmitter
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into a ``break'' condition, only cleared by writing a zero to that bit later.
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Reading from the {\tt tx\_data} register can also be used to determine if the
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transmitter is busy (via polling), whether it is currently in a break condition,
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or even what bit is currently being placed to the output port.
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The C++ simulation portion of the code revolves around the file
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{\tt bench/cpp/uartsim.cpp} and its associated header. This file defines a
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class, {\tt UARTSIM}, which can be used to connect the UART to a TCP/IP stream.
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When initialized, this class takes, as input, the TCP/IP port number that the
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class is to connect with. Once connected, using this is as simple as
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calculating the receive input bit from the transmit output bit when the
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clock is low, and the core takes care of everything else.
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\chapter{Operation}\label{ch:ops}
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% This section describes the operation of the core. Specific sequences, such
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% as startup sequences, as well as the modes and states of the block should be
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% described.
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%
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To use the core, a couple of steps are required. First, wire it up. The
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{\tt wbuart-insert.v} file should provide a good example of how to wire it up.
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Second, set the UART configuration register. This is ideally set in an
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initial statement within the code somewhere, but can easily be set elsewhere
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by writing to this register from the bus.
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From a simulation standpoint, it will also need to be wired up. Somewhere,
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internal to the top--level Verilator C++ simulation file, you'll want to
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have a line similar to,
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\begin{tabbing}
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{\tt if (!clk)} \= \\
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\> {\tt tb->i\_rx} {\tt = } {\tt uartsim(tb->o\_uart, setup);}
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\end{tabbing}
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To use the transmitter, set the {\tt i\_stb} and {\tt i\_data} wires. Drop
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the strobe line any time after {\tt (i\_stb)\&\&(!o\_busy)}.
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To use the receiver, grab the data any time {\tt o\_stb} is true.
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From the standpoint of the bus, there are two ways to handle receiving and
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transmitting: polling and interrupt based, although both work one character at
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a time. To poll, repeatedly read the receive data register until only no
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bits but the bottom eight are set. This is an indication that the byte is
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valid. Alternatively, you could wait until the an interrupt line is set and
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then read. In the {\tt wbuart-insert.v} example, the {\tt rx\_int} line will
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be set, and automatically cleared upon any read. To write, one can read from
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the transmit data register until the eighth bit, the {\tt tx\_busy} bit, is
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cleared, and then transmit. Alternatively, this negation of this bit may be
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connected to an interrupt line. Writing to the port while idle will start
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it transmitting. Writing to the port while it is busy will fill a one word
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buffer that will get sent as soon as the port is idle for one clock.
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\chapter{Registers}\label{ch:registers}
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% This section specifies all internal registers. It should completely cover
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% the interface between the CPU and the host as seen from the software point
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% of view.
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% List of Registers
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% Register 1 Description
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%
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% You shall choose the style of register you prefer. Do not use both options
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% in one and the same document. (Table of bits, vs. byetarray type of
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% description).
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The core really only has one register associated with it, which is the setup
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register. The format of this register is important, although not necessarily
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trivial or obvious. We'll cover two other registers here, though, associated
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with the example wishbone connections from {\tt wbuart-insert.v}. All three
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of these registers are shown in Tbl.~\ref{tbl:reglist}.
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\begin{table}
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\begin{center}
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\begin{reglist}
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SETUP & & 30 & R/W & UART configuration/setup register.\\\hline
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RX\_DATA & & 12 & R(/W) & Read data, reads from the UART.\\\hline
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TX\_DATA & & 12 & (R/)W & Transmit data: writes send out the UART.\\\hline
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\end{reglist}\caption{UART Registers}\label{tbl:reglist}
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\end{center}\end{table}
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Since the connections presented are only examples, they are listed without
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addresses, as their wishbone bus connectivity will be determined once they
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are connected.
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\section{Setup Register}
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The setup register is perhaps the most critical of all the registers. This
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is shown in Fig.\ref{fig:SETUP}.
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\begin{figure}\begin{center}
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\begin{bytefield}[endianness=big]{32}
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\bitheader{0-31}\\
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\bitbox{2}{00}
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\bitbox{2}{N}
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\bitbox{1}{S}
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\bitbox{1}{P}
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\bitbox{1}{F}
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\bitbox{1}{T}
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\bitbox{24}{Baud CLKS}
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\end{bytefield}
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\caption{SETUP Register fields}\label{fig:SETUP}
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\end{center}\end{figure}
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It is designed so that, for any 8N1 protocol (eight data bits, no parity, one
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stop bit), only the number of clocks per baud interval needs to be set. The
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top two bits are unused, making this a 30--bit number. The other fields
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are: $N$ sets the number of bits per word. A value of zero corresponds
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to 8--bit words, a value of one to seven bit words, and so forth up to a value
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of three for five bit words. $S$ determines the number of stop bits. Set this
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to one for two stop bits, or leave it clear for a single stop bit. $P$
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determines whether or not a parity bit exists (1 for parity, 0 for none),
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while $F$ determines whether or not the parity is fixed. Tbl.~\ref{fig:parity}
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lists out the various values possible here.
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\begin{table}\begin{center}
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\begin{tabular}{ccc|l}
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P&F&T&Setting \\\hline\hline
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1 & 0 & 0 & Odd parity \\\hline
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1 & 0 & 1 & Even parity \\\hline
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1 & 1 & 0 & Parity bit is a Space (1'b0)\\\hline
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1 & 1 & 1 & Parity bit is a Mark (1'b1)\\\hline
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\end{tabular}\caption{Parity setup}\label{tbl:parity}
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\end{center}\end{table}
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\section{RX\_DATA Register}
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Fig.~\ref{fig:RXDATA}
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\begin{figure}\begin{center}
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\begin{bytefield}[endianness=big]{32}
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\bitheader{0-31}\\
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\bitbox{20}{20'h00}
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\bitbox{1}{B}
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\bitbox{1}{F}
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\bitbox{1}{P}
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\bitbox{1}{S}
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\bitbox{8}{RWORD}
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\end{bytefield}
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\caption{RXDATA Register fields}\label{fig:RXDATA}
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\end{center}\end{figure}
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|
breaks out the various bit fields of the receive
|
316 |
|
|
data register used in the {\tt wbuart-insert.v} example of connecting it to
|
317 |
|
|
a bus. In particular, the $B$ field indicates that the receive line is in
|
318 |
|
|
a break condition. The $F$ and $P$ fields indicate that a frame error or
|
319 |
|
|
parity error were detected. These are valid like the data word: when the strobe
|
320 |
|
|
line is set. The $S$ field will be false when the {\tt RWORD} is valid.
|
321 |
|
|
Hence, if {\tt (RWORD \& ~0x0ff)} is zero there is a word ready to be received
|
322 |
|
|
without error.
|
323 |
|
|
|
324 |
|
|
\section{TX\_DATA Register}
|
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|
|
Fig.~\ref{fig:TXDATA}
|
326 |
|
|
\begin{figure}\begin{center}
|
327 |
|
|
\begin{bytefield}[endianness=big]{32}
|
328 |
|
|
\bitheader{0-31}\\
|
329 |
|
|
\bitbox{20}{2'h00}
|
330 |
|
|
\bitbox{1}{C}
|
331 |
|
|
\bitbox{1}{O}
|
332 |
|
|
\bitbox{1}{B}
|
333 |
|
|
\bitbox{1}{S}
|
334 |
|
|
\bitbox{8}{TWORD}
|
335 |
|
|
\end{bytefield}
|
336 |
|
|
\caption{TXDATA Register fields}\label{fig:TXDATA}
|
337 |
|
|
\end{center}\end{figure}
|
338 |
|
|
breaks out the various bit fields of the transmit data register used in
|
339 |
|
|
{\tt wbuart-insert.v}. The $C$ field indicates whether or not the receive
|
340 |
|
|
data line is high or low, the $O$ field indicates the same for the transmit
|
341 |
|
|
line. These aren't particularly useful or valuable, but they don't fit in the
|
342 |
|
|
receive data register since they would violate the error condition detector.
|
343 |
|
|
They're thrown in here for whatever useful purpose one might find. The $B$
|
344 |
|
|
field, when set, sends a break condition down the wire. Writing to the TXDATA
|
345 |
|
|
register, clearing the $B$ field, will clear the transmitter from the break
|
346 |
|
|
condition without transmitting anything. The $S$ field is similar to the RXDATA
|
347 |
|
|
strobe register. It will be true whenever the transmitter is busy or a byte
|
348 |
|
|
is waiting for it. It will be clear only when the transmitter is idle.
|
349 |
|
|
|
350 |
|
|
To use the transmitter, simply write a byte to the TXDATA register with the
|
351 |
|
|
upper 24--bits clear to transmit.
|
352 |
|
|
|
353 |
|
|
\chapter{Clocks}\label{ch:clocks}
|
354 |
|
|
The UART has been tested with a clock as fast as 200~MHz
|
355 |
|
|
(Tbl.~\ref{tbl:clocks}).
|
356 |
|
|
\begin{table}\begin{center}
|
357 |
|
|
\begin{clocklist}
|
358 |
|
|
{\tt i\_clk} & (System) & 200~MHz & & System clock\\\hline
|
359 |
|
|
\end{clocklist}
|
360 |
|
|
\caption{Clock Requirements}\label{tbl:clocks}
|
361 |
|
|
\end{center}\end{table}
|
362 |
|
|
It should be able to use slower clocks, but only subject to the ability to
|
363 |
|
|
properly set the baud rate as shown in Eqn.~\eqref{eqn:baudlimit} on
|
364 |
|
|
Page~\pageref{eqn:baudlimit}.
|
365 |
|
|
|
366 |
|
|
I do not recommend using this core with a baud rate greater than a quarter
|
367 |
|
|
of the system clock rate.
|
368 |
|
|
|
369 |
|
|
% This section specifies all of the clocks. All clocks, clock domain passes
|
370 |
|
|
% and the clock relations should be described.
|
371 |
|
|
|
372 |
|
|
% Name | Source | Rates (MHz) | Remarks | Description
|
373 |
|
|
% | Max|Min|Resolution|
|
374 |
|
|
\chapter{Wishbone Datasheet}\label{ch:wishbone}
|
375 |
|
|
|
376 |
|
|
Tbl.~\ref{tbl:wishbone}
|
377 |
|
|
\begin{table}[htbp]
|
378 |
|
|
\begin{center}
|
379 |
|
|
\begin{wishboneds}
|
380 |
|
|
Revision level of wishbone & WB B4 spec \\\hline
|
381 |
|
|
Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
|
382 |
|
|
Port size & 32--bit \\\hline
|
383 |
|
|
Port granularity & 32--bit \\\hline
|
384 |
|
|
Maximum Operand Size & 32--bit \\\hline
|
385 |
|
|
Data transfer ordering & (Irrelevant) \\\hline
|
386 |
|
|
Clock constraints & None.\\\hline
|
387 |
|
|
Signal Names & \begin{tabular}{ll}
|
388 |
|
|
Signal Name & Wishbone Equivalent \\\hline
|
389 |
|
|
{\tt i\_wb\_clk} & {\tt CLK\_I} \\
|
390 |
|
|
{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
|
391 |
|
|
{\tt i\_wb\_stb} & {\tt STB\_I} \\
|
392 |
|
|
{\tt i\_wb\_we} & {\tt WE\_I} \\
|
393 |
|
|
{\tt i\_wb\_addr} & {\tt ADR\_I} \\
|
394 |
|
|
{\tt i\_wb\_data} & {\tt DAT\_I} \\
|
395 |
|
|
{\tt o\_wb\_ack} & {\tt ACK\_O} \\
|
396 |
|
|
{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
397 |
|
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
398 |
|
|
\end{tabular}\\\hline
|
399 |
|
|
\end{wishboneds}
|
400 |
|
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
401 |
|
|
\end{center}\end{table}
|
402 |
|
|
is required by the wishbone specification in order to declare the core as
|
403 |
|
|
wishbone compliant, and so it is included here. It references the connections
|
404 |
|
|
exemplified by {\tt wbuart-insert.v}. The big thing to notice is that this core
|
405 |
|
|
acts as a wishbone slave, and that all accesses to the core
|
406 |
|
|
registers are 32--bit reads and writes to this interface.
|
407 |
|
|
|
408 |
|
|
What this table doesn't show is that all accesses to the port take a single
|
409 |
|
|
clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the
|
410 |
|
|
{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall}
|
411 |
|
|
line is tied to zero.
|
412 |
|
|
|
413 |
|
|
Also, this particular wishbone implementation assumes that if {\tt i\_wb\_stb},
|
414 |
|
|
then {\tt i\_wb\_cyc} will be high as well. Hence it only checks whether or not
|
415 |
|
|
{\tt i\_wb\_stb} is true to determine if a transaction has taken place. If your
|
416 |
|
|
bus does not meet this requirement, you'll need to AND {\tt i\_wb\_stb} with
|
417 |
|
|
{\tt i\_wb\_cyc} before using the core.
|
418 |
|
|
|
419 |
|
|
\chapter{I/O Ports}\label{ch:ioports}
|
420 |
|
|
% This section specifies all of the core IO ports
|
421 |
|
|
|
422 |
|
|
In it's simplest form, the UART offers simply two I/O ports: the {\tt i\_rx}
|
423 |
|
|
line to receive, and the {\tt o\_tx} line to transmit. These lines need to be
|
424 |
|
|
brought to the outside of your design. Within verilator, they need to be
|
425 |
|
|
connected inside your verilator test bench, as in:
|
426 |
|
|
\begin{tabbing}
|
427 |
|
|
{\tt if (!clk)} \= \\
|
428 |
|
|
\> {\tt tb->i\_rx} {\tt = } {\tt uartsim(tb->o\_uart, setup);}
|
429 |
|
|
\end{tabbing}
|
430 |
|
|
|
431 |
|
|
A more detailed discussion of the connections associated with these modules
|
432 |
|
|
can begin with Tbl.~\ref{tbl:rxports}, detailing the I/O ports of the
|
433 |
|
|
UART receiver, and Tbl.~\ref{tbl:txports},
|
434 |
|
|
\begin{table}\begin{center}\begin{portlist}
|
435 |
|
|
{\tt i\_clk} & 1 & Input & The system clock \\\hline
|
436 |
|
|
{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline
|
437 |
|
|
{\tt i\_setup} & 30 & Input & The 30--bit setup register \\\hline
|
438 |
|
|
{\tt i\_uart} & 1 & Input & The input wire from the outside world. \\\hline
|
439 |
|
|
{\tt o\_wr} & 1 & Output & True if a word was received. At this time,
|
440 |
|
|
{\tt o\_data}, {\tt o\_break}, {\tt o\_parity\_err}, and
|
441 |
|
|
{\tt o\_frame\_err} will also be valid. \\\hline
|
442 |
|
|
{\tt o\_data} & 8 & Output & The received data, valid if {\tt o\_wr} \\\hline
|
443 |
|
|
{\tt o\_break} & 1 & Output & True in the case of a break condition \\\hline
|
444 |
|
|
{\tt o\_parity\_err} & 1 & Output & True if a parity error was detected \\\hline
|
445 |
|
|
{\tt o\_frame\_err} & 1 & Output & True if a frame error was detected \\\hline
|
446 |
|
|
{\tt o\_ck\_uart} & 1 & Output & A synchronized copy of {\tt i\_uart} \\\hline
|
447 |
|
|
\end{portlist}\caption{RXUART port list}\label{tbl:rxports}
|
448 |
|
|
\end{center}\end{table}
|
449 |
|
|
detailing the I/O ports of the UART transmitter.
|
450 |
|
|
\begin{table}\begin{center}\begin{portlist}
|
451 |
|
|
{\tt i\_clk} & 1 & Input & The system clock \\\hline
|
452 |
|
|
{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline
|
453 |
|
|
{\tt i\_setup} & 30 & Input & The 30--bit setup register \\\hline
|
454 |
|
|
{\tt i\_break} & 1 & Input & Set to true to place the transmit channel into a break condition\\\hline
|
455 |
|
|
{\tt i\_wr} & 1 & Input & An input strobe. Set to one when you wish to transmit data, clear once it has been accepted\\\hline
|
456 |
|
|
{\tt i\_data} & 8 & Input & The data to be transmitted, ignored unless
|
457 |
|
|
{\tt (i\_wr)\&\&(!o\_busy)} \\\hline
|
458 |
|
|
{\tt o\_uart} & 1 & Output & The wire to be connected to the external port\\\hline
|
459 |
|
|
{\tt o\_busy} & 1 & Output & True if the transmitter is busy, false if it will receive data\\\hline
|
460 |
|
|
\end{portlist}\caption{TXUART port list}\label{tbl:txports}
|
461 |
|
|
\end{center}\end{table}
|
462 |
|
|
|
463 |
|
|
The ``ports'' associated with the {\tt wbuart-insert.v} example may be
|
464 |
|
|
inferred from the wishbone data sheet.
|
465 |
|
|
|
466 |
|
|
% Appendices
|
467 |
|
|
% A. May be added to outline different specifications. (??)
|
468 |
|
|
|
469 |
|
|
|
470 |
|
|
% Index
|
471 |
|
|
\end{document}
|
472 |
|
|
|
473 |
|
|
|