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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: rxuartlite.v
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//
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// Project: wbuart32, a full featured UART with simulator
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//
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// Purpose: Receive and decode inputs from a single UART line.
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//
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//
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// To interface with this module, connect it to your system clock,
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// and a UART input. Set the parameter to the number of clocks per
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// baud. When data becomes available, the o_wr line will be asserted
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// for one clock cycle.
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//
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// This interface only handles 8N1 serial port communications. It does
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// not handle the break, parity, or frame error conditions.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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dgisselq |
`default_nettype none
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//
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`define RXUL_BIT_ZERO 4'h0
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`define RXUL_BIT_ONE 4'h1
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`define RXUL_BIT_TWO 4'h2
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`define RXUL_BIT_THREE 4'h3
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`define RXUL_BIT_FOUR 4'h4
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`define RXUL_BIT_FIVE 4'h5
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`define RXUL_BIT_SIX 4'h6
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`define RXUL_BIT_SEVEN 4'h7
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`define RXUL_STOP 4'h8
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`define RXUL_IDLE 4'hf
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dgisselq |
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module rxuartlite(i_clk, i_uart_rx, o_wr, o_data);
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parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
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dgisselq |
input wire i_clk;
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input wire i_uart_rx;
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dgisselq |
output reg o_wr;
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output reg [7:0] o_data;
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wire [23:0] half_baud;
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dgisselq |
reg [3:0] state;
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assign half_baud = { 1'b0, CLOCKS_PER_BAUD[23:1] } - 24'h1;
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reg [23:0] baud_counter;
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reg zero_baud_counter;
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// Since this is an asynchronous receiver, we need to register our
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// input a couple of clocks over to avoid any problems with
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// metastability. We do that here, and then ignore all but the
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// ck_uart wire.
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reg q_uart, qq_uart, ck_uart;
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initial q_uart = 1'b0;
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initial qq_uart = 1'b0;
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initial ck_uart = 1'b0;
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always @(posedge i_clk)
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begin
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q_uart <= i_uart_rx;
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qq_uart <= q_uart;
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ck_uart <= qq_uart;
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end
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// Keep track of the number of clocks since the last change.
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//
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// This is used to determine if we are in either a break or an idle
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// condition, as discussed further below.
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reg [23:0] chg_counter;
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initial chg_counter = 24'h00;
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always @(posedge i_clk)
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if (qq_uart != ck_uart)
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chg_counter <= 24'h00;
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else
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chg_counter <= chg_counter + 1;
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// Are we in the middle of a baud iterval? Specifically, are we
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// in the middle of a start bit? Set this to high if so. We'll use
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// this within our state machine to transition out of the IDLE
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// state.
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reg half_baud_time;
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initial half_baud_time = 0;
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always @(posedge i_clk)
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half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
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initial state = `RXUL_IDLE;
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dgisselq |
always @(posedge i_clk)
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begin
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if (state == `RXUL_IDLE)
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begin // Idle state, independent of baud counter
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// By default, just stay in the IDLE state
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state <= `RXUL_IDLE;
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if ((~ck_uart)&&(half_baud_time))
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// UNLESS: We are in the center of a valid
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// start bit
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state <= `RXUL_BIT_ZERO;
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end else if (zero_baud_counter)
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begin
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if (state < `RXUL_STOP)
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// Data arrives least significant bit first.
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// By the time this is clocked in, it's what
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// you'll have.
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state <= state + 1;
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else // Wait for the next character
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state <= `RXUL_IDLE;
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end
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end
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// Data bit capture logic.
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//
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// This is drastically simplified from the state machine above, based
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// upon: 1) it doesn't matter what it is until the end of a captured
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// byte, and 2) the data register will flush itself of any invalid
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// data in all other cases. Hence, let's keep it real simple.
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reg [7:0] data_reg;
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always @(posedge i_clk)
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if (zero_baud_counter)
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data_reg <= { ck_uart, data_reg[7:1] };
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// Our data bit logic doesn't need nearly the complexity of all that
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// work above. Indeed, we only need to know if we are at the end of
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// a stop bit, in which case we copy the data_reg into our output
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// data register, o_data, and tell others (for one clock) that data is
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// available.
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//
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initial o_data = 8'h00;
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always @(posedge i_clk)
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if ((zero_baud_counter)&&(state == `RXUL_STOP))
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begin
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o_wr <= 1'b1;
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o_data <= data_reg;
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end else
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o_wr <= 1'b0;
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// The baud counter
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//
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// This is used as a "clock divider" if you will, but the clock needs
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// to be reset before any byte can be decoded. In all other respects,
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// we set ourselves up for CLOCKS_PER_BAUD counts between baud
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// intervals.
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always @(posedge i_clk)
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if ((zero_baud_counter)|||(state == `RXUL_IDLE))
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baud_counter <= CLOCKS_PER_BAUD-1'b1;
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else
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baud_counter <= baud_counter-1'b1;
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// zero_baud_counter
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//
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// Rather than testing whether or not (baud_counter == 0) within our
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// (already too complicated) state transition tables, we use
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// zero_baud_counter to pre-charge that test on the clock
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// before--cleaning up some otherwise difficult timing dependencies.
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initial zero_baud_counter = 1'b0;
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always @(posedge i_clk)
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if (state == `RXUL_IDLE)
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zero_baud_counter <= 1'b0;
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else
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zero_baud_counter <= (baud_counter == 24'h01);
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endmodule
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