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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_cs_rf.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller Chip Select Register File       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_cs_rf.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
//  $Date: 2002/01/21 13:08:52 $
//  $Revision: 1.6 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: mc_cs_rf.v,v $
//               Revision 1.6  2002/01/21 13:08:52  rudi
//
//               Fixed several minor bugs, cleaned up the code further ...
//
//               Revision 1.5  2001/12/11 02:47:19  rudi
//
//               - Made some changes not to expect clock during reset ...
//
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/24 00:38:21  rudi
//
//               Changed Reset to be active high and async.
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//               Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:42  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_cs_rf(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
                wp_err, lmr_req, lmr_ack, init_req, init_ack );
 
input           clk, rst;
input           wb_we_i;
input   [31:0]   din;
input           rf_we;
input   [31:0]   addr;
 
output  [31:0]   csc;
output  [31:0]   tms;
input   [31:0]   poc;
input   [31:0]   csc_mask;
output          cs;
output          wp_err;
 
output          lmr_req;
input           lmr_ack;
output          init_req;
input           init_ack;
 
parameter       [2:0]    this_cs = 0;
parameter       [3:0]    reg_select = this_cs + 2;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
 
reg     [31:0]   csc;
reg     [31:0]   tms;
wire            sel;
wire            cs_d;
wire            wp;
reg             inited;
reg             init_req;
reg             init_req_we;
reg             lmr_req;
reg             lmr_req_we;
 
////////////////////////////////////////////////////////////////////
//
// A kludge for cases where there is no clock during reset ...
//
 
reg     rst_r1, rst_r2;
 
always @(posedge clk or posedge rst)
        if(rst)         rst_r1 <= #1 1'b1;
        else            rst_r1 <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)         rst_r2 <= #1 1'b1;
        else            rst_r2 <= #1 rst_r1;
 
////////////////////////////////////////////////////////////////////
//
// Write Logic
//
 
reg     [6:0]    addr_r;
 
always @(posedge clk)
        addr_r <= #1 addr[6:0];
 
assign sel = addr_r[6:3] == reg_select[3:0];
 
always @(posedge clk)
        if(rst_r2)                      csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
                                        {26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;
        else
        if(rf_we & sel & !addr_r[2])    csc <= #1 din;
 
always @(posedge clk)
        if(rst_r2)                      tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
                                                `MC_DEF_POR_TMS : 32'h0;
        else
        if(rf_we & sel & addr_r[2])     tms <= #1 din;
 
////////////////////////////////////////////////////////////////////
//
// Load Mode Register Request/Ack Logic
//
always @(posedge clk or posedge rst)
        if(rst)         lmr_req_we <= #1 1'b0;
        else            lmr_req_we <= #1 rf_we & sel & addr_r[2];
 
always @(posedge clk or posedge rst)
        if(rst)         lmr_req <= #1 1'b0;
        else
        if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))
                        lmr_req <= #1 inited;
        else
        if(lmr_ack)     lmr_req <= #1 1'b0;
 
////////////////////////////////////////////////////////////////////
//
// Initialize SDRAM Request/Ack & tracking logic
//
always @(posedge clk or posedge rst)
        if(rst) init_req_we <= #1 1'b0;
        else    init_req_we <= #1 rf_we & sel & !addr_r[2];
 
always @(posedge clk or posedge rst)
        if(rst)         init_req <= #1 1'b0;
        else
        if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)
                        init_req <= #1 1'b1;
        else
        if(init_ack)    init_req <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)         inited <= #1 1'b0;
        else
        if(init_ack)    inited <= #1 1'b1;
 
////////////////////////////////////////////////////////////////////
//
// Chip Select Generation Logic
//
 
assign cs_d = ((csc[23:16] & csc_mask[7:0]) == (addr[28:21] & csc_mask[7:0])) & csc[0];
 
assign wp = wb_we_i & csc[8];
 
assign wp_err = cs_d &  wp;
assign cs     = cs_d & !wp;
 
endmodule
 
 
 
// This dummy is used to terminate the outputs for non existing Chip Selects
module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
                wp_err, lmr_req, lmr_ack, init_req, init_ack );
 
parameter       [2:0]    this_cs = 0;
 
input           clk, rst;
input           wb_we_i;
input   [31:0]   din;
input           rf_we;
input   [31:0]   addr;
 
output  [31:0]   csc;
output  [31:0]   tms;
input   [31:0]   poc;
input   [31:0]   csc_mask;
output          cs;
output          wp_err;
 
output          lmr_req;
input           lmr_ack;
output          init_req;
input           init_ack;
 
assign csc = 32'h0;
assign tms = 32'h0;
assign cs = 1'b0;
assign wp_err = 1'b0;
assign lmr_req = 1'b0;
assign init_req = 1'b0;
 
endmodule

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_cs_rf.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller Chip Select Register File ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: mc_cs_rf.v,v 1.6 2002/01/21 13:08:52 rudi Exp $`
42			`//`
43			`// $Date: 2002/01/21 13:08:52 $`
44			`// $Revision: 1.6 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: mc_cs_rf.v,v $`
51			`// Revision 1.6 2002/01/21 13:08:52 rudi`
52			`//`
53			`// Fixed several minor bugs, cleaned up the code further ...`
54			`//`
55			`// Revision 1.5 2001/12/11 02:47:19 rudi`
56			`//`
57			`// - Made some changes not to expect clock during reset ...`
58			`//`
59			`// Revision 1.4 2001/11/29 02:16:28 rudi`
60			`//`
61			`//`
62			`// - More Synthesis cleanup, mostly for speed`
63			`// - Several bug fixes`
64			`// - Changed code to avoid auto-precharge and`
65			`// burst-terminate combinations (apparently illegal ?)`
66			`// Now we will do a manual precharge ...`
67			`//`
68			`// Revision 1.3 2001/09/24 00:38:21 rudi`
69			`//`
70			`// Changed Reset to be active high and async.`
71			`//`
72			`// Revision 1.2 2001/08/10 08:16:21 rudi`
73			`//`
74			`// - Changed IO names to be more clear.`
75			`// - Uniquifyed define names to be core specific.`
76			`// - Removed "Refresh Early" configuration`
77			`//`
78			`// Revision 1.1 2001/07/29 07:34:41 rudi`
79			`//`
80			`//`
81			`// 1) Changed Directory Structure`
82			`// 2) Fixed several minor bugs`
83			`//`
84			`// Revision 1.3 2001/06/12 15:19:49 rudi`
85			`//`
86			`//`
87			`// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.`
88			`//`
89			`// Revision 1.2 2001/06/03 11:37:17 rudi`
90			`//`
91			`//`
92			`// 1) Fixed Chip Select Mask Register`
93			`// - Power On Value is now all ones`
94			`// - Comparison Logic is now correct`
95			`//`
96			`// 2) All resets are now asynchronous`
97			`//`
98			`// 3) Converted Power On Delay to an configurable item`
99			`//`
100			`// 4) Added reset to Chip Select Output Registers`
101			`//`
102			`// 5) Forcing all outputs to Hi-Z state during reset`
103			`//`
104			`// Revision 1.1.1.1 2001/05/13 09:39:42 rudi`
105			`// Created Directory Structure`
106			`//`
107			`//`
108			`//`
109			`//`
110
111			`include "mc_defines.v"
112
113			`module mc_cs_rf(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,`
114			`wp_err, lmr_req, lmr_ack, init_req, init_ack );`
115
116			`input clk, rst;`
117			`input wb_we_i;`
118			`input [31:0] din;`
119			`input rf_we;`
120			`input [31:0] addr;`
121
122			`output [31:0] csc;`
123			`output [31:0] tms;`
124			`input [31:0] poc;`
125			`input [31:0] csc_mask;`
126			`output cs;`
127			`output wp_err;`
128
129			`output lmr_req;`
130			`input lmr_ack;`
131			`output init_req;`
132			`input init_ack;`
133
134			`parameter [2:0] this_cs = 0;`
135			`parameter [3:0] reg_select = this_cs + 2;`
136
137			`////////////////////////////////////////////////////////////////////`
138			`//`
139			`// Local Registers and Wires`
140			`//`
141
142			`reg [31:0] csc;`
143			`reg [31:0] tms;`
144			`wire sel;`
145			`wire cs_d;`
146			`wire wp;`
147			`reg inited;`
148			`reg init_req;`
149			`reg init_req_we;`
150			`reg lmr_req;`
151			`reg lmr_req_we;`
152
153			`////////////////////////////////////////////////////////////////////`
154			`//`
155			`// A kludge for cases where there is no clock during reset ...`
156			`//`
157
158			`reg rst_r1, rst_r2;`
159
160			`always @(posedge clk or posedge rst)`
161			`if(rst) rst_r1 <= #1 1'b1;`
162			`else rst_r1 <= #1 1'b0;`
163
164			`always @(posedge clk or posedge rst)`
165			`if(rst) rst_r2 <= #1 1'b1;`
166			`else rst_r2 <= #1 rst_r1;`
167
168			`////////////////////////////////////////////////////////////////////`
169			`//`
170			`// Write Logic`
171			`//`
172
173			`reg [6:0] addr_r;`
174
175			`always @(posedge clk)`
176			`addr_r <= #1 addr[6:0];`
177
178			`assign sel = addr_r[6:3] == reg_select[3:0];`
179
180			`always @(posedge clk)`
181			if(rst_r2) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
182			`{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;`
183			`else`
184			`if(rf_we & sel & !addr_r[2]) csc <= #1 din;`
185
186			`always @(posedge clk)`
187			if(rst_r2) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
188			`MC_DEF_POR_TMS : 32'h0;
189			`else`
190			`if(rf_we & sel & addr_r[2]) tms <= #1 din;`
191
192			`////////////////////////////////////////////////////////////////////`
193			`//`
194			`// Load Mode Register Request/Ack Logic`
195			`//`
196			`always @(posedge clk or posedge rst)`
197			`if(rst) lmr_req_we <= #1 1'b0;`
198			`else lmr_req_we <= #1 rf_we & sel & addr_r[2];`
199
200			`always @(posedge clk or posedge rst)`
201			`if(rst) lmr_req <= #1 1'b0;`
202			`else`
203			if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))
204			`lmr_req <= #1 inited;`
205			`else`
206			`if(lmr_ack) lmr_req <= #1 1'b0;`
207
208			`////////////////////////////////////////////////////////////////////`
209			`//`
210			`// Initialize SDRAM Request/Ack & tracking logic`
211			`//`
212			`always @(posedge clk or posedge rst)`
213			`if(rst) init_req_we <= #1 1'b0;`
214			`else init_req_we <= #1 rf_we & sel & !addr_r[2];`
215
216			`always @(posedge clk or posedge rst)`
217			`if(rst) init_req <= #1 1'b0;`
218			`else`
219			if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)
220			`init_req <= #1 1'b1;`
221			`else`
222			`if(init_ack) init_req <= #1 1'b0;`
223
224			`always @(posedge clk or posedge rst)`
225			`if(rst) inited <= #1 1'b0;`
226			`else`
227			`if(init_ack) inited <= #1 1'b1;`
228
229			`////////////////////////////////////////////////////////////////////`
230			`//`
231			`// Chip Select Generation Logic`
232			`//`
233
234			`assign cs_d = ((csc[23:16] & csc_mask[7:0]) == (addr[28:21] & csc_mask[7:0])) & csc[0];`
235
236			`assign wp = wb_we_i & csc[8];`
237
238			`assign wp_err = cs_d & wp;`
239			`assign cs = cs_d & !wp;`
240
241			`endmodule`
242
243
244
245			`// This dummy is used to terminate the outputs for non existing Chip Selects`
246			`module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,`
247			`wp_err, lmr_req, lmr_ack, init_req, init_ack );`
248
249			`parameter [2:0] this_cs = 0;`
250
251			`input clk, rst;`
252			`input wb_we_i;`
253			`input [31:0] din;`
254			`input rf_we;`
255			`input [31:0] addr;`
256
257			`output [31:0] csc;`
258			`output [31:0] tms;`
259			`input [31:0] poc;`
260			`input [31:0] csc_mask;`
261			`output cs;`
262			`output wp_err;`
263
264			`output lmr_req;`
265			`input lmr_ack;`
266			`output init_req;`
267			`input init_ack;`
268
269			`assign csc = 32'h0;`
270			`assign tms = 32'h0;`
271			`assign cs = 1'b0;`
272			`assign wp_err = 1'b0;`
273			`assign lmr_req = 1'b0;`
274			`assign init_req = 1'b0;`
275
276			`endmodule`