URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_defines.v] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller Definitions                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_defines.v,v 1.7 2002/01/21 13:08:52 rudi Exp $
//
//  $Date: 2002/01/21 13:08:52 $
//  $Revision: 1.7 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: mc_defines.v,v $
//               Revision 1.7  2002/01/21 13:08:52  rudi
//
//               Fixed several minor bugs, cleaned up the code further ...
//
//               Revision 1.6  2001/12/12 06:35:15  rudi
//               *** empty log message ***
//
//               Revision 1.5  2001/12/11 02:47:19  rudi
//
//               - Made some changes not to expect clock during reset ...
//
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/10 13:44:17  rudi
//               *** empty log message ***
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//              Minor changes after running lint, and a small bug
//              fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:38  rudi
//               Created Directory Structure
//
//
//
//
 
`timescale 1ns / 10ps
 
/////////////////////////////////////////////////////////////////////
//
// This define selects how the WISHBONE interface determines if
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_REG_SEL              (wb_addr_i[27] == 1'b1)
 
// This define selects how the WISHBONE interface determines if
// the memory is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_MEM_SEL              (wb_addr_i[27] == 1'b0)
 
/////////////////////////////////////////////////////////////////////
//
// This are the default Power-On Reset values for Chip Select
//
 
// This will be defined by the run script for my test bench ...
// Alternatively force here for synthesis ...
//`define RUDIS_TB 1
 
// Defines which chip select is used for Power On booting
 
// To run my default testbench default boot CS must be 3 !!!
`ifdef RUDIS_TB
`define MC_DEF_SEL              3'h3
`else
`define MC_DEF_SEL              3'h0
`endif
 
// Defines the default (reset) TMS value for the DEF_SEL chip select
`define MC_DEF_POR_TMS  32'hffff_ffff
 
 
/////////////////////////////////////////////////////////////////////
//
// Define how many Chip Selects to Implement
//
//`define MC_HAVE_CS1   1
//`define MC_HAVE_CS2   1
//`define MC_HAVE_CS3   1
//`define MC_HAVE_CS4   1
//`define MC_HAVE_CS5   1
//`define MC_HAVE_CS6   1
//`define MC_HAVE_CS7   1
 
 
// To run my default testbench those need to there !!!
`ifdef RUDIS_TB
`define MC_HAVE_CS2     1
`define MC_HAVE_CS3     1
`define MC_HAVE_CS4     1
`define MC_HAVE_CS5     1
`endif
 
/////////////////////////////////////////////////////////////////////
//
// Init Refresh
//
// Number of Refresh Cycles to perform during SDRAM initialization.
// This varies between SDRAM manufacturer. Typically this value is
// between 2 and 8. This number must be smaller than 16.
`define MC_INIT_RFRC_CNT        8
 
/////////////////////////////////////////////////////////////////////
//
// Power On Delay
//
// Most if SDRAMs require some time to initialize before they can be used
// after power on. If the Memory Controller shall stall after power on to
// allow SDRAMs to finish the initialization process uncomment the below
// define statement
`define MC_POR_DELAY    1
 
// This value defines how many MEM_CLK cycles the Memory Controller should
// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250
// cycles.
`define MC_POR_DELAY_VAL        8'd250
 
 
// ===============================================================
// ===============================================================
// Various internal defines (DO NOT MODIFY !)
// ===============================================================
// ===============================================================
 
// Register settings encodings
`define MC_BW_8                 2'h0
`define MC_BW_16                2'h1
`define MC_BW_32                2'h2
 
`define MC_MEM_TYPE_SDRAM       3'h0
`define MC_MEM_TYPE_SRAM        3'h1
`define MC_MEM_TYPE_ACS         3'h2
`define MC_MEM_TYPE_SCS         3'h3
 
`define MC_MEM_SIZE_64          2'h0
`define MC_MEM_SIZE_128         2'h1
`define MC_MEM_SIZE_256         2'h2
 
// Command Valid, Ras_, Cas_, We_
`define MC_CMD_NOP              4'b0111
`define MC_CMD_PC               4'b1010
`define MC_CMD_ACT              4'b1011
`define MC_CMD_WR               4'b1100
`define MC_CMD_RD               4'b1101
`define MC_CMD_BT               4'b1110
`define MC_CMD_ARFR             4'b1001
`define MC_CMD_LMR              4'b1000
`define MC_CMD_XRD              4'b1111
`define MC_CMD_XWR              4'b1110
 
`define MC_SINGLE_BANK          1'b0
`define MC_ALL_BANKS            1'b1
 
`define MC_BA_MASK_VAL 11'h020
`define MC_POC_VAL     32'h00000002

Browse

Tools

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_defines.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	5	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller Definitions ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: mc_defines.v,v 1.7 2002/01/21 13:08:52 rudi Exp $`
42			`//`
43			`// $Date: 2002/01/21 13:08:52 $`
44			`// $Revision: 1.7 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: mc_defines.v,v $`
51			`// Revision 1.7 2002/01/21 13:08:52 rudi`
52			`//`
53			`// Fixed several minor bugs, cleaned up the code further ...`
54			`//`
55			`// Revision 1.6 2001/12/12 06:35:15 rudi`
56			`// * empty log message *`
57			`//`
58			`// Revision 1.5 2001/12/11 02:47:19 rudi`
59			`//`
60			`// - Made some changes not to expect clock during reset ...`
61			`//`
62			`// Revision 1.4 2001/11/29 02:16:28 rudi`
63			`//`
64			`//`
65			`// - More Synthesis cleanup, mostly for speed`
66			`// - Several bug fixes`
67			`// - Changed code to avoid auto-precharge and`
68			`// burst-terminate combinations (apparently illegal ?)`
69			`// Now we will do a manual precharge ...`
70			`//`
71			`// Revision 1.3 2001/09/10 13:44:17 rudi`
72			`// * empty log message *`
73			`//`
74			`// Revision 1.2 2001/08/10 08:16:21 rudi`
75			`//`
76			`// - Changed IO names to be more clear.`
77			`// - Uniquifyed define names to be core specific.`
78			`// - Removed "Refresh Early" configuration`
79			`//`
80			`// Revision 1.1 2001/07/29 07:34:41 rudi`
81			`//`
82			`//`
83			`// 1) Changed Directory Structure`
84			`// 2) Fixed several minor bugs`
85			`//`
86			`// Revision 1.3 2001/06/12 15:19:49 rudi`
87			`//`
88			`//`
89			`// Minor changes after running lint, and a small bug`
90			`// fix reading csr and ba_mask registers.`
91			`//`
92			`// Revision 1.2 2001/06/03 11:37:17 rudi`
93			`//`
94			`//`
95			`// 1) Fixed Chip Select Mask Register`
96			`// - Power On Value is now all ones`
97			`// - Comparison Logic is now correct`
98			`//`
99			`// 2) All resets are now asynchronous`
100			`//`
101			`// 3) Converted Power On Delay to an configurable item`
102			`//`
103			`// 4) Added reset to Chip Select Output Registers`
104			`//`
105			`// 5) Forcing all outputs to Hi-Z state during reset`
106			`//`
107			`// Revision 1.1.1.1 2001/05/13 09:39:38 rudi`
108			`// Created Directory Structure`
109			`//`
110			`//`
111			`//`
112			`//`
113
114			`timescale 1ns / 10ps
115
116			`/////////////////////////////////////////////////////////////////////`
117			`//`
118			`// This define selects how the WISHBONE interface determines if`
119			`// the internal register file is selected.`
120			`// This should be a simple address decoder. "wb_addr_i" is the`
121			`// WISHBONE address bus (32 bits wide).`
122			`define MC_REG_SEL (wb_addr_i[27] == 1'b1)
123
124			`// This define selects how the WISHBONE interface determines if`
125			`// the memory is selected.`
126			`// This should be a simple address decoder. "wb_addr_i" is the`
127			`// WISHBONE address bus (32 bits wide).`
128			`define MC_MEM_SEL (wb_addr_i[27] == 1'b0)
129
130			`/////////////////////////////////////////////////////////////////////`
131			`//`
132			`// This are the default Power-On Reset values for Chip Select`
133			`//`
134
135			`// This will be defined by the run script for my test bench ...`
136			`// Alternatively force here for synthesis ...`
137			//`define RUDIS_TB 1
138
139			`// Defines which chip select is used for Power On booting`
140
141			`// To run my default testbench default boot CS must be 3 !!!`
142			`ifdef RUDIS_TB
143			`define MC_DEF_SEL 3'h3
144			`else
145			`define MC_DEF_SEL 3'h0
146			`endif
147
148			`// Defines the default (reset) TMS value for the DEF_SEL chip select`
149			`define MC_DEF_POR_TMS 32'hffff_ffff
150
151
152			`/////////////////////////////////////////////////////////////////////`
153			`//`
154			`// Define how many Chip Selects to Implement`
155			`//`
156			//`define MC_HAVE_CS1 1
157			//`define MC_HAVE_CS2 1
158			//`define MC_HAVE_CS3 1
159			//`define MC_HAVE_CS4 1
160			//`define MC_HAVE_CS5 1
161			//`define MC_HAVE_CS6 1
162			//`define MC_HAVE_CS7 1
163
164
165			`// To run my default testbench those need to there !!!`
166			`ifdef RUDIS_TB
167			`define MC_HAVE_CS2 1
168			`define MC_HAVE_CS3 1
169			`define MC_HAVE_CS4 1
170			`define MC_HAVE_CS5 1
171			`endif
172
173			`/////////////////////////////////////////////////////////////////////`
174			`//`
175			`// Init Refresh`
176			`//`
177			`// Number of Refresh Cycles to perform during SDRAM initialization.`
178			`// This varies between SDRAM manufacturer. Typically this value is`
179			`// between 2 and 8. This number must be smaller than 16.`
180			`define MC_INIT_RFRC_CNT 8
181
182			`/////////////////////////////////////////////////////////////////////`
183			`//`
184			`// Power On Delay`
185			`//`
186			`// Most if SDRAMs require some time to initialize before they can be used`
187			`// after power on. If the Memory Controller shall stall after power on to`
188			`// allow SDRAMs to finish the initialization process uncomment the below`
189			`// define statement`
190			`define MC_POR_DELAY 1
191
192			`// This value defines how many MEM_CLK cycles the Memory Controller should`
193			`// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250`
194			`// cycles.`
195			`define MC_POR_DELAY_VAL 8'd250
196
197
198			`// ===============================================================`
199			`// ===============================================================`
200			`// Various internal defines (DO NOT MODIFY !)`
201			`// ===============================================================`
202			`// ===============================================================`
203
204			`// Register settings encodings`
205			`define MC_BW_8 2'h0
206			`define MC_BW_16 2'h1
207			`define MC_BW_32 2'h2
208
209			`define MC_MEM_TYPE_SDRAM 3'h0
210			`define MC_MEM_TYPE_SRAM 3'h1
211			`define MC_MEM_TYPE_ACS 3'h2
212			`define MC_MEM_TYPE_SCS 3'h3
213
214			`define MC_MEM_SIZE_64 2'h0
215			`define MC_MEM_SIZE_128 2'h1
216			`define MC_MEM_SIZE_256 2'h2
217
218			`// Command Valid, Ras_, Cas_, We_`
219			`define MC_CMD_NOP 4'b0111
220			`define MC_CMD_PC 4'b1010
221			`define MC_CMD_ACT 4'b1011
222			`define MC_CMD_WR 4'b1100
223			`define MC_CMD_RD 4'b1101
224			`define MC_CMD_BT 4'b1110
225			`define MC_CMD_ARFR 4'b1001
226			`define MC_CMD_LMR 4'b1000
227			`define MC_CMD_XRD 4'b1111
228			`define MC_CMD_XWR 4'b1110
229
230			`define MC_SINGLE_BANK 1'b0
231			`define MC_ALL_BANKS 1'b1
232
233			`define MC_BA_MASK_VAL 11'h020
234			`define MC_POC_VAL 32'h00000002