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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_mem_if.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Memory Bus Interface                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_mem_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
//  $Date: 2002/01/21 13:08:52 $
//  $Revision: 1.6 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: mc_mem_if.v,v $
//               Revision 1.6  2002/01/21 13:08:52  rudi
//
//               Fixed several minor bugs, cleaned up the code further ...
//
//               Revision 1.5  2001/12/21 05:09:29  rudi
//
//               - Fixed combinatorial loops in synthesis
//               - Fixed byte select bug
//
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/24 00:38:21  rudi
//
//               Changed Reset to be active high and async.
//
//               Revision 1.2  2001/09/02 02:28:28  rudi
//
//               Many fixes for minor bugs that showed up in gate level simulations.
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/14 01:57:37  rudi
//
//
//               Fixed a potential bug in a corner case situation where the TMS register
//               does not propegate properly during initialisation.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:48  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,
                mc_addr, mc_data_o, mc_dp_o, mc_data_oe,
                mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,
                mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d,
                mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r,
                we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack,
                cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel,
                suspended_o, oe_, wb_cyc_i, wb_stb_i, wb_sel_i, wb_cycle,
                wr_cycle, mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i,
                mc_zz_o
                );
// Memory Interface
input           clk;
input           rst;
input           mc_clk;
input           mc_br;
output          mc_bg;
output  [23:0]   mc_addr;
output  [31:0]   mc_data_o;
output  [3:0]    mc_dp_o;
output          mc_data_oe;
output  [3:0]    mc_dqm;
output          mc_oe_;
output          mc_we_;
output          mc_cas_;
output          mc_ras_;
output          mc_cke_;
output  [7:0]    mc_cs_;
output          mc_adsc_;
output          mc_adv_;
input           mc_ack;
output          mc_rp;
output          mc_c_oe;
output  [35:0]   mc_data_ir;
output          mc_sts_ir;
output          mc_zz_o;
 
// Internal Interface
output          mc_br_r;
input           mc_bg_d;
input           data_oe;
input           susp_sel;
input           suspended_o;
input   [31:0]   mc_data_od;
input   [3:0]    mc_dp_od;
input   [23:0]   mc_addr_d;
output          mc_ack_r;
input           wb_cyc_i;
input           wb_stb_i;
input   [3:0]    wb_sel_i;
input           wb_cycle;
input           wr_cycle;
input           oe_ ;
input           we_;
input           ras_;
input           cas_;
input           cke_;
input           cs_en;
input           rfr_ack;
input   [7:0]    cs_need_rfr;
input           lmr_sel;
input   [7:0]    spec_req_cs;
input   [7:0]    cs;
input           fs;
input           mc_adsc_d;
input           mc_adv_d;
input           mc_c_oe_d;
input   [31:0]   mc_data_i;
input   [3:0]    mc_dp_i;
input           mc_sts_i;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg             mc_data_oe;
reg     [31:0]   mc_data_o;
reg     [3:0]    mc_dp_o;
reg     [3:0]    mc_dqm;
reg     [3:0]    mc_dqm_r;
reg     [23:0]   mc_addr;
reg             mc_oe_;
reg             mc_we_;
reg             mc_cas_;
reg             mc_ras_;
wire            mc_cke_;
reg     [7:0]    mc_cs_;
reg             mc_bg;
reg             mc_adsc_;
reg             mc_adv_;
reg             mc_br_r;
reg             mc_ack_r;
reg             mc_rp;
reg             mc_c_oe;
reg             mc_zz_o;
 
reg     [35:0]   mc_data_ir;
reg             mc_sts_ir;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge mc_clk)
        mc_zz_o <= #1 suspended_o;
 
always @(posedge mc_clk)
        mc_sts_ir <= #1 mc_sts_i;
 
always @(posedge mc_clk)
        mc_data_ir <= #1 {mc_dp_i, mc_data_i};
 
always @(posedge mc_clk)
        mc_c_oe <= #1 mc_c_oe_d;
 
always @(posedge mc_clk)
        mc_rp <= #1 !suspended_o & !fs;
 
always @(posedge mc_clk)
        mc_br_r <= #1 mc_br;
 
always @(posedge mc_clk)
        mc_ack_r <= #1 mc_ack;
 
always @(posedge mc_clk)
        mc_bg <= #1 mc_bg_d;
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_data_oe <= #1 1'b0;
        else            mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d;
 
always @(posedge mc_clk)
        mc_data_o <= #1 mc_data_od;
 
always @(posedge mc_clk)
        mc_dp_o <= #1 mc_dp_od;
 
always @(posedge mc_clk)
        mc_addr <= #1 mc_addr_d;
 
always @(posedge clk)
        if(wb_cyc_i & wb_stb_i)
                mc_dqm_r <= #1 wb_sel_i;
 
reg     [3:0]    mc_dqm_r2;
always @(posedge clk)
                mc_dqm_r2 <= #1 mc_dqm_r;
 
always @(posedge mc_clk)
        mc_dqm <= #1    susp_sel ? 4'hf :
                        data_oe ? ~mc_dqm_r2 :
                        (wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_oe_ <= #1 1'b1;
        else            mc_oe_ <= #1 oe_ | susp_sel;
 
always @(posedge mc_clk)
        mc_we_ <= #1 we_;
 
always @(posedge mc_clk)
        mc_cas_ <= #1 cas_;
 
always @(posedge mc_clk)
        mc_ras_ <= #1 ras_;
 
assign  mc_cke_ = cke_;
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[0] <= #1 1'b1;
        else
        mc_cs_[0] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[0] :
                                lmr_sel ? spec_req_cs[0] :
                                cs[0]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[1] <= #1 1'b1;
        else
           mc_cs_[1] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[1] :
                                lmr_sel ? spec_req_cs[1] :
                                cs[1]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[2] <= #1 1'b1;
        else
           mc_cs_[2] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[2] :
                                lmr_sel ? spec_req_cs[2] :
                                cs[2]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[3] <= #1 1'b1;
        else
           mc_cs_[3] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[3] :
                                lmr_sel ? spec_req_cs[3] :
                                cs[3]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[4] <= #1 1'b1;
        else
           mc_cs_[4] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[4] :
                                lmr_sel ? spec_req_cs[4] :
                                cs[4]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[5] <= #1 1'b1;
        else
           mc_cs_[5] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[5] :
                                lmr_sel ? spec_req_cs[5] :
                                cs[5]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[6] <= #1 1'b1;
        else
           mc_cs_[6] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[6] :
                                lmr_sel ? spec_req_cs[6] :
                                cs[6]
                        ));
 
always @(posedge mc_clk or posedge rst)
        if(rst)         mc_cs_[7] <= #1 1'b1;
        else
           mc_cs_[7] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[7] :
                                lmr_sel ? spec_req_cs[7] :
                                cs[7]
                        ));
 
always @(posedge mc_clk)
        mc_adsc_ <= #1 ~mc_adsc_d;
 
always @(posedge mc_clk)
        mc_adv_  <= #1 ~mc_adv_d;
 
endmodule

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_mem_if.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Memory Bus Interface ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42			`// $Id: mc_mem_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $`
43			`//`
44			`// $Date: 2002/01/21 13:08:52 $`
45			`// $Revision: 1.6 $`
46			`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: mc_mem_if.v,v $`
52			`// Revision 1.6 2002/01/21 13:08:52 rudi`
53			`//`
54			`// Fixed several minor bugs, cleaned up the code further ...`
55			`//`
56			`// Revision 1.5 2001/12/21 05:09:29 rudi`
57			`//`
58			`// - Fixed combinatorial loops in synthesis`
59			`// - Fixed byte select bug`
60			`//`
61			`// Revision 1.4 2001/11/29 02:16:28 rudi`
62			`//`
63			`//`
64			`// - More Synthesis cleanup, mostly for speed`
65			`// - Several bug fixes`
66			`// - Changed code to avoid auto-precharge and`
67			`// burst-terminate combinations (apparently illegal ?)`
68			`// Now we will do a manual precharge ...`
69			`//`
70			`// Revision 1.3 2001/09/24 00:38:21 rudi`
71			`//`
72			`// Changed Reset to be active high and async.`
73			`//`
74			`// Revision 1.2 2001/09/02 02:28:28 rudi`
75			`//`
76			`// Many fixes for minor bugs that showed up in gate level simulations.`
77			`//`
78			`// Revision 1.1 2001/07/29 07:34:41 rudi`
79			`//`
80			`//`
81			`// 1) Changed Directory Structure`
82			`// 2) Fixed several minor bugs`
83			`//`
84			`// Revision 1.3 2001/06/14 01:57:37 rudi`
85			`//`
86			`//`
87			`// Fixed a potential bug in a corner case situation where the TMS register`
88			`// does not propegate properly during initialisation.`
89			`//`
90			`// Revision 1.2 2001/06/03 11:37:17 rudi`
91			`//`
92			`//`
93			`// 1) Fixed Chip Select Mask Register`
94			`// - Power On Value is now all ones`
95			`// - Comparison Logic is now correct`
96			`//`
97			`// 2) All resets are now asynchronous`
98			`//`
99			`// 3) Converted Power On Delay to an configurable item`
100			`//`
101			`// 4) Added reset to Chip Select Output Registers`
102			`//`
103			`// 5) Forcing all outputs to Hi-Z state during reset`
104			`//`
105			`// Revision 1.1.1.1 2001/05/13 09:39:48 rudi`
106			`// Created Directory Structure`
107			`//`
108			`//`
109			`//`
110			`//`
111
112			`include "mc_defines.v"
113
114			`module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,`
115			`mc_addr, mc_data_o, mc_dp_o, mc_data_oe,`
116			`mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,`
117			`mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d,`
118			`mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r,`
119			`we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack,`
120			`cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel,`
121			`suspended_o, oe_, wb_cyc_i, wb_stb_i, wb_sel_i, wb_cycle,`
122			`wr_cycle, mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i,`
123			`mc_zz_o`
124			`);`
125			`// Memory Interface`
126			`input clk;`
127			`input rst;`
128			`input mc_clk;`
129			`input mc_br;`
130			`output mc_bg;`
131			`output [23:0] mc_addr;`
132			`output [31:0] mc_data_o;`
133			`output [3:0] mc_dp_o;`
134			`output mc_data_oe;`
135			`output [3:0] mc_dqm;`
136			`output mc_oe_;`
137			`output mc_we_;`
138			`output mc_cas_;`
139			`output mc_ras_;`
140			`output mc_cke_;`
141			`output [7:0] mc_cs_;`
142			`output mc_adsc_;`
143			`output mc_adv_;`
144			`input mc_ack;`
145			`output mc_rp;`
146			`output mc_c_oe;`
147			`output [35:0] mc_data_ir;`
148			`output mc_sts_ir;`
149			`output mc_zz_o;`
150
151			`// Internal Interface`
152			`output mc_br_r;`
153			`input mc_bg_d;`
154			`input data_oe;`
155			`input susp_sel;`
156			`input suspended_o;`
157			`input [31:0] mc_data_od;`
158			`input [3:0] mc_dp_od;`
159			`input [23:0] mc_addr_d;`
160			`output mc_ack_r;`
161			`input wb_cyc_i;`
162			`input wb_stb_i;`
163			`input [3:0] wb_sel_i;`
164			`input wb_cycle;`
165			`input wr_cycle;`
166			`input oe_ ;`
167			`input we_;`
168			`input ras_;`
169			`input cas_;`
170			`input cke_;`
171			`input cs_en;`
172			`input rfr_ack;`
173			`input [7:0] cs_need_rfr;`
174			`input lmr_sel;`
175			`input [7:0] spec_req_cs;`
176			`input [7:0] cs;`
177			`input fs;`
178			`input mc_adsc_d;`
179			`input mc_adv_d;`
180			`input mc_c_oe_d;`
181			`input [31:0] mc_data_i;`
182			`input [3:0] mc_dp_i;`
183			`input mc_sts_i;`
184
185			`////////////////////////////////////////////////////////////////////`
186			`//`
187			`// Local Wires`
188			`//`
189
190			`reg mc_data_oe;`
191			`reg [31:0] mc_data_o;`
192			`reg [3:0] mc_dp_o;`
193			`reg [3:0] mc_dqm;`
194			`reg [3:0] mc_dqm_r;`
195			`reg [23:0] mc_addr;`
196			`reg mc_oe_;`
197			`reg mc_we_;`
198			`reg mc_cas_;`
199			`reg mc_ras_;`
200			`wire mc_cke_;`
201			`reg [7:0] mc_cs_;`
202			`reg mc_bg;`
203			`reg mc_adsc_;`
204			`reg mc_adv_;`
205			`reg mc_br_r;`
206			`reg mc_ack_r;`
207			`reg mc_rp;`
208			`reg mc_c_oe;`
209			`reg mc_zz_o;`
210
211			`reg [35:0] mc_data_ir;`
212			`reg mc_sts_ir;`
213
214			`////////////////////////////////////////////////////////////////////`
215			`//`
216			`// Misc Logic`
217			`//`
218
219			`always @(posedge mc_clk)`
220			`mc_zz_o <= #1 suspended_o;`
221
222			`always @(posedge mc_clk)`
223			`mc_sts_ir <= #1 mc_sts_i;`
224
225			`always @(posedge mc_clk)`
226			`mc_data_ir <= #1 {mc_dp_i, mc_data_i};`
227
228			`always @(posedge mc_clk)`
229			`mc_c_oe <= #1 mc_c_oe_d;`
230
231			`always @(posedge mc_clk)`
232			`mc_rp <= #1 !suspended_o & !fs;`
233
234			`always @(posedge mc_clk)`
235			`mc_br_r <= #1 mc_br;`
236
237			`always @(posedge mc_clk)`
238			`mc_ack_r <= #1 mc_ack;`
239
240			`always @(posedge mc_clk)`
241			`mc_bg <= #1 mc_bg_d;`
242
243			`always @(posedge mc_clk or posedge rst)`
244			`if(rst) mc_data_oe <= #1 1'b0;`
245			`else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d;`
246
247			`always @(posedge mc_clk)`
248			`mc_data_o <= #1 mc_data_od;`
249
250			`always @(posedge mc_clk)`
251			`mc_dp_o <= #1 mc_dp_od;`
252
253			`always @(posedge mc_clk)`
254			`mc_addr <= #1 mc_addr_d;`
255
256			`always @(posedge clk)`
257			`if(wb_cyc_i & wb_stb_i)`
258			`mc_dqm_r <= #1 wb_sel_i;`
259
260			`reg [3:0] mc_dqm_r2;`
261			`always @(posedge clk)`
262			`mc_dqm_r2 <= #1 mc_dqm_r;`
263
264			`always @(posedge mc_clk)`
265			`mc_dqm <= #1 susp_sel ? 4'hf :`
266			`data_oe ? ~mc_dqm_r2 :`
267			`(wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;`
268
269			`always @(posedge mc_clk or posedge rst)`
270			`if(rst) mc_oe_ <= #1 1'b1;`
271			`else mc_oe_ <= #1 oe_ \| susp_sel;`
272
273			`always @(posedge mc_clk)`
274			`mc_we_ <= #1 we_;`
275
276			`always @(posedge mc_clk)`
277			`mc_cas_ <= #1 cas_;`
278
279			`always @(posedge mc_clk)`
280			`mc_ras_ <= #1 ras_;`
281
282			`assign mc_cke_ = cke_;`
283
284			`always @(posedge mc_clk or posedge rst)`
285			`if(rst) mc_cs_[0] <= #1 1'b1;`
286			`else`
287			`mc_cs_[0] <= #1 ~(cs_en & (`
288			`(rfr_ack \| susp_sel) ? cs_need_rfr[0] :`
289			`lmr_sel ? spec_req_cs[0] :`
290			`cs[0]`
291			`));`
292
293			`always @(posedge mc_clk or posedge rst)`
294			`if(rst) mc_cs_[1] <= #1 1'b1;`
295			`else`
296			`mc_cs_[1] <= #1 ~(cs_en & (`
297			`(rfr_ack \| susp_sel) ? cs_need_rfr[1] :`
298			`lmr_sel ? spec_req_cs[1] :`
299			`cs[1]`
300			`));`
301
302			`always @(posedge mc_clk or posedge rst)`
303			`if(rst) mc_cs_[2] <= #1 1'b1;`
304			`else`
305			`mc_cs_[2] <= #1 ~(cs_en & (`
306			`(rfr_ack \| susp_sel) ? cs_need_rfr[2] :`
307			`lmr_sel ? spec_req_cs[2] :`
308			`cs[2]`
309			`));`
310
311			`always @(posedge mc_clk or posedge rst)`
312			`if(rst) mc_cs_[3] <= #1 1'b1;`
313			`else`
314			`mc_cs_[3] <= #1 ~(cs_en & (`
315			`(rfr_ack \| susp_sel) ? cs_need_rfr[3] :`
316			`lmr_sel ? spec_req_cs[3] :`
317			`cs[3]`
318			`));`
319
320			`always @(posedge mc_clk or posedge rst)`
321			`if(rst) mc_cs_[4] <= #1 1'b1;`
322			`else`
323			`mc_cs_[4] <= #1 ~(cs_en & (`
324			`(rfr_ack \| susp_sel) ? cs_need_rfr[4] :`
325			`lmr_sel ? spec_req_cs[4] :`
326			`cs[4]`
327			`));`
328
329			`always @(posedge mc_clk or posedge rst)`
330			`if(rst) mc_cs_[5] <= #1 1'b1;`
331			`else`
332			`mc_cs_[5] <= #1 ~(cs_en & (`
333			`(rfr_ack \| susp_sel) ? cs_need_rfr[5] :`
334			`lmr_sel ? spec_req_cs[5] :`
335			`cs[5]`
336			`));`
337
338			`always @(posedge mc_clk or posedge rst)`
339			`if(rst) mc_cs_[6] <= #1 1'b1;`
340			`else`
341			`mc_cs_[6] <= #1 ~(cs_en & (`
342			`(rfr_ack \| susp_sel) ? cs_need_rfr[6] :`
343			`lmr_sel ? spec_req_cs[6] :`
344			`cs[6]`
345			`));`
346
347			`always @(posedge mc_clk or posedge rst)`
348			`if(rst) mc_cs_[7] <= #1 1'b1;`
349			`else`
350			`mc_cs_[7] <= #1 ~(cs_en & (`
351			`(rfr_ack \| susp_sel) ? cs_need_rfr[7] :`
352			`lmr_sel ? spec_req_cs[7] :`
353			`cs[7]`
354			`));`
355
356			`always @(posedge mc_clk)`
357			`mc_adsc_ <= #1 ~mc_adsc_d;`
358
359			`always @(posedge mc_clk)`
360			`mc_adv_ <= #1 ~mc_adv_d;`
361
362			`endmodule`