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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_obct.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Open Bank & Row Tracking Block                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_obct.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
//  $Date: 2002/01/21 13:08:52 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: mc_obct.v,v $
//               Revision 1.4  2002/01/21 13:08:52  rudi
//
//               Fixed several minor bugs, cleaned up the code further ...
//
//               Revision 1.3  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.2  2001/09/24 00:38:21  rudi
//
//               Changed Reset to be active high and async.
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//               Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:45  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
                bank_open, any_bank_open, row_same);
input           clk, rst;
input   [12:0]   row_adr;
input   [1:0]    bank_adr;
input           bank_set;
input           bank_clr;
input           bank_clr_all;
output          bank_open;
output          any_bank_open;
output          row_same;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg             bank0_open, bank1_open, bank2_open, bank3_open;
reg             bank_open;
reg     [12:0]   b0_last_row;
reg     [12:0]   b1_last_row;
reg     [12:0]   b2_last_row;
reg     [12:0]   b3_last_row;
wire            row0_same, row1_same, row2_same, row3_same;
reg             row_same;
 
////////////////////////////////////////////////////////////////////
//
// Bank Open/Closed Tracking
//
 
always @(posedge clk or posedge rst)
        if(rst)                                 bank0_open <= #1 1'b0;
        else
        if((bank_adr == 2'h0) & bank_set)       bank0_open <= #1 1'b1;
        else
        if((bank_adr == 2'h0) & bank_clr)       bank0_open <= #1 1'b0;
        else
        if(bank_clr_all)                        bank0_open <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)                                 bank1_open <= #1 1'b0;
        else
        if((bank_adr == 2'h1) & bank_set)       bank1_open <= #1 1'b1;
        else
        if((bank_adr == 2'h1) & bank_clr)       bank1_open <= #1 1'b0;
        else
        if(bank_clr_all)                        bank1_open <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)                                 bank2_open <= #1 1'b0;
        else
        if((bank_adr == 2'h2) & bank_set)       bank2_open <= #1 1'b1;
        else
        if((bank_adr == 2'h2) & bank_clr)       bank2_open <= #1 1'b0;
        else
        if(bank_clr_all)                        bank2_open <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)                                 bank3_open <= #1 1'b0;
        else
        if((bank_adr == 2'h3) & bank_set)       bank3_open <= #1 1'b1;
        else
        if((bank_adr == 2'h3) & bank_clr)       bank3_open <= #1 1'b0;
        else
        if(bank_clr_all)                        bank3_open <= #1 1'b0;
 
always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open)
        case(bank_adr)          // synopsys full_case parallel_case
           2'h0: bank_open = bank0_open;
           2'h1: bank_open = bank1_open;
           2'h2: bank_open = bank2_open;
           2'h3: bank_open = bank3_open;
        endcase
 
assign any_bank_open = bank0_open | bank1_open | bank2_open | bank3_open;
 
////////////////////////////////////////////////////////////////////
//
// Raw Address Tracking
//
 
always @(posedge clk)
        if((bank_adr == 2'h0) & bank_set)       b0_last_row <= #1 row_adr;
 
always @(posedge clk)
        if((bank_adr == 2'h1) & bank_set)       b1_last_row <= #1 row_adr;
 
always @(posedge clk)
        if((bank_adr == 2'h2) & bank_set)       b2_last_row <= #1 row_adr;
 
always @(posedge clk)
        if((bank_adr == 2'h3) & bank_set)       b3_last_row <= #1 row_adr;
 
////////////////////////////////////////////////////////////////////
//
// Raw address checking
//
 
assign row0_same = (b0_last_row == row_adr);
assign row1_same = (b1_last_row == row_adr);
assign row2_same = (b2_last_row == row_adr);
assign row3_same = (b3_last_row == row_adr);
 
always @(bank_adr or row0_same or row1_same or row2_same or row3_same)
        case(bank_adr)          // synopsys full_case parallel_case
           2'h0: row_same = row0_same;
           2'h1: row_same = row1_same;
           2'h2: row_same = row2_same;
           2'h3: row_same = row3_same;
        endcase
 
endmodule
 
 
// This is used for unused Chip Selects
module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
                bank_open, any_bank_open, row_same);
input           clk, rst;
input   [12:0]   row_adr;
input   [1:0]    bank_adr;
input           bank_set;
input           bank_clr;
input           bank_clr_all;
output          bank_open;
output          any_bank_open;
output          row_same;
 
assign bank_open = 1'b0;
assign any_bank_open = 1'b0;
assign row_same = 1'b0;
 
endmodule

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_obct.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Open Bank & Row Tracking Block ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42			`// $Id: mc_obct.v,v 1.4 2002/01/21 13:08:52 rudi Exp $`
43			`//`
44			`// $Date: 2002/01/21 13:08:52 $`
45			`// $Revision: 1.4 $`
46			`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: mc_obct.v,v $`
52			`// Revision 1.4 2002/01/21 13:08:52 rudi`
53			`//`
54			`// Fixed several minor bugs, cleaned up the code further ...`
55			`//`
56			`// Revision 1.3 2001/11/29 02:16:28 rudi`
57			`//`
58			`//`
59			`// - More Synthesis cleanup, mostly for speed`
60			`// - Several bug fixes`
61			`// - Changed code to avoid auto-precharge and`
62			`// burst-terminate combinations (apparently illegal ?)`
63			`// Now we will do a manual precharge ...`
64			`//`
65			`// Revision 1.2 2001/09/24 00:38:21 rudi`
66			`//`
67			`// Changed Reset to be active high and async.`
68			`//`
69			`// Revision 1.1 2001/07/29 07:34:41 rudi`
70			`//`
71			`//`
72			`// 1) Changed Directory Structure`
73			`// 2) Fixed several minor bugs`
74			`//`
75			`// Revision 1.3 2001/06/12 15:19:49 rudi`
76			`//`
77			`//`
78			`// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.`
79			`//`
80			`// Revision 1.2 2001/06/03 11:37:17 rudi`
81			`//`
82			`//`
83			`// 1) Fixed Chip Select Mask Register`
84			`// - Power On Value is now all ones`
85			`// - Comparison Logic is now correct`
86			`//`
87			`// 2) All resets are now asynchronous`
88			`//`
89			`// 3) Converted Power On Delay to an configurable item`
90			`//`
91			`// 4) Added reset to Chip Select Output Registers`
92			`//`
93			`// 5) Forcing all outputs to Hi-Z state during reset`
94			`//`
95			`// Revision 1.1.1.1 2001/05/13 09:39:45 rudi`
96			`// Created Directory Structure`
97			`//`
98			`//`
99			`//`
100			`//`
101
102			`include "mc_defines.v"
103
104			`module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,`
105			`bank_open, any_bank_open, row_same);`
106			`input clk, rst;`
107			`input [12:0] row_adr;`
108			`input [1:0] bank_adr;`
109			`input bank_set;`
110			`input bank_clr;`
111			`input bank_clr_all;`
112			`output bank_open;`
113			`output any_bank_open;`
114			`output row_same;`
115
116			`////////////////////////////////////////////////////////////////////`
117			`//`
118			`// Local Registers & Wires`
119			`//`
120
121			`reg bank0_open, bank1_open, bank2_open, bank3_open;`
122			`reg bank_open;`
123			`reg [12:0] b0_last_row;`
124			`reg [12:0] b1_last_row;`
125			`reg [12:0] b2_last_row;`
126			`reg [12:0] b3_last_row;`
127			`wire row0_same, row1_same, row2_same, row3_same;`
128			`reg row_same;`
129
130			`////////////////////////////////////////////////////////////////////`
131			`//`
132			`// Bank Open/Closed Tracking`
133			`//`
134
135			`always @(posedge clk or posedge rst)`
136			`if(rst) bank0_open <= #1 1'b0;`
137			`else`
138			`if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1;`
139			`else`
140			`if((bank_adr == 2'h0) & bank_clr) bank0_open <= #1 1'b0;`
141			`else`
142			`if(bank_clr_all) bank0_open <= #1 1'b0;`
143
144			`always @(posedge clk or posedge rst)`
145			`if(rst) bank1_open <= #1 1'b0;`
146			`else`
147			`if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1;`
148			`else`
149			`if((bank_adr == 2'h1) & bank_clr) bank1_open <= #1 1'b0;`
150			`else`
151			`if(bank_clr_all) bank1_open <= #1 1'b0;`
152
153			`always @(posedge clk or posedge rst)`
154			`if(rst) bank2_open <= #1 1'b0;`
155			`else`
156			`if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1;`
157			`else`
158			`if((bank_adr == 2'h2) & bank_clr) bank2_open <= #1 1'b0;`
159			`else`
160			`if(bank_clr_all) bank2_open <= #1 1'b0;`
161
162			`always @(posedge clk or posedge rst)`
163			`if(rst) bank3_open <= #1 1'b0;`
164			`else`
165			`if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1;`
166			`else`
167			`if((bank_adr == 2'h3) & bank_clr) bank3_open <= #1 1'b0;`
168			`else`
169			`if(bank_clr_all) bank3_open <= #1 1'b0;`
170
171			`always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open)`
172			`case(bank_adr) // synopsys full_case parallel_case`
173			`2'h0: bank_open = bank0_open;`
174			`2'h1: bank_open = bank1_open;`
175			`2'h2: bank_open = bank2_open;`
176			`2'h3: bank_open = bank3_open;`
177			`endcase`
178
179			`assign any_bank_open = bank0_open \| bank1_open \| bank2_open \| bank3_open;`
180
181			`////////////////////////////////////////////////////////////////////`
182			`//`
183			`// Raw Address Tracking`
184			`//`
185
186			`always @(posedge clk)`
187			`if((bank_adr == 2'h0) & bank_set) b0_last_row <= #1 row_adr;`
188
189			`always @(posedge clk)`
190			`if((bank_adr == 2'h1) & bank_set) b1_last_row <= #1 row_adr;`
191
192			`always @(posedge clk)`
193			`if((bank_adr == 2'h2) & bank_set) b2_last_row <= #1 row_adr;`
194
195			`always @(posedge clk)`
196			`if((bank_adr == 2'h3) & bank_set) b3_last_row <= #1 row_adr;`
197
198			`////////////////////////////////////////////////////////////////////`
199			`//`
200			`// Raw address checking`
201			`//`
202
203			`assign row0_same = (b0_last_row == row_adr);`
204			`assign row1_same = (b1_last_row == row_adr);`
205			`assign row2_same = (b2_last_row == row_adr);`
206			`assign row3_same = (b3_last_row == row_adr);`
207
208			`always @(bank_adr or row0_same or row1_same or row2_same or row3_same)`
209			`case(bank_adr) // synopsys full_case parallel_case`
210			`2'h0: row_same = row0_same;`
211			`2'h1: row_same = row1_same;`
212			`2'h2: row_same = row2_same;`
213			`2'h3: row_same = row3_same;`
214			`endcase`
215
216			`endmodule`
217
218
219			`// This is used for unused Chip Selects`
220			`module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,`
221			`bank_open, any_bank_open, row_same);`
222			`input clk, rst;`
223			`input [12:0] row_adr;`
224			`input [1:0] bank_adr;`
225			`input bank_set;`
226			`input bank_clr;`
227			`input bank_clr_all;`
228			`output bank_open;`
229			`output any_bank_open;`
230			`output row_same;`
231
232			`assign bank_open = 1'b0;`
233			`assign any_bank_open = 1'b0;`
234			`assign row_same = 1'b0;`
235
236			`endmodule`