URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_obct_top.v] - Blame information for rev 5

Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Open Bank & Row Tracking Block Top Level                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_obct_top.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
//
//  $Date: 2002/01/21 13:08:52 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: mc_obct_top.v,v $
//               Revision 1.4  2002/01/21 13:08:52  rudi
//
//               Fixed several minor bugs, cleaned up the code further ...
//
//               Revision 1.3  2001/12/21 05:09:29  rudi
//
//               - Fixed combinatorial loops in synthesis
//               - Fixed byte select bug
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
                bank_open, any_bank_open, row_same, rfr_ack);
input           clk, rst;
input   [7:0]    cs;
input   [12:0]   row_adr;
input   [1:0]    bank_adr;
input           bank_set;
input           bank_clr;
input           bank_clr_all;
output          bank_open;
output          any_bank_open;
output          row_same;
input           rfr_ack;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg             bank_open;
reg             row_same;
reg             any_bank_open;
 
wire            bank_set_0;
wire            bank_clr_0;
wire            bank_clr_all_0;
wire            bank_open_0;
wire            row_same_0;
wire            any_bank_open_0;
 
wire            bank_set_1;
wire            bank_clr_1;
wire            bank_clr_all_1;
wire            bank_open_1;
wire            row_same_1;
wire            any_bank_open_1;
 
wire            bank_set_2;
wire            bank_clr_2;
wire            bank_clr_all_2;
wire            bank_open_2;
wire            row_same_2;
wire            any_bank_open_2;
 
wire            bank_set_3;
wire            bank_clr_3;
wire            bank_clr_all_3;
wire            bank_open_3;
wire            row_same_3;
wire            any_bank_open_3;
 
wire            bank_set_4;
wire            bank_clr_4;
wire            bank_clr_all_4;
wire            bank_open_4;
wire            row_same_4;
wire            any_bank_open_4;
 
wire            bank_set_5;
wire            bank_clr_5;
wire            bank_clr_all_5;
wire            bank_open_5;
wire            row_same_5;
wire            any_bank_open_5;
 
wire            bank_set_6;
wire            bank_clr_6;
wire            bank_clr_all_6;
wire            bank_open_6;
wire            row_same_6;
wire            any_bank_open_6;
 
wire            bank_set_7;
wire            bank_clr_7;
wire            bank_clr_all_7;
wire            bank_open_7;
wire            row_same_7;
wire            any_bank_open_7;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign bank_set_0 = cs[0] & bank_set;
assign bank_set_1 = cs[1] & bank_set;
assign bank_set_2 = cs[2] & bank_set;
assign bank_set_3 = cs[3] & bank_set;
assign bank_set_4 = cs[4] & bank_set;
assign bank_set_5 = cs[5] & bank_set;
assign bank_set_6 = cs[6] & bank_set;
assign bank_set_7 = cs[7] & bank_set;
 
assign bank_clr_0 = cs[0] & bank_clr;
assign bank_clr_1 = cs[1] & bank_clr;
assign bank_clr_2 = cs[2] & bank_clr;
assign bank_clr_3 = cs[3] & bank_clr;
assign bank_clr_4 = cs[4] & bank_clr;
assign bank_clr_5 = cs[5] & bank_clr;
assign bank_clr_6 = cs[6] & bank_clr;
assign bank_clr_7 = cs[7] & bank_clr;
 
assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack;
assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack;
assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack;
assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack;
assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack;
assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack;
assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack;
assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack;
 
always @(posedge clk)
        bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) |
                        (cs[2] & bank_open_2) | (cs[3] & bank_open_3) |
                        (cs[4] & bank_open_4) | (cs[5] & bank_open_5) |
                        (cs[6] & bank_open_6) | (cs[7] & bank_open_7);
 
always @(posedge clk)
        row_same <= #1  (cs[0] & row_same_0) | (cs[1] & row_same_1) |
                        (cs[2] & row_same_2) | (cs[3] & row_same_3) |
                        (cs[4] & row_same_4) | (cs[5] & row_same_5) |
                        (cs[6] & row_same_6) | (cs[7] & row_same_7);
 
always @(posedge clk)
        any_bank_open <= #1     (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) |
                                (cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) |
                                (cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) |
                                (cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7);
 
 
////////////////////////////////////////////////////////////////////
//
// OBCT Modules for each Chip Select
//
 
mc_obct u0(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_0      ),
                .bank_clr(      bank_clr_0      ),
                .bank_clr_all(  bank_clr_all_0  ),
                .bank_open(     bank_open_0     ),
                .any_bank_open( any_bank_open_0 ),
                .row_same(      row_same_0      )
                );
 
`ifdef MC_HAVE_CS1
mc_obct u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_1      ),
                .bank_clr(      bank_clr_1      ),
                .bank_clr_all(  bank_clr_all_1  ),
                .bank_open(     bank_open_1     ),
                .any_bank_open( any_bank_open_1 ),
                .row_same(      row_same_1      )
                );
`else
mc_obct_dummy   u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_1      ),
                .bank_clr(      bank_clr_1      ),
                .bank_clr_all(  bank_clr_all_1  ),
                .bank_open(     bank_open_1     ),
                .any_bank_open( any_bank_open_1 ),
                .row_same(      row_same_1      )
                );
`endif
 
`ifdef MC_HAVE_CS2
mc_obct u2(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_2      ),
                .bank_clr(      bank_clr_2      ),
                .bank_clr_all(  bank_clr_all_2  ),
                .bank_open(     bank_open_2     ),
                .any_bank_open( any_bank_open_2 ),
                .row_same(      row_same_2      )
                );
`else
mc_obct_dummy   u2(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_2      ),
                .bank_clr(      bank_clr_2      ),
                .bank_clr_all(  bank_clr_all_2  ),
                .bank_open(     bank_open_2     ),
                .any_bank_open( any_bank_open_2 ),
                .row_same(      row_same_2      )
                );
`endif
 
`ifdef MC_HAVE_CS3
mc_obct u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_3      ),
                .bank_clr(      bank_clr_3      ),
                .bank_clr_all(  bank_clr_all_3  ),
                .bank_open(     bank_open_3     ),
                .any_bank_open( any_bank_open_3 ),
                .row_same(      row_same_3      )
                );
`else
mc_obct_dummy   u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_3      ),
                .bank_clr(      bank_clr_3      ),
                .bank_clr_all(  bank_clr_all_3  ),
                .bank_open(     bank_open_3     ),
                .any_bank_open( any_bank_open_3 ),
                .row_same(      row_same_3      )
                );
`endif
 
`ifdef MC_HAVE_CS4
mc_obct u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_4      ),
                .bank_clr(      bank_clr_4      ),
                .bank_clr_all(  bank_clr_all_4  ),
                .bank_open(     bank_open_4     ),
                .any_bank_open( any_bank_open_4 ),
                .row_same(      row_same_4      )
                );
`else
mc_obct_dummy   u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_4      ),
                .bank_clr(      bank_clr_4      ),
                .bank_clr_all(  bank_clr_all_4  ),
                .bank_open(     bank_open_4     ),
                .any_bank_open( any_bank_open_4 ),
                .row_same(      row_same_4      )
                );
`endif
 
`ifdef MC_HAVE_CS5
mc_obct u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_5      ),
                .bank_clr(      bank_clr_5      ),
                .bank_clr_all(  bank_clr_all_5  ),
                .bank_open(     bank_open_5     ),
                .any_bank_open( any_bank_open_5 ),
                .row_same(      row_same_5      )
                );
`else
mc_obct_dummy   u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_5      ),
                .bank_clr(      bank_clr_5      ),
                .bank_clr_all(  bank_clr_all_5  ),
                .bank_open(     bank_open_5     ),
                .any_bank_open( any_bank_open_5 ),
                .row_same(      row_same_5      )
                );
`endif
 
`ifdef MC_HAVE_CS6
mc_obct u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_6      ),
                .bank_clr(      bank_clr_6      ),
                .bank_clr_all(  bank_clr_all_6  ),
                .bank_open(     bank_open_6     ),
                .any_bank_open( any_bank_open_6 ),
                .row_same(      row_same_6      )
                );
`else
mc_obct_dummy   u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_6      ),
                .bank_clr(      bank_clr_6      ),
                .bank_clr_all(  bank_clr_all_6  ),
                .bank_open(     bank_open_6     ),
                .any_bank_open( any_bank_open_6 ),
                .row_same(      row_same_6      )
                );
`endif
 
`ifdef MC_HAVE_CS7
mc_obct u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_7      ),
                .bank_clr(      bank_clr_7      ),
                .bank_clr_all(  bank_clr_all_7  ),
                .bank_open(     bank_open_7     ),
                .any_bank_open( any_bank_open_7 ),
                .row_same(      row_same_7      )
                );
`else
mc_obct_dummy   u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_7      ),
                .bank_clr(      bank_clr_7      ),
                .bank_clr_all(  bank_clr_all_7  ),
                .bank_open(     bank_open_7     ),
                .any_bank_open( any_bank_open_7 ),
                .row_same(      row_same_7      )
                );
`endif
 
endmodule

Browse

Tools

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_obct_top.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Open Bank & Row Tracking Block Top Level ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42			`// $Id: mc_obct_top.v,v 1.4 2002/01/21 13:08:52 rudi Exp $`
43			`//`
44			`// $Date: 2002/01/21 13:08:52 $`
45			`// $Revision: 1.4 $`
46			`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: mc_obct_top.v,v $`
52			`// Revision 1.4 2002/01/21 13:08:52 rudi`
53			`//`
54			`// Fixed several minor bugs, cleaned up the code further ...`
55			`//`
56			`// Revision 1.3 2001/12/21 05:09:29 rudi`
57			`//`
58			`// - Fixed combinatorial loops in synthesis`
59			`// - Fixed byte select bug`
60			`//`
61			`// Revision 1.2 2001/08/10 08:16:21 rudi`
62			`//`
63			`// - Changed IO names to be more clear.`
64			`// - Uniquifyed define names to be core specific.`
65			`// - Removed "Refresh Early" configuration`
66			`//`
67			`// Revision 1.1 2001/07/29 07:34:41 rudi`
68			`//`
69			`//`
70			`// 1) Changed Directory Structure`
71			`// 2) Fixed several minor bugs`
72			`//`
73			`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
74			`// Created Directory Structure`
75			`//`
76			`//`
77			`//`
78			`//`
79
80			`include "mc_defines.v"
81
82			`module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,`
83			`bank_open, any_bank_open, row_same, rfr_ack);`
84			`input clk, rst;`
85			`input [7:0] cs;`
86			`input [12:0] row_adr;`
87			`input [1:0] bank_adr;`
88			`input bank_set;`
89			`input bank_clr;`
90			`input bank_clr_all;`
91			`output bank_open;`
92			`output any_bank_open;`
93			`output row_same;`
94			`input rfr_ack;`
95
96			`////////////////////////////////////////////////////////////////////`
97			`//`
98			`// Local Registers & Wires`
99			`//`
100
101			`reg bank_open;`
102			`reg row_same;`
103			`reg any_bank_open;`
104
105			`wire bank_set_0;`
106			`wire bank_clr_0;`
107			`wire bank_clr_all_0;`
108			`wire bank_open_0;`
109			`wire row_same_0;`
110			`wire any_bank_open_0;`
111
112			`wire bank_set_1;`
113			`wire bank_clr_1;`
114			`wire bank_clr_all_1;`
115			`wire bank_open_1;`
116			`wire row_same_1;`
117			`wire any_bank_open_1;`
118
119			`wire bank_set_2;`
120			`wire bank_clr_2;`
121			`wire bank_clr_all_2;`
122			`wire bank_open_2;`
123			`wire row_same_2;`
124			`wire any_bank_open_2;`
125
126			`wire bank_set_3;`
127			`wire bank_clr_3;`
128			`wire bank_clr_all_3;`
129			`wire bank_open_3;`
130			`wire row_same_3;`
131			`wire any_bank_open_3;`
132
133			`wire bank_set_4;`
134			`wire bank_clr_4;`
135			`wire bank_clr_all_4;`
136			`wire bank_open_4;`
137			`wire row_same_4;`
138			`wire any_bank_open_4;`
139
140			`wire bank_set_5;`
141			`wire bank_clr_5;`
142			`wire bank_clr_all_5;`
143			`wire bank_open_5;`
144			`wire row_same_5;`
145			`wire any_bank_open_5;`
146
147			`wire bank_set_6;`
148			`wire bank_clr_6;`
149			`wire bank_clr_all_6;`
150			`wire bank_open_6;`
151			`wire row_same_6;`
152			`wire any_bank_open_6;`
153
154			`wire bank_set_7;`
155			`wire bank_clr_7;`
156			`wire bank_clr_all_7;`
157			`wire bank_open_7;`
158			`wire row_same_7;`
159			`wire any_bank_open_7;`
160
161			`////////////////////////////////////////////////////////////////////`
162			`//`
163			`// Misc Logic`
164			`//`
165
166			`assign bank_set_0 = cs[0] & bank_set;`
167			`assign bank_set_1 = cs[1] & bank_set;`
168			`assign bank_set_2 = cs[2] & bank_set;`
169			`assign bank_set_3 = cs[3] & bank_set;`
170			`assign bank_set_4 = cs[4] & bank_set;`
171			`assign bank_set_5 = cs[5] & bank_set;`
172			`assign bank_set_6 = cs[6] & bank_set;`
173			`assign bank_set_7 = cs[7] & bank_set;`
174
175			`assign bank_clr_0 = cs[0] & bank_clr;`
176			`assign bank_clr_1 = cs[1] & bank_clr;`
177			`assign bank_clr_2 = cs[2] & bank_clr;`
178			`assign bank_clr_3 = cs[3] & bank_clr;`
179			`assign bank_clr_4 = cs[4] & bank_clr;`
180			`assign bank_clr_5 = cs[5] & bank_clr;`
181			`assign bank_clr_6 = cs[6] & bank_clr;`
182			`assign bank_clr_7 = cs[7] & bank_clr;`
183
184			`assign bank_clr_all_0 = (cs[0] & bank_clr_all) \| rfr_ack;`
185			`assign bank_clr_all_1 = (cs[1] & bank_clr_all) \| rfr_ack;`
186			`assign bank_clr_all_2 = (cs[2] & bank_clr_all) \| rfr_ack;`
187			`assign bank_clr_all_3 = (cs[3] & bank_clr_all) \| rfr_ack;`
188			`assign bank_clr_all_4 = (cs[4] & bank_clr_all) \| rfr_ack;`
189			`assign bank_clr_all_5 = (cs[5] & bank_clr_all) \| rfr_ack;`
190			`assign bank_clr_all_6 = (cs[6] & bank_clr_all) \| rfr_ack;`
191			`assign bank_clr_all_7 = (cs[7] & bank_clr_all) \| rfr_ack;`
192
193			`always @(posedge clk)`
194			`bank_open <= #1 (cs[0] & bank_open_0) \| (cs[1] & bank_open_1) \|`
195			`(cs[2] & bank_open_2) \| (cs[3] & bank_open_3) \|`
196			`(cs[4] & bank_open_4) \| (cs[5] & bank_open_5) \|`
197			`(cs[6] & bank_open_6) \| (cs[7] & bank_open_7);`
198
199			`always @(posedge clk)`
200			`row_same <= #1 (cs[0] & row_same_0) \| (cs[1] & row_same_1) \|`
201			`(cs[2] & row_same_2) \| (cs[3] & row_same_3) \|`
202			`(cs[4] & row_same_4) \| (cs[5] & row_same_5) \|`
203			`(cs[6] & row_same_6) \| (cs[7] & row_same_7);`
204
205			`always @(posedge clk)`
206			`any_bank_open <= #1 (cs[0] & any_bank_open_0) \| (cs[1] & any_bank_open_1) \|`
207			`(cs[2] & any_bank_open_2) \| (cs[3] & any_bank_open_3) \|`
208			`(cs[4] & any_bank_open_4) \| (cs[5] & any_bank_open_5) \|`
209			`(cs[6] & any_bank_open_6) \| (cs[7] & any_bank_open_7);`
210
211
212			`////////////////////////////////////////////////////////////////////`
213			`//`
214			`// OBCT Modules for each Chip Select`
215			`//`
216
217			`mc_obct u0(`
218			`.clk( clk ),`
219			`.rst( rst ),`
220			`.row_adr( row_adr ),`
221			`.bank_adr( bank_adr ),`
222			`.bank_set( bank_set_0 ),`
223			`.bank_clr( bank_clr_0 ),`
224			`.bank_clr_all( bank_clr_all_0 ),`
225			`.bank_open( bank_open_0 ),`
226			`.any_bank_open( any_bank_open_0 ),`
227			`.row_same( row_same_0 )`
228			`);`
229
230			`ifdef MC_HAVE_CS1
231			`mc_obct u1(`
232			`.clk( clk ),`
233			`.rst( rst ),`
234			`.row_adr( row_adr ),`
235			`.bank_adr( bank_adr ),`
236			`.bank_set( bank_set_1 ),`
237			`.bank_clr( bank_clr_1 ),`
238			`.bank_clr_all( bank_clr_all_1 ),`
239			`.bank_open( bank_open_1 ),`
240			`.any_bank_open( any_bank_open_1 ),`
241			`.row_same( row_same_1 )`
242			`);`
243			`else
244			`mc_obct_dummy u1(`
245			`.clk( clk ),`
246			`.rst( rst ),`
247			`.row_adr( row_adr ),`
248			`.bank_adr( bank_adr ),`
249			`.bank_set( bank_set_1 ),`
250			`.bank_clr( bank_clr_1 ),`
251			`.bank_clr_all( bank_clr_all_1 ),`
252			`.bank_open( bank_open_1 ),`
253			`.any_bank_open( any_bank_open_1 ),`
254			`.row_same( row_same_1 )`
255			`);`
256			`endif
257
258			`ifdef MC_HAVE_CS2
259			`mc_obct u2(`
260			`.clk( clk ),`
261			`.rst( rst ),`
262			`.row_adr( row_adr ),`
263			`.bank_adr( bank_adr ),`
264			`.bank_set( bank_set_2 ),`
265			`.bank_clr( bank_clr_2 ),`
266			`.bank_clr_all( bank_clr_all_2 ),`
267			`.bank_open( bank_open_2 ),`
268			`.any_bank_open( any_bank_open_2 ),`
269			`.row_same( row_same_2 )`
270			`);`
271			`else
272			`mc_obct_dummy u2(`
273			`.clk( clk ),`
274			`.rst( rst ),`
275			`.row_adr( row_adr ),`
276			`.bank_adr( bank_adr ),`
277			`.bank_set( bank_set_2 ),`
278			`.bank_clr( bank_clr_2 ),`
279			`.bank_clr_all( bank_clr_all_2 ),`
280			`.bank_open( bank_open_2 ),`
281			`.any_bank_open( any_bank_open_2 ),`
282			`.row_same( row_same_2 )`
283			`);`
284			`endif
285
286			`ifdef MC_HAVE_CS3
287			`mc_obct u3(`
288			`.clk( clk ),`
289			`.rst( rst ),`
290			`.row_adr( row_adr ),`
291			`.bank_adr( bank_adr ),`
292			`.bank_set( bank_set_3 ),`
293			`.bank_clr( bank_clr_3 ),`
294			`.bank_clr_all( bank_clr_all_3 ),`
295			`.bank_open( bank_open_3 ),`
296			`.any_bank_open( any_bank_open_3 ),`
297			`.row_same( row_same_3 )`
298			`);`
299			`else
300			`mc_obct_dummy u3(`
301			`.clk( clk ),`
302			`.rst( rst ),`
303			`.row_adr( row_adr ),`
304			`.bank_adr( bank_adr ),`
305			`.bank_set( bank_set_3 ),`
306			`.bank_clr( bank_clr_3 ),`
307			`.bank_clr_all( bank_clr_all_3 ),`
308			`.bank_open( bank_open_3 ),`
309			`.any_bank_open( any_bank_open_3 ),`
310			`.row_same( row_same_3 )`
311			`);`
312			`endif
313
314			`ifdef MC_HAVE_CS4
315			`mc_obct u4(`
316			`.clk( clk ),`
317			`.rst( rst ),`
318			`.row_adr( row_adr ),`
319			`.bank_adr( bank_adr ),`
320			`.bank_set( bank_set_4 ),`
321			`.bank_clr( bank_clr_4 ),`
322			`.bank_clr_all( bank_clr_all_4 ),`
323			`.bank_open( bank_open_4 ),`
324			`.any_bank_open( any_bank_open_4 ),`
325			`.row_same( row_same_4 )`
326			`);`
327			`else
328			`mc_obct_dummy u4(`
329			`.clk( clk ),`
330			`.rst( rst ),`
331			`.row_adr( row_adr ),`
332			`.bank_adr( bank_adr ),`
333			`.bank_set( bank_set_4 ),`
334			`.bank_clr( bank_clr_4 ),`
335			`.bank_clr_all( bank_clr_all_4 ),`
336			`.bank_open( bank_open_4 ),`
337			`.any_bank_open( any_bank_open_4 ),`
338			`.row_same( row_same_4 )`
339			`);`
340			`endif
341
342			`ifdef MC_HAVE_CS5
343			`mc_obct u5(`
344			`.clk( clk ),`
345			`.rst( rst ),`
346			`.row_adr( row_adr ),`
347			`.bank_adr( bank_adr ),`
348			`.bank_set( bank_set_5 ),`
349			`.bank_clr( bank_clr_5 ),`
350			`.bank_clr_all( bank_clr_all_5 ),`
351			`.bank_open( bank_open_5 ),`
352			`.any_bank_open( any_bank_open_5 ),`
353			`.row_same( row_same_5 )`
354			`);`
355			`else
356			`mc_obct_dummy u5(`
357			`.clk( clk ),`
358			`.rst( rst ),`
359			`.row_adr( row_adr ),`
360			`.bank_adr( bank_adr ),`
361			`.bank_set( bank_set_5 ),`
362			`.bank_clr( bank_clr_5 ),`
363			`.bank_clr_all( bank_clr_all_5 ),`
364			`.bank_open( bank_open_5 ),`
365			`.any_bank_open( any_bank_open_5 ),`
366			`.row_same( row_same_5 )`
367			`);`
368			`endif
369
370			`ifdef MC_HAVE_CS6
371			`mc_obct u6(`
372			`.clk( clk ),`
373			`.rst( rst ),`
374			`.row_adr( row_adr ),`
375			`.bank_adr( bank_adr ),`
376			`.bank_set( bank_set_6 ),`
377			`.bank_clr( bank_clr_6 ),`
378			`.bank_clr_all( bank_clr_all_6 ),`
379			`.bank_open( bank_open_6 ),`
380			`.any_bank_open( any_bank_open_6 ),`
381			`.row_same( row_same_6 )`
382			`);`
383			`else
384			`mc_obct_dummy u6(`
385			`.clk( clk ),`
386			`.rst( rst ),`
387			`.row_adr( row_adr ),`
388			`.bank_adr( bank_adr ),`
389			`.bank_set( bank_set_6 ),`
390			`.bank_clr( bank_clr_6 ),`
391			`.bank_clr_all( bank_clr_all_6 ),`
392			`.bank_open( bank_open_6 ),`
393			`.any_bank_open( any_bank_open_6 ),`
394			`.row_same( row_same_6 )`
395			`);`
396			`endif
397
398			`ifdef MC_HAVE_CS7
399			`mc_obct u7(`
400			`.clk( clk ),`
401			`.rst( rst ),`
402			`.row_adr( row_adr ),`
403			`.bank_adr( bank_adr ),`
404			`.bank_set( bank_set_7 ),`
405			`.bank_clr( bank_clr_7 ),`
406			`.bank_clr_all( bank_clr_all_7 ),`
407			`.bank_open( bank_open_7 ),`
408			`.any_bank_open( any_bank_open_7 ),`
409			`.row_same( row_same_7 )`
410			`);`
411			`else
412			`mc_obct_dummy u7(`
413			`.clk( clk ),`
414			`.rst( rst ),`
415			`.row_adr( row_adr ),`
416			`.bank_adr( bank_adr ),`
417			`.bank_set( bank_set_7 ),`
418			`.bank_clr( bank_clr_7 ),`
419			`.bank_clr_all( bank_clr_all_7 ),`
420			`.bank_open( bank_open_7 ),`
421			`.any_bank_open( any_bank_open_7 ),`
422			`.row_same( row_same_7 )`
423			`);`
424			`endif
425
426			`endmodule`