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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Memory Controller Register File ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: mc_rf.v,v 1.8 2002/01/21 13:08:52 rudi Exp $
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//
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// $Date: 2002/01/21 13:08:52 $
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// $Revision: 1.8 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: mc_rf.v,v $
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// Revision 1.8 2002/01/21 13:08:52 rudi
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//
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// Fixed several minor bugs, cleaned up the code further ...
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//
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// Revision 1.7 2001/12/21 05:09:29 rudi
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//
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// - Fixed combinatorial loops in synthesis
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// - Fixed byte select bug
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//
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// Revision 1.6 2001/12/11 02:47:19 rudi
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//
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// - Made some changes not to expect clock during reset ...
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//
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// Revision 1.5 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.4 2001/10/04 03:19:37 rudi
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//
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// Fixed Register reads
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// Tightened up timing for register rd/wr
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//
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// Revision 1.3 2001/09/24 00:38:21 rudi
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//
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// Changed Reset to be active high and async.
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Comparison Logic is now correct
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//
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// 2) All resets are now asynchronous
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//
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// 3) Converted Power On Delay to an configurable item
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//
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// 4) Added reset to Chip Select Output Registers
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//
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// 5) Forcing all outputs to Hi-Z state during reset
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//
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// Revision 1.1.1.1 2001/05/13 09:39:42 rudi
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// Created Directory Structure
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//
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//
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//
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//
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`include "mc_defines.v"
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module mc_rf(clk, rst,
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wb_data_i, rf_dout, wb_addr_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wp_err,
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csc, tms, poc,
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sp_csc, sp_tms, cs,
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mc_data_i, mc_sts, mc_vpen, fs,
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cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,
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init_ack, lmr_req, lmr_ack,
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spec_req_cs
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);
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input clk, rst;
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// --------------------------------------
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// WISHBONE INTERFACE
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// Slave Interface
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input [31:0] wb_data_i;
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output [31:0] rf_dout;
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input [31:0] wb_addr_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_stb_i;
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output wb_ack_o;
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output wp_err;
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// --------------------------------------
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// Misc Signals
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output [31:0] csc;
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output [31:0] tms;
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output [31:0] poc;
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output [31:0] sp_csc;
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output [31:0] sp_tms;
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output [7:0] cs;
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input [31:0] mc_data_i;
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input mc_sts;
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output mc_vpen;
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output fs;
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input cs_le_d;
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input cs_le;
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output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM
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// attached and need to be refreshed
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output [2:0] ref_int; // Refresh Interval
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output [7:0] rfr_ps_val;
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output init_req;
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input init_ack;
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output lmr_req;
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input lmr_ack;
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output [7:0] spec_req_cs;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg wb_ack_o;
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reg [31:0] csc;
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reg [31:0] tms;
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reg [31:0] sp_csc;
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reg [31:0] sp_tms;
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reg [31:0] rf_dout;
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reg [7:0] cs;
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reg rf_we;
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wire [31:0] csr;
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reg [10:0] csr_r;
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reg [7:0] csr_r2;
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reg [31:0] poc;
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wire [31:0] csc_mask;
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reg [10:0] csc_mask_r;
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wire [31:0] csc0, tms0;
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wire [31:0] csc1, tms1;
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wire [31:0] csc2, tms2;
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wire [31:0] csc3, tms3;
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wire [31:0] csc4, tms4;
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wire [31:0] csc5, tms5;
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wire [31:0] csc6, tms6;
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wire [31:0] csc7, tms7;
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wire cs0, cs1, cs2, cs3;
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wire cs4, cs5, cs6, cs7;
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wire wp_err0, wp_err1, wp_err2, wp_err3;
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wire wp_err4, wp_err5, wp_err6, wp_err7;
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reg wp_err;
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wire lmr_req7, lmr_req6, lmr_req5, lmr_req4;
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wire lmr_req3, lmr_req2, lmr_req1, lmr_req0;
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wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4;
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wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0;
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wire init_req7, init_req6, init_req5, init_req4;
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wire init_req3, init_req2, init_req1, init_req0;
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wire init_ack7, init_ack6, init_ack5, init_ack4;
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wire init_ack3, init_ack2, init_ack1, init_ack0;
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reg init_ack_r;
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wire init_ack_fe;
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reg lmr_ack_r;
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wire lmr_ack_fe;
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wire [7:0] spec_req_cs_t;
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wire [7:0] spec_req_cs_d;
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reg [7:0] spec_req_cs;
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reg init_req, lmr_req;
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reg sreq_cs_le;
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// Aliases
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assign csr = {csr_r2, 8'h0, 5'h0, csr_r};
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assign csc_mask = {21'h0, csc_mask_r};
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////////////////////////////////////////////////////////////////////
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//
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// WISHBONE Register Read logic
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//
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always @(wb_addr_i or csr or poc or csc_mask or csc0 or tms0 or csc1 or
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tms1 or csc2 or tms2 or csc3 or tms3 or csc4 or tms4 or csc5 or
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tms5 or csc6 or tms6 or csc7 or tms7)
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case(wb_addr_i[6:2]) // synopsys full_case parallel_case
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5'h00: rf_dout <= #1 csr;
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5'h01: rf_dout <= #1 poc;
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5'h02: rf_dout <= #1 csc_mask;
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5'h04: rf_dout <= #1 csc0;
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5'h05: rf_dout <= #1 tms0;
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5'h06: rf_dout <= #1 csc1;
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5'h07: rf_dout <= #1 tms1;
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5'h08: rf_dout <= #1 csc2;
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5'h09: rf_dout <= #1 tms2;
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5'h0a: rf_dout <= #1 csc3;
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5'h0b: rf_dout <= #1 tms3;
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5'h0c: rf_dout <= #1 csc4;
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5'h0d: rf_dout <= #1 tms4;
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5'h0e: rf_dout <= #1 csc5;
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5'h0f: rf_dout <= #1 tms5;
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5'h10: rf_dout <= #1 csc6;
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5'h11: rf_dout <= #1 tms6;
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5'h12: rf_dout <= #1 csc7;
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5'h13: rf_dout <= #1 tms7;
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endcase
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////////////////////////////////////////////////////////////////////
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//
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// WISHBONE Register Write logic
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//
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reg [6:0] wb_addr_r;
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always @(posedge clk)
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wb_addr_r <= #1 wb_addr_i[6:0];
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always @(posedge clk or posedge rst)
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if(rst) rf_we <= #1 1'b0;
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else rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we;
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always @(posedge clk or posedge rst)
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if(rst) csr_r2 <= #1 8'h0;
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else
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if(rf_we & (wb_addr_r[6:2] == 5'h0) )
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csr_r2 <= #1 wb_data_i[31:24];
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always @(posedge clk or posedge rst)
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if(rst) csr_r[10:1] <= #1 10'h0;
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else
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if(rf_we & (wb_addr_r[6:2] == 5'h0) )
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csr_r[10:1] <= #1 wb_data_i[10:1];
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always @(posedge clk)
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csr_r[0] <= #1 mc_sts;
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assign mc_vpen = csr_r[1];
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assign fs = csr_r[2];
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assign rfr_ps_val = csr_r2[7:0];
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always @(posedge clk or posedge rst)
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if(rst) csc_mask_r <= #1 `MC_BA_MASK_VAL;
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else
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if(rf_we & (wb_addr_r[6:2] == 5'h2) )
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csc_mask_r <= #1 wb_data_i[10:0];
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////////////////////////////////////////////////////////////////////
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| 314 |
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//
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| 315 |
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// A kludge for cases where there is no clock during reset ...
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| 316 |
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//
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| 317 |
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reg rst_r1, rst_r2, rst_r3;
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always @(posedge clk or posedge rst)
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if(rst) rst_r1 <= #1 1'b1;
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else rst_r1 <= #1 1'b0;
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always @(posedge clk or posedge rst)
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if(rst) rst_r2 <= #1 1'b1;
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else rst_r2 <= #1 rst_r1;
|
| 327 |
|
|
|
| 328 |
|
|
always @(posedge clk or posedge rst)
|
| 329 |
|
|
if(rst) rst_r3 <= #1 1'b1;
|
| 330 |
|
|
else rst_r3 <= #1 rst_r2;
|
| 331 |
|
|
|
| 332 |
|
|
always @(posedge clk)
|
| 333 |
|
|
if(rst_r3) poc <= #1 `MC_POC_VAL;
|
| 334 |
|
|
|
| 335 |
|
|
////////////////////////////////////////////////////////////////////
|
| 336 |
|
|
//
|
| 337 |
|
|
// WISHBONE Register Ack logic
|
| 338 |
|
|
//
|
| 339 |
|
|
|
| 340 |
|
|
always @(posedge clk)
|
| 341 |
|
|
wb_ack_o <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
|
| 342 |
|
|
|
| 343 |
|
|
////////////////////////////////////////////////////////////////////
|
| 344 |
|
|
//
|
| 345 |
|
|
// Select CSC and TMS Registers
|
| 346 |
|
|
//
|
| 347 |
|
|
|
| 348 |
|
|
always @(posedge clk or posedge rst)
|
| 349 |
|
|
if(rst) cs <= #1 8'h0;
|
| 350 |
|
|
else
|
| 351 |
|
|
if(cs_le) cs <= #1 {cs7, cs6, cs5, cs4, cs3, cs2, cs1, cs0};
|
| 352 |
|
|
|
| 353 |
|
|
always @(posedge clk or posedge rst)
|
| 354 |
|
|
if(rst) wp_err <= #1 1'b0;
|
| 355 |
|
|
else
|
| 356 |
|
|
if(cs_le & wb_cyc_i & wb_stb_i)
|
| 357 |
|
|
wp_err <= #1 wp_err7 | wp_err6 | wp_err5 | wp_err4 |
|
| 358 |
|
|
wp_err3 | wp_err2 | wp_err1 | wp_err0;
|
| 359 |
|
|
else
|
| 360 |
|
|
if(!wb_cyc_i) wp_err <= #1 1'b0;
|
| 361 |
|
|
|
| 362 |
|
|
always @(posedge clk or posedge rst)
|
| 363 |
|
|
if(rst) csc <= #1 32'h0;
|
| 364 |
|
|
else
|
| 365 |
|
|
if(cs_le_d & wb_cyc_i & wb_stb_i)
|
| 366 |
|
|
begin
|
| 367 |
|
|
if(cs0) csc <= #1 csc0;
|
| 368 |
|
|
else
|
| 369 |
|
|
if(cs1) csc <= #1 csc1;
|
| 370 |
|
|
else
|
| 371 |
|
|
if(cs2) csc <= #1 csc2;
|
| 372 |
|
|
else
|
| 373 |
|
|
if(cs3) csc <= #1 csc3;
|
| 374 |
|
|
else
|
| 375 |
|
|
if(cs4) csc <= #1 csc4;
|
| 376 |
|
|
else
|
| 377 |
|
|
if(cs5) csc <= #1 csc5;
|
| 378 |
|
|
else
|
| 379 |
|
|
if(cs6) csc <= #1 csc6;
|
| 380 |
|
|
else csc <= #1 csc7;
|
| 381 |
|
|
end
|
| 382 |
|
|
|
| 383 |
|
|
always @(posedge clk or posedge rst)
|
| 384 |
|
|
if(rst) tms <= #1 32'hffff_ffff;
|
| 385 |
|
|
else
|
| 386 |
|
|
if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)
|
| 387 |
|
|
begin
|
| 388 |
|
|
if(cs0) tms <= #1 tms0;
|
| 389 |
|
|
else
|
| 390 |
|
|
if(cs1) tms <= #1 tms1;
|
| 391 |
|
|
else
|
| 392 |
|
|
if(cs2) tms <= #1 tms2;
|
| 393 |
|
|
else
|
| 394 |
|
|
if(cs3) tms <= #1 tms3;
|
| 395 |
|
|
else
|
| 396 |
|
|
if(cs4) tms <= #1 tms4;
|
| 397 |
|
|
else
|
| 398 |
|
|
if(cs5) tms <= #1 tms5;
|
| 399 |
|
|
else
|
| 400 |
|
|
if(cs6) tms <= #1 tms6;
|
| 401 |
|
|
else tms <= #1 tms7;
|
| 402 |
|
|
end
|
| 403 |
|
|
|
| 404 |
|
|
always @(posedge clk or posedge rst)
|
| 405 |
|
|
if(rst) sp_csc <= #1 32'h0;
|
| 406 |
|
|
else
|
| 407 |
|
|
if(cs_le_d & wb_cyc_i & wb_stb_i)
|
| 408 |
|
|
begin
|
| 409 |
|
|
if(spec_req_cs[0]) sp_csc <= #1 csc0;
|
| 410 |
|
|
else
|
| 411 |
|
|
if(spec_req_cs[1]) sp_csc <= #1 csc1;
|
| 412 |
|
|
else
|
| 413 |
|
|
if(spec_req_cs[2]) sp_csc <= #1 csc2;
|
| 414 |
|
|
else
|
| 415 |
|
|
if(spec_req_cs[3]) sp_csc <= #1 csc3;
|
| 416 |
|
|
else
|
| 417 |
|
|
if(spec_req_cs[4]) sp_csc <= #1 csc4;
|
| 418 |
|
|
else
|
| 419 |
|
|
if(spec_req_cs[5]) sp_csc <= #1 csc5;
|
| 420 |
|
|
else
|
| 421 |
|
|
if(spec_req_cs[6]) sp_csc <= #1 csc6;
|
| 422 |
|
|
else sp_csc <= #1 csc7;
|
| 423 |
|
|
end
|
| 424 |
|
|
|
| 425 |
|
|
always @(posedge clk or posedge rst)
|
| 426 |
|
|
if(rst) sp_tms <= #1 32'hffff_ffff;
|
| 427 |
|
|
else
|
| 428 |
|
|
if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)
|
| 429 |
|
|
begin
|
| 430 |
|
|
if(spec_req_cs[0]) sp_tms <= #1 tms0;
|
| 431 |
|
|
else
|
| 432 |
|
|
if(spec_req_cs[1]) sp_tms <= #1 tms1;
|
| 433 |
|
|
else
|
| 434 |
|
|
if(spec_req_cs[2]) sp_tms <= #1 tms2;
|
| 435 |
|
|
else
|
| 436 |
|
|
if(spec_req_cs[3]) sp_tms <= #1 tms3;
|
| 437 |
|
|
else
|
| 438 |
|
|
if(spec_req_cs[4]) sp_tms <= #1 tms4;
|
| 439 |
|
|
else
|
| 440 |
|
|
if(spec_req_cs[5]) sp_tms <= #1 tms5;
|
| 441 |
|
|
else
|
| 442 |
|
|
if(spec_req_cs[6]) sp_tms <= #1 tms6;
|
| 443 |
|
|
else sp_tms <= #1 tms7;
|
| 444 |
|
|
end
|
| 445 |
|
|
|
| 446 |
|
|
assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 447 |
|
|
assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 448 |
|
|
assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 449 |
|
|
assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 450 |
|
|
assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 451 |
|
|
assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 452 |
|
|
assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 453 |
|
|
assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MC_MEM_TYPE_SDRAM);
|
| 454 |
|
|
|
| 455 |
|
|
assign ref_int = csr_r[10:8];
|
| 456 |
|
|
|
| 457 |
|
|
////////////////////////////////////////////////////////////////////
|
| 458 |
|
|
//
|
| 459 |
|
|
// Init & Lmr Logic
|
| 460 |
|
|
//
|
| 461 |
|
|
|
| 462 |
|
|
// Init Ack falling edge detector
|
| 463 |
|
|
always @(posedge clk)
|
| 464 |
|
|
init_ack_r <= #1 init_ack;
|
| 465 |
|
|
|
| 466 |
|
|
assign init_ack_fe = init_ack_r & !init_ack;
|
| 467 |
|
|
|
| 468 |
|
|
// LMR Ack falling edge detector
|
| 469 |
|
|
always @(posedge clk)
|
| 470 |
|
|
lmr_ack_r <= #1 lmr_ack;
|
| 471 |
|
|
|
| 472 |
|
|
assign lmr_ack_fe = lmr_ack_r & !lmr_ack;
|
| 473 |
|
|
|
| 474 |
|
|
// Chip Select Output
|
| 475 |
|
|
always @(posedge clk or posedge rst)
|
| 476 |
|
|
if(rst) spec_req_cs <= #1 8'h0;
|
| 477 |
|
|
else
|
| 478 |
|
|
if(sreq_cs_le) spec_req_cs <= #1 spec_req_cs_d;
|
| 479 |
|
|
|
| 480 |
|
|
always @(posedge clk or posedge rst)
|
| 481 |
|
|
if(rst) sreq_cs_le <= #1 1'b0;
|
| 482 |
|
|
else sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe;
|
| 483 |
|
|
|
| 484 |
|
|
// Make sure only one is serviced at a time
|
| 485 |
|
|
assign spec_req_cs_d[0] = spec_req_cs_t[0];
|
| 486 |
|
|
assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0];
|
| 487 |
|
|
assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] );
|
| 488 |
|
|
assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] );
|
| 489 |
|
|
assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] );
|
| 490 |
|
|
assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] );
|
| 491 |
|
|
assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] );
|
| 492 |
|
|
assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] );
|
| 493 |
|
|
|
| 494 |
|
|
// Request Tracking
|
| 495 |
|
|
always @(posedge clk or posedge rst)
|
| 496 |
|
|
if(rst) init_req <= #1 1'b0;
|
| 497 |
|
|
else init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 |
|
| 498 |
|
|
init_req4 | init_req5 | init_req6 | init_req7;
|
| 499 |
|
|
|
| 500 |
|
|
always @(posedge clk or posedge rst)
|
| 501 |
|
|
if(rst) lmr_req <= #1 1'b0;
|
| 502 |
|
|
else lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 |
|
| 503 |
|
|
lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7;
|
| 504 |
|
|
|
| 505 |
|
|
assign spec_req_cs_t = !init_req ? // Load Mode Register Requests
|
| 506 |
|
|
{lmr_req7, lmr_req6, lmr_req5, lmr_req4,
|
| 507 |
|
|
lmr_req3, lmr_req2, lmr_req1, lmr_req0 } :
|
| 508 |
|
|
// Initialize SDRAM Requests
|
| 509 |
|
|
{init_req7, init_req6, init_req5, init_req4,
|
| 510 |
|
|
init_req3, init_req2, init_req1, init_req0 };
|
| 511 |
|
|
|
| 512 |
|
|
// Ack distribution
|
| 513 |
|
|
assign lmr_ack0 = spec_req_cs[0] & lmr_ack_fe;
|
| 514 |
|
|
assign lmr_ack1 = spec_req_cs[1] & lmr_ack_fe;
|
| 515 |
|
|
assign lmr_ack2 = spec_req_cs[2] & lmr_ack_fe;
|
| 516 |
|
|
assign lmr_ack3 = spec_req_cs[3] & lmr_ack_fe;
|
| 517 |
|
|
assign lmr_ack4 = spec_req_cs[4] & lmr_ack_fe;
|
| 518 |
|
|
assign lmr_ack5 = spec_req_cs[5] & lmr_ack_fe;
|
| 519 |
|
|
assign lmr_ack6 = spec_req_cs[6] & lmr_ack_fe;
|
| 520 |
|
|
assign lmr_ack7 = spec_req_cs[7] & lmr_ack_fe;
|
| 521 |
|
|
|
| 522 |
|
|
assign init_ack0 = spec_req_cs[0] & init_ack_fe;
|
| 523 |
|
|
assign init_ack1 = spec_req_cs[1] & init_ack_fe;
|
| 524 |
|
|
assign init_ack2 = spec_req_cs[2] & init_ack_fe;
|
| 525 |
|
|
assign init_ack3 = spec_req_cs[3] & init_ack_fe;
|
| 526 |
|
|
assign init_ack4 = spec_req_cs[4] & init_ack_fe;
|
| 527 |
|
|
assign init_ack5 = spec_req_cs[5] & init_ack_fe;
|
| 528 |
|
|
assign init_ack6 = spec_req_cs[6] & init_ack_fe;
|
| 529 |
|
|
assign init_ack7 = spec_req_cs[7] & init_ack_fe;
|
| 530 |
|
|
|
| 531 |
|
|
////////////////////////////////////////////////////////////////////
|
| 532 |
|
|
//
|
| 533 |
|
|
// Modules
|
| 534 |
|
|
//
|
| 535 |
|
|
|
| 536 |
|
|
mc_cs_rf #(3'h0) u0(
|
| 537 |
|
|
.clk( clk ),
|
| 538 |
|
|
.rst( rst ),
|
| 539 |
|
|
.wb_we_i( wb_we_i ),
|
| 540 |
|
|
.din( wb_data_i ),
|
| 541 |
|
|
.rf_we( rf_we ),
|
| 542 |
|
|
.addr( wb_addr_i ),
|
| 543 |
|
|
.csc( csc0 ),
|
| 544 |
|
|
.tms( tms0 ),
|
| 545 |
|
|
.poc( poc ),
|
| 546 |
|
|
.csc_mask( csc_mask ),
|
| 547 |
|
|
.cs( cs0 ),
|
| 548 |
|
|
.wp_err( wp_err0 ),
|
| 549 |
|
|
.lmr_req( lmr_req0 ),
|
| 550 |
|
|
.lmr_ack( lmr_ack0 ),
|
| 551 |
|
|
.init_req( init_req0 ),
|
| 552 |
|
|
.init_ack( init_ack0 )
|
| 553 |
|
|
);
|
| 554 |
|
|
|
| 555 |
|
|
`ifdef MC_HAVE_CS1
|
| 556 |
|
|
mc_cs_rf #(3'h1) u1(
|
| 557 |
|
|
.clk( clk ),
|
| 558 |
|
|
.rst( rst ),
|
| 559 |
|
|
.wb_we_i( wb_we_i ),
|
| 560 |
|
|
.din( wb_data_i ),
|
| 561 |
|
|
.rf_we( rf_we ),
|
| 562 |
|
|
.addr( wb_addr_i ),
|
| 563 |
|
|
.csc( csc1 ),
|
| 564 |
|
|
.tms( tms1 ),
|
| 565 |
|
|
.poc( poc ),
|
| 566 |
|
|
.csc_mask( csc_mask ),
|
| 567 |
|
|
.cs( cs1 ),
|
| 568 |
|
|
.wp_err( wp_err1 ),
|
| 569 |
|
|
.lmr_req( lmr_req1 ),
|
| 570 |
|
|
.lmr_ack( lmr_ack1 ),
|
| 571 |
|
|
.init_req( init_req1 ),
|
| 572 |
|
|
.init_ack( init_ack1 )
|
| 573 |
|
|
);
|
| 574 |
|
|
`else
|
| 575 |
|
|
mc_cs_rf_dummy #(3'h1) u1(
|
| 576 |
|
|
.clk( clk ),
|
| 577 |
|
|
.rst( rst ),
|
| 578 |
|
|
.wb_we_i( wb_we_i ),
|
| 579 |
|
|
.din( wb_data_i ),
|
| 580 |
|
|
.rf_we( rf_we ),
|
| 581 |
|
|
.addr( wb_addr_i ),
|
| 582 |
|
|
.csc( csc1 ),
|
| 583 |
|
|
.tms( tms1 ),
|
| 584 |
|
|
.poc( poc ),
|
| 585 |
|
|
.csc_mask( csc_mask ),
|
| 586 |
|
|
.cs( cs1 ),
|
| 587 |
|
|
.wp_err( wp_err1 ),
|
| 588 |
|
|
.lmr_req( lmr_req1 ),
|
| 589 |
|
|
.lmr_ack( lmr_ack1 ),
|
| 590 |
|
|
.init_req( init_req1 ),
|
| 591 |
|
|
.init_ack( init_ack1 )
|
| 592 |
|
|
);
|
| 593 |
|
|
`endif
|
| 594 |
|
|
|
| 595 |
|
|
`ifdef MC_HAVE_CS2
|
| 596 |
|
|
mc_cs_rf #(3'h2) u2(
|
| 597 |
|
|
.clk( clk ),
|
| 598 |
|
|
.rst( rst ),
|
| 599 |
|
|
.wb_we_i( wb_we_i ),
|
| 600 |
|
|
.din( wb_data_i ),
|
| 601 |
|
|
.rf_we( rf_we ),
|
| 602 |
|
|
.addr( wb_addr_i ),
|
| 603 |
|
|
.csc( csc2 ),
|
| 604 |
|
|
.tms( tms2 ),
|
| 605 |
|
|
.poc( poc ),
|
| 606 |
|
|
.csc_mask( csc_mask ),
|
| 607 |
|
|
.cs( cs2 ),
|
| 608 |
|
|
.wp_err( wp_err2 ),
|
| 609 |
|
|
.lmr_req( lmr_req2 ),
|
| 610 |
|
|
.lmr_ack( lmr_ack2 ),
|
| 611 |
|
|
.init_req( init_req2 ),
|
| 612 |
|
|
.init_ack( init_ack2 )
|
| 613 |
|
|
);
|
| 614 |
|
|
`else
|
| 615 |
|
|
mc_cs_rf_dummy #(3'h2) u2(
|
| 616 |
|
|
.clk( clk ),
|
| 617 |
|
|
.rst( rst ),
|
| 618 |
|
|
.wb_we_i( wb_we_i ),
|
| 619 |
|
|
.din( wb_data_i ),
|
| 620 |
|
|
.rf_we( rf_we ),
|
| 621 |
|
|
.addr( wb_addr_i ),
|
| 622 |
|
|
.csc( csc2 ),
|
| 623 |
|
|
.tms( tms2 ),
|
| 624 |
|
|
.poc( poc ),
|
| 625 |
|
|
.csc_mask( csc_mask ),
|
| 626 |
|
|
.cs( cs2 ),
|
| 627 |
|
|
.wp_err( wp_err2 ),
|
| 628 |
|
|
.lmr_req( lmr_req2 ),
|
| 629 |
|
|
.lmr_ack( lmr_ack2 ),
|
| 630 |
|
|
.init_req( init_req2 ),
|
| 631 |
|
|
.init_ack( init_ack2 )
|
| 632 |
|
|
);
|
| 633 |
|
|
`endif
|
| 634 |
|
|
|
| 635 |
|
|
`ifdef MC_HAVE_CS3
|
| 636 |
|
|
mc_cs_rf #(3'h3) u3(
|
| 637 |
|
|
.clk( clk ),
|
| 638 |
|
|
.rst( rst ),
|
| 639 |
|
|
.wb_we_i( wb_we_i ),
|
| 640 |
|
|
.din( wb_data_i ),
|
| 641 |
|
|
.rf_we( rf_we ),
|
| 642 |
|
|
.addr( wb_addr_i ),
|
| 643 |
|
|
.csc( csc3 ),
|
| 644 |
|
|
.tms( tms3 ),
|
| 645 |
|
|
.poc( poc ),
|
| 646 |
|
|
.csc_mask( csc_mask ),
|
| 647 |
|
|
.cs( cs3 ),
|
| 648 |
|
|
.wp_err( wp_err3 ),
|
| 649 |
|
|
.lmr_req( lmr_req3 ),
|
| 650 |
|
|
.lmr_ack( lmr_ack3 ),
|
| 651 |
|
|
.init_req( init_req3 ),
|
| 652 |
|
|
.init_ack( init_ack3 )
|
| 653 |
|
|
);
|
| 654 |
|
|
`else
|
| 655 |
|
|
mc_cs_rf_dummy #(3'h3) u3(
|
| 656 |
|
|
.clk( clk ),
|
| 657 |
|
|
.rst( rst ),
|
| 658 |
|
|
.wb_we_i( wb_we_i ),
|
| 659 |
|
|
.din( wb_data_i ),
|
| 660 |
|
|
.rf_we( rf_we ),
|
| 661 |
|
|
.addr( wb_addr_i ),
|
| 662 |
|
|
.csc( csc3 ),
|
| 663 |
|
|
.tms( tms3 ),
|
| 664 |
|
|
.poc( poc ),
|
| 665 |
|
|
.csc_mask( csc_mask ),
|
| 666 |
|
|
.cs( cs3 ),
|
| 667 |
|
|
.wp_err( wp_err3 ),
|
| 668 |
|
|
.lmr_req( lmr_req3 ),
|
| 669 |
|
|
.lmr_ack( lmr_ack3 ),
|
| 670 |
|
|
.init_req( init_req3 ),
|
| 671 |
|
|
.init_ack( init_ack3 )
|
| 672 |
|
|
);
|
| 673 |
|
|
`endif
|
| 674 |
|
|
|
| 675 |
|
|
`ifdef MC_HAVE_CS4
|
| 676 |
|
|
mc_cs_rf #(3'h4) u4(
|
| 677 |
|
|
.clk( clk ),
|
| 678 |
|
|
.rst( rst ),
|
| 679 |
|
|
.wb_we_i( wb_we_i ),
|
| 680 |
|
|
.din( wb_data_i ),
|
| 681 |
|
|
.rf_we( rf_we ),
|
| 682 |
|
|
.addr( wb_addr_i ),
|
| 683 |
|
|
.csc( csc4 ),
|
| 684 |
|
|
.tms( tms4 ),
|
| 685 |
|
|
.poc( poc ),
|
| 686 |
|
|
.csc_mask( csc_mask ),
|
| 687 |
|
|
.cs( cs4 ),
|
| 688 |
|
|
.wp_err( wp_err4 ),
|
| 689 |
|
|
.lmr_req( lmr_req4 ),
|
| 690 |
|
|
.lmr_ack( lmr_ack4 ),
|
| 691 |
|
|
.init_req( init_req4 ),
|
| 692 |
|
|
.init_ack( init_ack4 )
|
| 693 |
|
|
);
|
| 694 |
|
|
`else
|
| 695 |
|
|
mc_cs_rf_dummy #(3'h4) u4(
|
| 696 |
|
|
.clk( clk ),
|
| 697 |
|
|
.rst( rst ),
|
| 698 |
|
|
.wb_we_i( wb_we_i ),
|
| 699 |
|
|
.din( wb_data_i ),
|
| 700 |
|
|
.rf_we( rf_we ),
|
| 701 |
|
|
.addr( wb_addr_i ),
|
| 702 |
|
|
.csc( csc4 ),
|
| 703 |
|
|
.tms( tms4 ),
|
| 704 |
|
|
.poc( poc ),
|
| 705 |
|
|
.csc_mask( csc_mask ),
|
| 706 |
|
|
.cs( cs4 ),
|
| 707 |
|
|
.wp_err( wp_err4 ),
|
| 708 |
|
|
.lmr_req( lmr_req4 ),
|
| 709 |
|
|
.lmr_ack( lmr_ack4 ),
|
| 710 |
|
|
.init_req( init_req4 ),
|
| 711 |
|
|
.init_ack( init_ack4 )
|
| 712 |
|
|
);
|
| 713 |
|
|
`endif
|
| 714 |
|
|
|
| 715 |
|
|
`ifdef MC_HAVE_CS5
|
| 716 |
|
|
mc_cs_rf #(3'h5) u5(
|
| 717 |
|
|
.clk( clk ),
|
| 718 |
|
|
.rst( rst ),
|
| 719 |
|
|
.wb_we_i( wb_we_i ),
|
| 720 |
|
|
.din( wb_data_i ),
|
| 721 |
|
|
.rf_we( rf_we ),
|
| 722 |
|
|
.addr( wb_addr_i ),
|
| 723 |
|
|
.csc( csc5 ),
|
| 724 |
|
|
.tms( tms5 ),
|
| 725 |
|
|
.poc( poc ),
|
| 726 |
|
|
.csc_mask( csc_mask ),
|
| 727 |
|
|
.cs( cs5 ),
|
| 728 |
|
|
.wp_err( wp_err5 ),
|
| 729 |
|
|
.lmr_req( lmr_req5 ),
|
| 730 |
|
|
.lmr_ack( lmr_ack5 ),
|
| 731 |
|
|
.init_req( init_req5 ),
|
| 732 |
|
|
.init_ack( init_ack5 )
|
| 733 |
|
|
);
|
| 734 |
|
|
`else
|
| 735 |
|
|
mc_cs_rf_dummy #(3'h5) u5(
|
| 736 |
|
|
.clk( clk ),
|
| 737 |
|
|
.rst( rst ),
|
| 738 |
|
|
.wb_we_i( wb_we_i ),
|
| 739 |
|
|
.din( wb_data_i ),
|
| 740 |
|
|
.rf_we( rf_we ),
|
| 741 |
|
|
.addr( wb_addr_i ),
|
| 742 |
|
|
.csc( csc5 ),
|
| 743 |
|
|
.tms( tms5 ),
|
| 744 |
|
|
.poc( poc ),
|
| 745 |
|
|
.csc_mask( csc_mask ),
|
| 746 |
|
|
.cs( cs5 ),
|
| 747 |
|
|
.wp_err( wp_err5 ),
|
| 748 |
|
|
.lmr_req( lmr_req5 ),
|
| 749 |
|
|
.lmr_ack( lmr_ack5 ),
|
| 750 |
|
|
.init_req( init_req5 ),
|
| 751 |
|
|
.init_ack( init_ack5 )
|
| 752 |
|
|
);
|
| 753 |
|
|
`endif
|
| 754 |
|
|
|
| 755 |
|
|
`ifdef MC_HAVE_CS6
|
| 756 |
|
|
mc_cs_rf #(3'h6) u6(
|
| 757 |
|
|
.clk( clk ),
|
| 758 |
|
|
.rst( rst ),
|
| 759 |
|
|
.wb_we_i( wb_we_i ),
|
| 760 |
|
|
.din( wb_data_i ),
|
| 761 |
|
|
.rf_we( rf_we ),
|
| 762 |
|
|
.addr( wb_addr_i ),
|
| 763 |
|
|
.csc( csc6 ),
|
| 764 |
|
|
.tms( tms6 ),
|
| 765 |
|
|
.poc( poc ),
|
| 766 |
|
|
.csc_mask( csc_mask ),
|
| 767 |
|
|
.cs( cs6 ),
|
| 768 |
|
|
.wp_err( wp_err6 ),
|
| 769 |
|
|
.lmr_req( lmr_req6 ),
|
| 770 |
|
|
.lmr_ack( lmr_ack6 ),
|
| 771 |
|
|
.init_req( init_req6 ),
|
| 772 |
|
|
.init_ack( init_ack6 )
|
| 773 |
|
|
);
|
| 774 |
|
|
`else
|
| 775 |
|
|
mc_cs_rf_dummy #(3'h6) u6(
|
| 776 |
|
|
.clk( clk ),
|
| 777 |
|
|
.rst( rst ),
|
| 778 |
|
|
.wb_we_i( wb_we_i ),
|
| 779 |
|
|
.din( wb_data_i ),
|
| 780 |
|
|
.rf_we( rf_we ),
|
| 781 |
|
|
.addr( wb_addr_i ),
|
| 782 |
|
|
.csc( csc6 ),
|
| 783 |
|
|
.tms( tms6 ),
|
| 784 |
|
|
.poc( poc ),
|
| 785 |
|
|
.csc_mask( csc_mask ),
|
| 786 |
|
|
.cs( cs6 ),
|
| 787 |
|
|
.wp_err( wp_err6 ),
|
| 788 |
|
|
.lmr_req( lmr_req6 ),
|
| 789 |
|
|
.lmr_ack( lmr_ack6 ),
|
| 790 |
|
|
.init_req( init_req6 ),
|
| 791 |
|
|
.init_ack( init_ack6 )
|
| 792 |
|
|
);
|
| 793 |
|
|
`endif
|
| 794 |
|
|
|
| 795 |
|
|
`ifdef MC_HAVE_CS7
|
| 796 |
|
|
mc_cs_rf #(3'h7) u7(
|
| 797 |
|
|
.clk( clk ),
|
| 798 |
|
|
.rst( rst ),
|
| 799 |
|
|
.wb_we_i( wb_we_i ),
|
| 800 |
|
|
.din( wb_data_i ),
|
| 801 |
|
|
.rf_we( rf_we ),
|
| 802 |
|
|
.addr( wb_addr_i ),
|
| 803 |
|
|
.csc( csc7 ),
|
| 804 |
|
|
.tms( tms7 ),
|
| 805 |
|
|
.poc( poc ),
|
| 806 |
|
|
.csc_mask( csc_mask ),
|
| 807 |
|
|
.cs( cs7 ),
|
| 808 |
|
|
.wp_err( wp_err7 ),
|
| 809 |
|
|
.lmr_req( lmr_req7 ),
|
| 810 |
|
|
.lmr_ack( lmr_ack7 ),
|
| 811 |
|
|
.init_req( init_req7 ),
|
| 812 |
|
|
.init_ack( init_ack7 )
|
| 813 |
|
|
);
|
| 814 |
|
|
`else
|
| 815 |
|
|
mc_cs_rf_dummy #(3'h7) u7(
|
| 816 |
|
|
.clk( clk ),
|
| 817 |
|
|
.rst( rst ),
|
| 818 |
|
|
.wb_we_i( wb_we_i ),
|
| 819 |
|
|
.din( wb_data_i ),
|
| 820 |
|
|
.rf_we( rf_we ),
|
| 821 |
|
|
.addr( wb_addr_i ),
|
| 822 |
|
|
.csc( csc7 ),
|
| 823 |
|
|
.tms( tms7 ),
|
| 824 |
|
|
.poc( poc ),
|
| 825 |
|
|
.csc_mask( csc_mask ),
|
| 826 |
|
|
.cs( cs7 ),
|
| 827 |
|
|
.wp_err( wp_err7 ),
|
| 828 |
|
|
.lmr_req( lmr_req7 ),
|
| 829 |
|
|
.lmr_ack( lmr_ack7 ),
|
| 830 |
|
|
.init_req( init_req7 ),
|
| 831 |
|
|
.init_ack( init_ack7 )
|
| 832 |
|
|
);
|
| 833 |
|
|
`endif
|
| 834 |
|
|
|
| 835 |
|
|
endmodule
|
| 836 |
|
|
|
