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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_wb_if.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  WISHBONE Interface                                         ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_wb_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $
//
//  $Date: 2002/01/21 13:08:52 $
//  $Revision: 1.6 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: mc_wb_if.v,v $
//               Revision 1.6  2002/01/21 13:08:52  rudi
//
//               Fixed several minor bugs, cleaned up the code further ...
//
//               Revision 1.5  2001/12/11 02:47:19  rudi
//
//               - Made some changes not to expect clock during reset ...
//
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/24 00:38:21  rudi
//
//               Changed Reset to be active high and async.
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//              Minor changes after running lint, and a small bug
//              fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_wb_if(clk, rst,
                wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
                wb_read_go, wb_write_go,
                wb_first, wb_wait, mem_ack, wr_hold,
                err, par_err, wp_err,
                wb_data_o, mem_dout, rf_dout);
 
input           clk, rst;
input   [31:0]   wb_addr_i;
input           wb_cyc_i;
input           wb_stb_i;
input           wb_we_i;
output          wb_err;
output          wb_ack_o;
output          wb_read_go;
output          wb_write_go;
output          wb_first;
output          wb_wait;
input           mem_ack;
output          wr_hold;
input           err, par_err, wp_err;
output  [31:0]   wb_data_o;
input   [31:0]   mem_dout, rf_dout;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
wire            mem_sel;
reg             read_go_r;
reg             read_go_r1;
reg             write_go_r;
reg             write_go_r1;
reg             wb_first_r;
wire            wb_first_set;
reg             wr_hold;
wire            rmw;
reg             rmw_r;
reg             rmw_en;
reg             wb_ack_o;
reg             wb_err;
reg     [31:0]   wb_data_o;
 
////////////////////////////////////////////////////////////////////
//
// Memory Go Logic
//
 
assign mem_sel = `MC_MEM_SEL;
 
always @(posedge clk or posedge rst)
        if(rst)                 rmw_en <= #1 1'b0;
        else
        if(wb_ack_o)            rmw_en <= #1 1'b1;
        else
        if(!wb_cyc_i)           rmw_en <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst) rmw_r <= #1 1'b0;
        else    rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
 
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
 
always @(posedge clk or posedge rst)
        if(rst) read_go_r1 <= #1 1'b0;
        else    read_go_r1 <= #1 !rmw & wb_cyc_i &
                                ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
 
always @(posedge clk or posedge rst)
        if(rst) read_go_r <= #1 1'b0;
        else    read_go_r <= #1 read_go_r1 & wb_cyc_i;
 
assign  wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
 
always @(posedge clk or posedge rst)
        if(rst) write_go_r1 <= #1 1'b0;
        else    write_go_r1 <= #1 wb_cyc_i &
                                ((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
 
always @(posedge clk or posedge rst)
        if(rst)         write_go_r <= #1 1'b0;
        else            write_go_r <= #1 write_go_r1 & wb_cyc_i &
                                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_write_go =    !rmw & write_go_r1 & wb_cyc_i &
                        ((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
 
always @(posedge clk or posedge rst)
        if(rst)                 wb_first_r <= #1 1'b0;
        else
        if(wb_first_set)        wb_first_r <= #1 1'b1;
        else
        if(wb_ack_o | wb_err)   wb_first_r <= #1 1'b0;
 
always @(posedge clk or posedge rst)
        if(rst)                 wr_hold <= #1 1'b0;
        else
        if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
 
////////////////////////////////////////////////////////////////////
//
// WB Ack
//
 
wire    wb_err_d;
 
// Ack no longer asserted when wb_err is asserted
always @(posedge clk or posedge rst)
        if(rst) wb_ack_o <= #1 1'b0;
        else    wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
                                `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err);
 
always @(posedge clk or posedge rst)
        if(rst) wb_err <= #1 1'b0;
        else    wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
 
////////////////////////////////////////////////////////////////////
//
// Memory Wait Logic
//
 
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Data Output
//
 
always @(posedge clk)
        wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
 
endmodule

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [mc/] [mc_wb_if.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// WISHBONE Interface ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42			`// $Id: mc_wb_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $`
43			`//`
44			`// $Date: 2002/01/21 13:08:52 $`
45			`// $Revision: 1.6 $`
46			`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: mc_wb_if.v,v $`
52			`// Revision 1.6 2002/01/21 13:08:52 rudi`
53			`//`
54			`// Fixed several minor bugs, cleaned up the code further ...`
55			`//`
56			`// Revision 1.5 2001/12/11 02:47:19 rudi`
57			`//`
58			`// - Made some changes not to expect clock during reset ...`
59			`//`
60			`// Revision 1.4 2001/11/29 02:16:28 rudi`
61			`//`
62			`//`
63			`// - More Synthesis cleanup, mostly for speed`
64			`// - Several bug fixes`
65			`// - Changed code to avoid auto-precharge and`
66			`// burst-terminate combinations (apparently illegal ?)`
67			`// Now we will do a manual precharge ...`
68			`//`
69			`// Revision 1.3 2001/09/24 00:38:21 rudi`
70			`//`
71			`// Changed Reset to be active high and async.`
72			`//`
73			`// Revision 1.2 2001/08/10 08:16:21 rudi`
74			`//`
75			`// - Changed IO names to be more clear.`
76			`// - Uniquifyed define names to be core specific.`
77			`// - Removed "Refresh Early" configuration`
78			`//`
79			`// Revision 1.1 2001/07/29 07:34:41 rudi`
80			`//`
81			`//`
82			`// 1) Changed Directory Structure`
83			`// 2) Fixed several minor bugs`
84			`//`
85			`// Revision 1.3 2001/06/12 15:19:49 rudi`
86			`//`
87			`//`
88			`// Minor changes after running lint, and a small bug`
89			`// fix reading csr and ba_mask registers.`
90			`//`
91			`// Revision 1.2 2001/06/03 11:37:17 rudi`
92			`//`
93			`//`
94			`// 1) Fixed Chip Select Mask Register`
95			`// - Power On Value is now all ones`
96			`// - Comparison Logic is now correct`
97			`//`
98			`// 2) All resets are now asynchronous`
99			`//`
100			`// 3) Converted Power On Delay to an configurable item`
101			`//`
102			`// 4) Added reset to Chip Select Output Registers`
103			`//`
104			`// 5) Forcing all outputs to Hi-Z state during reset`
105			`//`
106			`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
107			`// Created Directory Structure`
108			`//`
109			`//`
110			`//`
111			`//`
112
113			`include "mc_defines.v"
114
115			`module mc_wb_if(clk, rst,`
116			`wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,`
117			`wb_read_go, wb_write_go,`
118			`wb_first, wb_wait, mem_ack, wr_hold,`
119			`err, par_err, wp_err,`
120			`wb_data_o, mem_dout, rf_dout);`
121
122			`input clk, rst;`
123			`input [31:0] wb_addr_i;`
124			`input wb_cyc_i;`
125			`input wb_stb_i;`
126			`input wb_we_i;`
127			`output wb_err;`
128			`output wb_ack_o;`
129			`output wb_read_go;`
130			`output wb_write_go;`
131			`output wb_first;`
132			`output wb_wait;`
133			`input mem_ack;`
134			`output wr_hold;`
135			`input err, par_err, wp_err;`
136			`output [31:0] wb_data_o;`
137			`input [31:0] mem_dout, rf_dout;`
138
139			`////////////////////////////////////////////////////////////////////`
140			`//`
141			`// Local Wires and Registers`
142			`//`
143
144			`wire mem_sel;`
145			`reg read_go_r;`
146			`reg read_go_r1;`
147			`reg write_go_r;`
148			`reg write_go_r1;`
149			`reg wb_first_r;`
150			`wire wb_first_set;`
151			`reg wr_hold;`
152			`wire rmw;`
153			`reg rmw_r;`
154			`reg rmw_en;`
155			`reg wb_ack_o;`
156			`reg wb_err;`
157			`reg [31:0] wb_data_o;`
158
159			`////////////////////////////////////////////////////////////////////`
160			`//`
161			`// Memory Go Logic`
162			`//`
163
164			assign mem_sel = `MC_MEM_SEL;
165
166			`always @(posedge clk or posedge rst)`
167			`if(rst) rmw_en <= #1 1'b0;`
168			`else`
169			`if(wb_ack_o) rmw_en <= #1 1'b1;`
170			`else`
171			`if(!wb_cyc_i) rmw_en <= #1 1'b0;`
172
173			`always @(posedge clk or posedge rst)`
174			`if(rst) rmw_r <= #1 1'b0;`
175			`else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;`
176
177			`assign rmw = rmw_r \| (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);`
178
179			`always @(posedge clk or posedge rst)`
180			`if(rst) read_go_r1 <= #1 1'b0;`
181			`else read_go_r1 <= #1 !rmw & wb_cyc_i &`
182			`((wb_stb_i & mem_sel & !wb_we_i) \| read_go_r);`
183
184			`always @(posedge clk or posedge rst)`
185			`if(rst) read_go_r <= #1 1'b0;`
186			`else read_go_r <= #1 read_go_r1 & wb_cyc_i;`
187
188			`assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;`
189
190			`always @(posedge clk or posedge rst)`
191			`if(rst) write_go_r1 <= #1 1'b0;`
192			`else write_go_r1 <= #1 wb_cyc_i &`
193			`((wb_stb_i & mem_sel & wb_we_i) \| write_go_r);`
194
195			`always @(posedge clk or posedge rst)`
196			`if(rst) write_go_r <= #1 1'b0;`
197			`else write_go_r <= #1 write_go_r1 & wb_cyc_i &`
198			`((wb_we_i & wb_stb_i) \| !wb_stb_i);`
199
200			`assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &`
201			`((wb_we_i & wb_stb_i) \| !wb_stb_i);`
202
203			`assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r \| write_go_r);`
204			`assign wb_first = wb_first_set \| (wb_first_r & !wb_ack_o & !wb_err);`
205
206			`always @(posedge clk or posedge rst)`
207			`if(rst) wb_first_r <= #1 1'b0;`
208			`else`
209			`if(wb_first_set) wb_first_r <= #1 1'b1;`
210			`else`
211			`if(wb_ack_o \| wb_err) wb_first_r <= #1 1'b0;`
212
213			`always @(posedge clk or posedge rst)`
214			`if(rst) wr_hold <= #1 1'b0;`
215			`else`
216			`if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;`
217
218			`////////////////////////////////////////////////////////////////////`
219			`//`
220			`// WB Ack`
221			`//`
222
223			`wire wb_err_d;`
224
225			`// Ack no longer asserted when wb_err is asserted`
226			`always @(posedge clk or posedge rst)`
227			`if(rst) wb_ack_o <= #1 1'b0;`
228			else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
229			`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
230
231			`assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err \| err \| wp_err);`
232
233			`always @(posedge clk or posedge rst)`
234			`if(rst) wb_err <= #1 1'b0;`
235			else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
236
237			`////////////////////////////////////////////////////////////////////`
238			`//`
239			`// Memory Wait Logic`
240			`//`
241
242			`assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go \| wb_read_go);`
243
244			`////////////////////////////////////////////////////////////////////`
245			`//`
246			`// WISHBONE Data Output`
247			`//`
248
249			`always @(posedge clk)`
250			wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
251
252			`endmodule`