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///////////////////////////////////////////////////////////////////////
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//// ////
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//// xilinx_internal_jtag.v ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// //
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// This file is a wrapper for the various Xilinx internal BSCAN //
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// TAP devices. It is designed to take the place of a separate TAP //
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// controller in Xilinx systems, to allow a user to access a CPU //
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// debug module (such as that of the OR1200) through the FPGA's //
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// dedicated JTAG / configuration port. //
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// //
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: xilinx_internal_jtag.v,v $
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// Revision 1.3 2009/06/16 02:54:23 Nathan
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// Changed some signal names for better consistency between different hardware modules.
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//
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// Revision 1.2 2009/05/17 20:54:16 Nathan
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// Changed email address to opencores.org
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//
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// Revision 1.1 2008/07/18 20:07:32 Nathan
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// Changed the directory structure to match existing projects.
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//
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// Revision 1.4 2008/07/11 08:26:10 Nathan
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// Ran through dos2unix
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//
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// Revision 1.3 2008/07/11 08:25:52 Nathan
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// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4.
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//
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// Revision 1.2 2008/06/09 19:34:14 Nathan
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// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools.
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//
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// Revision 1.1 2008/05/22 19:54:07 Nathan
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// Initial version
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//
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`include "minsoc_defines.v"
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// Note that the SPARTAN BSCAN controllers have more than one channel.
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// This implementation always uses channel 1, this is not configurable.
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// If you want to use another channel, then it is probably because you
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// want to attach multiple devices to the BSCAN device, which means
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// you'll be making changes to this file anyway.
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// Virtex BSCAN devices are instantiated separately for each channel.
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// To select something other than the default (1), change the parameter
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// "virtex_jtag_chain".
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module minsoc_xilinx_internal_jtag (
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tck_o,
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debug_tdo_i,
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tdi_o,
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test_logic_reset_o,
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run_test_idle_o,
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shift_dr_o,
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capture_dr_o,
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pause_dr_o,
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update_dr_o,
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debug_select_o
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);
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// May be 1, 2, 3, or 4
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// Only used for Virtex 4/5 devices
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parameter virtex_jtag_chain = 1;
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input debug_tdo_i;
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output tck_o;
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output tdi_o;
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output test_logic_reset_o;
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output run_test_idle_o;
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output shift_dr_o;
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output capture_dr_o;
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output pause_dr_o;
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output update_dr_o;
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output debug_select_o;
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wire debug_tdo_i;
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wire tck_o;
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wire drck;
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wire tdi_o;
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wire test_logic_reset_o;
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wire run_test_idle_o;
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wire shift_dr_o;
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wire pause_dr_o;
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wire update_dr_o;
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wire debug_select_o;
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`ifdef SPARTAN3E
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`define SPARTAN3
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`endif
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`ifdef SPARTAN2
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// Note that this version is missing three outputs.
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// It also does not have a real TCK...DRCK1 is only active when USER1 is selected
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// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no
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// capture_dr output.
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reg capture_dr_o;
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wire update_bscan;
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reg update_out;
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BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
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.DRCK1(drck), // Data register output for USER1 functions
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.DRCK2(), // Data register output for USER2 functions
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.RESET(test_logic_reset_o), // Reset output from TAP controller
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.SEL1(debug_select_o), // USER1 active output
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.SEL2(), // USER2 active output
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.SHIFT(shift_dr_o), // SHIFT output from TAP controller
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.TDI(tdi_o), // TDI output from TAP controller
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.UPDATE(update_bscan), // UPDATE output from TAP controller
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.TDO1(debug_tdo_i), // Data input for USER1 function
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.TDO2( 1'b0 ) // Data input for USER2 function
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);
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assign pause_dr_o = 1'b0;
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assign run_test_idle_o = 1'b0;
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// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
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// On that negative edge, set capture_dr, and it will get registered on the rising
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// edge.
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always @ (negedge tck_o)
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begin
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if(debug_select_o && !shift_dr_o)
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capture_dr_o <= 1'b1;
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else
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capture_dr_o <= 1'b0;
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end
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// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
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// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
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// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
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assign tck_o = (drck & debug_select_o & !update_bscan);
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// This will hold the update_dr output so it can be registered on the rising edge
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// of the clock created above.
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always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
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begin
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if(update_bscan) update_out <= 1'b1;
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else if(capture_dr_o) update_out <= 1'b0;
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else if(!debug_select_o) update_out <= 1'b0;
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end
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assign update_dr_o = update_out;
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`else
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`ifdef SPARTAN3
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// Note that this version is missing two outputs.
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// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
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wire capture_dr_o;
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wire update_bscan;
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reg update_out;
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BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
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.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
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.DRCK1(drck), // Data register output for USER1 functions
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.DRCK2(), // Data register output for USER2 functions
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.RESET(test_logic_reset_o), // Reset output from TAP controller
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.SEL1(debug_select_o), // USER1 active output
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.SEL2(), // USER2 active output
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.SHIFT(shift_dr_o), // SHIFT output from TAP controller
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.TDI(tdi_o), // TDI output from TAP controller
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.UPDATE(update_bscan), // UPDATE output from TAP controller
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.TDO1(debug_tdo_i), // Data input for USER1 function
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.TDO2(1'b0) // Data input for USER2 function
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);
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assign pause_dr_o = 1'b0;
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assign run_test_idle_o = 1'b0;
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// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
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// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
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// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
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assign tck_o = (drck & debug_select_o & !update_bscan);
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// This will hold the update_dr output so it can be registered on the rising edge
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// of the clock created above.
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always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
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begin
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if(update_bscan) update_out <= 1'b1;
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else if(capture_dr_o) update_out <= 1'b0;
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else if(!debug_select_o) update_out <= 1'b0;
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end
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assign update_dr_o = update_out;
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`ifdef SPARTAN3E
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`undef SPARTAN3
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`endif
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`else
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`ifdef SPARTAN3A
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// Note that this version is missing two outputs.
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// At least it has a real TCK.
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wire capture_dr_o;
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BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
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.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
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.DRCK1(), // Data register output for USER1 functions
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.DRCK2(), // Data register output for USER2 functions
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.RESET(test_logic_reset_o), // Reset output from TAP controller
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.SEL1(debug_select_o), // USER1 active output
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.SEL2(), // USER2 active output
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.SHIFT(shift_dr_o), // SHIFT output from TAP controller
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.TCK(tck_o), // TCK output from TAP controller
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.TDI(tdi_o), // TDI output from TAP controller
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.TMS(), // TMS output from TAP controller
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.UPDATE(update_dr_o), // UPDATE output from TAP controller
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.TDO1(debug_tdo_i), // Data input for USER1 function
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.TDO2( 1'b0) // Data input for USER2 function
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);
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assign pause_dr_o = 1'b0;
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assign run_test_idle_o = 1'b0;
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`else
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`ifdef VIRTEX
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// Note that this version is missing three outputs.
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// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
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reg capture_dr_o;
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wire update_bscan;
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reg update_out;
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BSCAN_VIRTEX BSCAN_VIRTEX_inst (
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.DRCK1(drck), // Data register output for USER1 functions
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.DRCK2(), // Data register output for USER2 functions
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.RESET(test_logic_reset_o), // Reset output from TAP controller
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268 |
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.SEL1(debug_select_o), // USER1 active output
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269 |
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.SEL2(), // USER2 active output
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270 |
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.SHIFT(shift_dr_o), // SHIFT output from TAP controller
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271 |
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.TDI(tdi_o), // TDI output from TAP controller
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272 |
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.UPDATE(update_bscan), // UPDATE output from TAP controller
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273 |
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.TDO1(debug_tdo_i), // Data input for USER1 function
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274 |
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.TDO2( 1'b0) // Data input for USER2 function
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275 |
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);
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276 |
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277 |
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assign pause_dr_o = 1'b0;
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278 |
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assign run_test_idle_o = 1'b0;
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279 |
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280 |
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// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low)
|
281 |
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// On that negative edge, set capture_dr, and it will get registered on the rising
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282 |
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// edge, then de-asserted on the same edge that SHIFT goes high.
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283 |
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always @ (negedge tck_o)
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284 |
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begin
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285 |
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if(debug_select_o && !shift_dr_o)
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286 |
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capture_dr_o <= 1'b1;
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287 |
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else
|
288 |
|
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capture_dr_o <= 1'b0;
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289 |
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end
|
290 |
|
|
|
291 |
|
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// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
292 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
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293 |
|
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// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
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294 |
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assign tck_o = (drck & debug_select_o & !update_bscan);
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295 |
|
|
|
296 |
|
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// This will hold the update_dr output so it can be registered on the rising edge
|
297 |
|
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// of the clock created above.
|
298 |
|
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always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
299 |
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begin
|
300 |
|
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if(update_bscan) update_out <= 1'b1;
|
301 |
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else if(capture_dr_o) update_out <= 1'b0;
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302 |
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else if(!debug_select_o) update_out <= 1'b0;
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303 |
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end
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304 |
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305 |
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assign update_dr_o = update_out;
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306 |
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|
307 |
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`else
|
308 |
|
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`ifdef VIRTEX2
|
309 |
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|
310 |
|
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// Note that this version is missing two outputs.
|
311 |
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// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
|
312 |
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|
313 |
|
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wire capture_dr_o;
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314 |
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wire update_bscan;
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315 |
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reg update_out;
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316 |
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317 |
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BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
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318 |
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.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
319 |
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.DRCK1(drck), // Data register output for USER1 functions
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320 |
|
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.DRCK2(), // Data register output for USER2 functions
|
321 |
|
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.RESET(test_logic_reset_o), // Reset output from TAP controller
|
322 |
|
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.SEL1(debug_select_o), // USER1 active output
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323 |
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.SEL2(), // USER2 active output
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324 |
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.SHIFT(shift_dr_o), // SHIFT output from TAP controller
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325 |
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.TDI(tdi_o), // TDI output from TAP controller
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326 |
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.UPDATE(update_bscan), // UPDATE output from TAP controller
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327 |
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.TDO1(debug_tdo_i), // Data input for USER1 function
|
328 |
|
|
.TDO2( 1'b0 ) // Data input for USER2 function
|
329 |
|
|
);
|
330 |
|
|
|
331 |
|
|
assign pause_dr_o = 1'b0;
|
332 |
|
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assign run_test_idle_o = 1'b0;
|
333 |
|
|
|
334 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
335 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
336 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
337 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
338 |
|
|
|
339 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
340 |
|
|
// of the clock created above.
|
341 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
342 |
|
|
begin
|
343 |
|
|
if(update_bscan) update_out <= 1'b1;
|
344 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
345 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
346 |
|
|
end
|
347 |
|
|
|
348 |
|
|
assign update_dr_o = update_out;
|
349 |
|
|
|
350 |
|
|
`else
|
351 |
|
|
`ifdef VIRTEX4
|
352 |
|
|
// Note that this version is missing two outputs.
|
353 |
|
|
// It also does not have a real TCK...DRCK is only active when USERn is selected.
|
354 |
|
|
|
355 |
|
|
wire capture_dr_o;
|
356 |
|
|
wire update_bscan;
|
357 |
|
|
reg update_out;
|
358 |
|
|
|
359 |
|
|
BSCAN_VIRTEX4 #(
|
360 |
|
|
.JTAG_CHAIN(virtex_jtag_chain)
|
361 |
|
|
) BSCAN_VIRTEX4_inst (
|
362 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
363 |
|
|
.DRCK(drck), // Data register output for USER function
|
364 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
365 |
|
|
.SEL(debug_select_o), // USER active output
|
366 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
367 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
368 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
369 |
|
|
.TDO( debug_tdo_i ) // Data input for USER function
|
370 |
|
|
);
|
371 |
|
|
|
372 |
|
|
assign pause_dr_o = 1'b0;
|
373 |
|
|
assign run_test_idle_o = 1'b0;
|
374 |
|
|
|
375 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
376 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
377 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
378 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
379 |
|
|
|
380 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
381 |
|
|
// of the clock created above.
|
382 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
383 |
|
|
begin
|
384 |
|
|
if(update_bscan) update_out <= 1'b1;
|
385 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
386 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
387 |
|
|
end
|
388 |
|
|
|
389 |
|
|
assign update_dr_o = update_out;
|
390 |
|
|
|
391 |
|
|
`else
|
392 |
|
|
`ifdef VIRTEX5
|
393 |
|
|
// Note that this version is missing two outputs.
|
394 |
|
|
// It also does not have a real TCK...DRCK is only active when USERn is selected.
|
395 |
|
|
|
396 |
|
|
wire capture_dr_o;
|
397 |
|
|
wire update_bscan;
|
398 |
|
|
reg update_out;
|
399 |
|
|
|
400 |
|
|
BSCAN_VIRTEX5 #(
|
401 |
|
|
.JTAG_CHAIN(virtex_jtag_chain)
|
402 |
|
|
) BSCAN_VIRTEX5_inst (
|
403 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
404 |
|
|
.DRCK(drck), // Data register output for USER function
|
405 |
|
|
.RESET(test_logic_reset), // Reset output from TAP controller
|
406 |
|
|
.SEL(debug_select_o), // USER active output
|
407 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
408 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
409 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
410 |
|
|
.TDO(debug_tdo_i) // Data input for USER function
|
411 |
|
|
);
|
412 |
|
|
|
413 |
|
|
assign pause_dr_o = 1'b0;
|
414 |
|
|
assign run_test_idle_o = 1'b0;
|
415 |
|
|
|
416 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
417 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
418 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
419 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
420 |
|
|
|
421 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
422 |
|
|
// of the clock created above.
|
423 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
424 |
|
|
begin
|
425 |
|
|
if(update_bscan) update_out <= 1'b1;
|
426 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
427 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
428 |
|
|
end
|
429 |
|
|
|
430 |
|
|
assign update_dr_o = update_out;
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
`endif
|
434 |
|
|
`endif
|
435 |
|
|
`endif
|
436 |
|
|
`endif
|
437 |
|
|
`endif
|
438 |
|
|
`endif
|
439 |
|
|
`endif
|
440 |
|
|
|
441 |
|
|
endmodule
|