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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [pll/] [pll1_waveforms.html] - Blame information for rev 7

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<html>
<head>
<title>Sample Waveforms for pll1.v </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file pll1.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll1.v. The design pll1.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
<CENTER><img src=pll1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>

Line No.	Rev	Author	Line
1	7	parrado	`<html>`
2			`<head>`
3			`<title>Sample Waveforms for pll1.v </title>`
4			`</head>`
5			`<body>`
6			`<h2><CENTER>Sample behavioral waveforms for design file pll1.v </CENTER></h2>`
7			`<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll1.v. The design pll1.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>`
8			`<CENTER><img src=pll1_wave0.jpg> </CENTER>`
9			`<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>`
10			`<P><FONT size=3></P>`
11			`<P></P>`
12			`</body>`
13			`</html>`

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Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [pll/] [pll1_waveforms.html] - Blame information for rev 7