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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 7

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1.1.1 2001-10-19 11:04:23 rudi Exp $
//
//  $Date: 2001-10-19 11:04:23 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   mem[mem_size:0];
integer         cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
cnt = 0;
cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
adr = $random;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
adr = $random;
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        //adr = 32'hxxxx_xxxx;
        adr = $random;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
cnt = cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cnt = cnt + wcount;
stb=0;
repeat(delay)   @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
cnt = cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
 
cyc = 0;
stb = 0;
we  = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
adr = $random;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = $random;
end
endtask
 
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        //adr = 32'hxxxx_xxxx;
        adr = $random;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hffff_ffff;
//adr = 32'hxxxx_xxxx;
adr = $random;
 
cnt = cnt + count;
end
endtask
 
endmodule

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Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2000 Rudolf Usselmann ////`
13			`//// rudi@asics.ws ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer.////`
19			`//// ////`
20			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
21			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
22			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
23			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
24			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
25			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
26			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
27			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
28			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
29			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
30			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
31			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
32			`//// POSSIBILITY OF SUCH DAMAGE. ////`
33			`//// ////`
34			`/////////////////////////////////////////////////////////////////////`
35
36			`// CVS Log`
37			`//`
38			`// $Id: wb_mast_model.v,v 1.1.1.1 2001-10-19 11:04:23 rudi Exp $`
39			`//`
40			`// $Date: 2001-10-19 11:04:23 $`
41			`// $Revision: 1.1.1.1 $`
42			`// $Author: rudi $`
43			`// $Locker: $`
44			`// $State: Exp $`
45			`//`
46			`// Change History:`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49			`//`
50			`//`
51			`//`
52
53			`include "wb_model_defines.v"
54
55			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
56
57			`input clk, rst;`
58			`output [31:0] adr;`
59			`input [31:0] din;`
60			`output [31:0] dout;`
61			`output cyc, stb;`
62			`output [3:0] sel;`
63			`output we;`
64			`input ack, err, rty;`
65
66			`////////////////////////////////////////////////////////////////////`
67			`//`
68			`// Local Wires`
69			`//`
70
71			`parameter mem_size = 4096;`
72
73			`reg [31:0] adr;`
74			`reg [31:0] dout;`
75			`reg cyc, stb;`
76			`reg [3:0] sel;`
77			`reg we;`
78
79			`reg [31:0] mem[mem_size:0];`
80			`integer cnt;`
81
82			`////////////////////////////////////////////////////////////////////`
83			`//`
84			`// Memory Logic`
85			`//`
86
87			`initial`
88			`begin`
89			`//adr = 32'hxxxx_xxxx;`
90			`//adr = 0;`
91			`adr = 32'hffff_ffff;`
92			`dout = 32'hxxxx_xxxx;`
93			`cyc = 0;`
94			`stb = 0;`
95			`sel = 4'hx;`
96			`we = 1'hx;`
97			`cnt = 0;`
98			`#1;`
99			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
100			`end`
101
102
103
104			`task mem_fill;`
105
106			`integer n;`
107			`begin`
108			`cnt = 0;`
109			`cnt = 0;`
110			`for(n=0;n<mem_size;n=n+1)`
111			`begin`
112			`mem[n] = $random;`
113			`end`
114			`end`
115			`endtask`
116
117			`////////////////////////////////////////////////////////////////////`
118			`//`
119			`// Write 1 Word Task`
120			`//`
121
122			`task wb_wr1;`
123			`input [31:0] a;`
124			`input [3:0] s;`
125			`input [31:0] d;`
126
127			`begin`
128
129			`//@(posedge clk);`
130			`#1;`
131			`adr = a;`
132			`dout = d;`
133			`cyc = 1;`
134			`stb = 1;`
135			`we=1;`
136			`sel = s;`
137
138			`@(posedge clk);`
139			`while(~ack & ~err) @(posedge clk);`
140			`#1;`
141			`cyc=0;`
142			`stb=0;`
143			`adr = 32'hxxxx_xxxx;`
144			`//adr = 32'hffff_ffff;`
145			`//adr = 0;`
146			`dout = 32'hxxxx_xxxx;`
147			`we = 1'hx;`
148			`sel = 4'hx;`
149			`adr = $random;`
150
151			`end`
152			`endtask`
153
154			`////////////////////////////////////////////////////////////////////`
155			`//`
156			`// Write 4 Words Task`
157			`//`
158
159			`task wb_wr4;`
160			`input [31:0] a;`
161			`input [3:0] s;`
162			`input delay;`
163			`input [31:0] d1;`
164			`input [31:0] d2;`
165			`input [31:0] d3;`
166			`input [31:0] d4;`
167
168			`integer delay;`
169
170			`begin`
171
172			`@(posedge clk);`
173			`#1;`
174			`cyc = 1;`
175			`sel = s;`
176
177			`adr = $random;`
178			`repeat(delay)`
179			`begin`
180			`@(posedge clk);`
181			`#1;`
182			`end`
183			`adr = a;`
184			`dout = d1;`
185			`stb = 1;`
186			`we=1;`
187			`while(~ack & ~err) @(posedge clk);`
188			`#2;`
189			`stb=0;`
190			`we=1'bx;`
191			`dout = 32'hxxxx_xxxx;`
192			`adr = $random;`
193
194
195			`repeat(delay)`
196			`begin`
197			`@(posedge clk);`
198			`#1;`
199			`end`
200			`stb=1;`
201			`adr = a+4;`
202			`dout = d2;`
203			`we=1;`
204			`@(posedge clk);`
205			`while(~ack & ~err) @(posedge clk);`
206			`#2;`
207			`stb=0;`
208			`we=1'bx;`
209			`dout = 32'hxxxx_xxxx;`
210
211			`repeat(delay)`
212			`begin`
213			`@(posedge clk);`
214			`#1;`
215			`end`
216			`stb=1;`
217			`adr = a+8;`
218			`dout = d3;`
219			`we=1;`
220			`@(posedge clk);`
221			`while(~ack & ~err) @(posedge clk);`
222			`#2;`
223			`stb=0;`
224			`we=1'bx;`
225			`dout = 32'hxxxx_xxxx;`
226			`adr = $random;`
227
228			`repeat(delay)`
229			`begin`
230			`@(posedge clk);`
231			`#1;`
232			`end`
233			`stb=1;`
234			`adr = a+12;`
235			`dout = d4;`
236			`we=1;`
237			`@(posedge clk);`
238			`while(~ack & ~err) @(posedge clk);`
239			`#1;`
240			`stb=0;`
241			`cyc=0;`
242
243			`adr = 32'hxxxx_xxxx;`
244			`adr = $random;`
245			`//adr = 0;`
246			`//adr = 32'hffff_ffff;`
247			`dout = 32'hxxxx_xxxx;`
248			`we = 1'hx;`
249			`sel = 4'hx;`
250
251			`end`
252			`endtask`
253
254
255			`task wb_wr_mult;`
256			`input [31:0] a;`
257			`input [3:0] s;`
258			`input delay;`
259			`input count;`
260
261			`integer delay;`
262			`integer count;`
263			`integer n;`
264
265			`begin`
266
267			`//@(posedge clk);`
268			`#1;`
269			`cyc = 1;`
270			`adr = $random;`
271			`for(n=0;n<count;n=n+1)`
272			`begin`
273			`repeat(delay)`
274			`begin`
275			`@(posedge clk);`
276			`#1;`
277			`end`
278			`adr = a + (n*4);`
279			`dout = mem[n + cnt];`
280			`stb = 1;`
281			`we=1;`
282			`sel = s;`
283			`if(n!=0) @(posedge clk);`
284			`while(~ack & ~err) @(posedge clk);`
285			`#2;`
286			`stb=0;`
287			`we=1'bx;`
288			`sel = 4'hx;`
289			`dout = 32'hxxxx_xxxx;`
290			`//adr = 32'hxxxx_xxxx;`
291			`adr = $random;`
292			`end`
293
294			`cyc=0;`
295
296			`adr = 32'hxxxx_xxxx;`
297			`//adr = 32'hffff_ffff;`
298
299			`cnt = cnt + count;`
300			`end`
301			`endtask`
302
303
304			`task wb_rmw;`
305			`input [31:0] a;`
306			`input [3:0] s;`
307			`input delay;`
308			`input rcount;`
309			`input wcount;`
310
311			`integer delay;`
312			`integer rcount;`
313			`integer wcount;`
314			`integer n;`
315
316			`begin`
317
318			`@(posedge clk);`
319			`#1;`
320			`cyc = 1;`
321			`we = 0;`
322			`sel = s;`
323			`repeat(delay) @(posedge clk);`
324
325			`for(n=0;n<rcount-1;n=n+1)`
326			`begin`
327			`adr = a + (n*4);`
328			`stb = 1;`
329			`while(~ack & ~err) @(posedge clk);`
330			`mem[n + cnt] = din;`
331			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
332			`#2;`
333			`stb=0;`
334			`we = 1'hx;`
335			`sel = 4'hx;`
336			`adr = 32'hxxxx_xxxx;`
337			`repeat(delay)`
338			`begin`
339			`@(posedge clk);`
340			`#1;`
341			`end`
342			`we = 0;`
343			`sel = s;`
344			`end`
345
346			`adr = a+(n*4);`
347			`stb = 1;`
348			`@(posedge clk);`
349			`while(~ack & ~err) @(posedge clk);`
350			`mem[n + cnt] = din;`
351			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
352			`#1;`
353			`stb=0;`
354			`we = 1'hx;`
355			`sel = 4'hx;`
356			`adr = 32'hxxxx_xxxx;`
357
358			`cnt = cnt + rcount;`
359
360			`//@(posedge clk);`
361
362
363			`for(n=0;n<wcount;n=n+1)`
364			`begin`
365			`repeat(delay)`
366			`begin`
367			`@(posedge clk);`
368			`#1;`
369			`end`
370			`adr = a + (n*4);`
371			`dout = mem[n + cnt];`
372			`stb = 1;`
373			`we=1;`
374			`sel = s;`
375			`// if(n!=0)`
376			`@(posedge clk);`
377			`while(~ack & ~err) @(posedge clk);`
378			`#2;`
379			`stb=0;`
380			`we=1'bx;`
381			`sel = 4'hx;`
382			`dout = 32'hxxxx_xxxx;`
383			`adr = 32'hxxxx_xxxx;`
384			`end`
385
386			`cyc=0;`
387
388			`adr = 32'hxxxx_xxxx;`
389			`//adr = 32'hffff_ffff;`
390
391			`cnt = cnt + wcount;`
392			`end`
393			`endtask`
394
395
396
397
398			`task wb_wmr;`
399			`input [31:0] a;`
400			`input [3:0] s;`
401			`input delay;`
402			`input rcount;`
403			`input wcount;`
404
405			`integer delay;`
406			`integer rcount;`
407			`integer wcount;`
408			`integer n;`
409
410			`begin`
411
412			`@(posedge clk);`
413			`#1;`
414			`cyc = 1;`
415			`we = 1'bx;`
416			`sel = 4'hx;`
417			`sel = s;`
418
419			`for(n=0;n<wcount;n=n+1)`
420			`begin`
421			`repeat(delay)`
422			`begin`
423			`@(posedge clk);`
424			`#1;`
425			`end`
426			`adr = a + (n*4);`
427			`dout = mem[n + cnt];`
428			`stb = 1;`
429			`we=1;`
430			`sel = s;`
431			`@(posedge clk);`
432			`while(~ack & ~err) @(posedge clk);`
433			`#2;`
434			`stb=0;`
435			`we=1'bx;`
436			`sel = 4'hx;`
437			`dout = 32'hxxxx_xxxx;`
438			`adr = 32'hxxxx_xxxx;`
439			`end`
440
441			`cnt = cnt + wcount;`
442			`stb=0;`
443			`repeat(delay) @(posedge clk);`
444			`#1;`
445
446			`sel = s;`
447			`we = 0;`
448			`for(n=0;n<rcount-1;n=n+1)`
449			`begin`
450			`adr = a + (n*4);`
451			`stb = 1;`
452			`while(~ack & ~err) @(posedge clk);`
453			`mem[n + cnt] = din;`
454			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
455			`#2;`
456			`stb=0;`
457			`we = 1'hx;`
458			`sel = 4'hx;`
459			`adr = 32'hxxxx_xxxx;`
460			`repeat(delay)`
461			`begin`
462			`@(posedge clk);`
463			`#1;`
464			`end`
465			`we = 0;`
466			`sel = s;`
467			`end`
468
469			`adr = a+(n*4);`
470			`stb = 1;`
471			`@(posedge clk);`
472			`while(~ack & ~err) @(posedge clk);`
473			`mem[n + cnt] = din;`
474			`cnt = cnt + rcount;`
475			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
476			`#1;`
477
478			`cyc = 0;`
479			`stb = 0;`
480			`we = 1'hx;`
481			`sel = 4'hx;`
482			`adr = 32'hxxxx_xxxx;`
483
484			`end`
485			`endtask`
486
487
488
489
490			`////////////////////////////////////////////////////////////////////`
491			`//`
492			`// Read 1 Word Task`
493			`//`
494
495			`task wb_rd1;`
496			`input [31:0] a;`
497			`input [3:0] s;`
498			`output [31:0] d;`
499
500			`begin`
501
502			`//@(posedge clk);`
503			`#1;`
504			`adr = a;`
505			`cyc = 1;`
506			`stb = 1;`
507			`we = 0;`
508			`sel = s;`
509
510			`//@(posedge clk);`
511			`while(~ack & ~err) @(posedge clk);`
512			`d = din;`
513			`#1;`
514			`cyc=0;`
515			`stb=0;`
516			`//adr = 32'hxxxx_xxxx;`
517			`//adr = 0;`
518			`adr = 32'hffff_ffff;`
519			`dout = 32'hxxxx_xxxx;`
520			`we = 1'hx;`
521			`sel = 4'hx;`
522			`adr = $random;`
523
524			`end`
525			`endtask`
526
527
528			`////////////////////////////////////////////////////////////////////`
529			`//`
530			`// Read 4 Words Task`
531			`//`
532
533
534			`task wb_rd4;`
535			`input [31:0] a;`
536			`input [3:0] s;`
537			`input delay;`
538			`output [31:0] d1;`
539			`output [31:0] d2;`
540			`output [31:0] d3;`
541			`output [31:0] d4;`
542
543			`integer delay;`
544			`begin`
545
546			`@(posedge clk);`
547			`#1;`
548			`cyc = 1;`
549			`we = 0;`
550			`adr = $random;`
551			`sel = s;`
552			`repeat(delay) @(posedge clk);`
553
554			`adr = a;`
555			`stb = 1;`
556			`while(~ack & ~err) @(posedge clk);`
557			`d1 = din;`
558			`#2;`
559			`stb=0;`
560			`we = 1'hx;`
561			`sel = 4'hx;`
562			`adr = $random;`
563			`repeat(delay)`
564			`begin`
565			`@(posedge clk);`
566			`#1;`
567			`end`
568			`we = 0;`
569			`sel = s;`
570
571			`adr = a+4;`
572			`stb = 1;`
573			`@(posedge clk);`
574			`while(~ack & ~err) @(posedge clk);`
575			`d2 = din;`
576			`#2;`
577			`stb=0;`
578			`we = 1'hx;`
579			`sel = 4'hx;`
580			`adr = $random;`
581			`repeat(delay)`
582			`begin`
583			`@(posedge clk);`
584			`#1;`
585			`end`
586			`we = 0;`
587			`sel = s;`
588
589
590			`adr = a+8;`
591			`stb = 1;`
592			`@(posedge clk);`
593			`while(~ack & ~err) @(posedge clk);`
594			`d3 = din;`
595			`#2;`
596			`stb=0;`
597			`we = 1'hx;`
598			`sel = 4'hx;`
599			`adr = $random;`
600			`repeat(delay)`
601			`begin`
602			`@(posedge clk);`
603			`#1;`
604			`end`
605			`we = 0;`
606			`sel = s;`
607
608			`adr = a+12;`
609			`stb = 1;`
610			`@(posedge clk);`
611			`while(~ack & ~err) @(posedge clk);`
612			`d4 = din;`
613			`#1;`
614			`stb=0;`
615			`cyc=0;`
616			`we = 1'hx;`
617			`sel = 4'hx;`
618			`adr = 32'hffff_ffff;`
619			`adr = $random;`
620			`end`
621			`endtask`
622
623
624
625			`task wb_rd_mult;`
626			`input [31:0] a;`
627			`input [3:0] s;`
628			`input delay;`
629			`input count;`
630
631			`integer delay;`
632			`integer count;`
633			`integer n;`
634
635			`begin`
636
637			`//@(posedge clk);`
638			`#1;`
639			`cyc = 1;`
640			`we = 0;`
641			`sel = s;`
642			`repeat(delay) @(posedge clk);`
643
644			`for(n=0;n<count-1;n=n+1)`
645			`begin`
646			`adr = a + (n*4);`
647			`stb = 1;`
648			`while(~ack & ~err) @(posedge clk);`
649			`mem[n + cnt] = din;`
650			`#2;`
651			`stb=0;`
652			`we = 1'hx;`
653			`sel = 4'hx;`
654			`//adr = 32'hxxxx_xxxx;`
655			`adr = $random;`
656			`repeat(delay)`
657			`begin`
658			`@(posedge clk);`
659			`#1;`
660			`end`
661			`we = 0;`
662			`sel = s;`
663			`end`
664
665			`adr = a+(n*4);`
666			`stb = 1;`
667			`@(posedge clk);`
668			`while(~ack & ~err) @(posedge clk);`
669			`mem[n + cnt] = din;`
670			`#1;`
671			`stb=0;`
672			`cyc=0;`
673			`we = 1'hx;`
674			`sel = 4'hx;`
675			`//adr = 32'hffff_ffff;`
676			`//adr = 32'hxxxx_xxxx;`
677			`adr = $random;`
678
679			`cnt = cnt + count;`
680			`end`
681			`endtask`
682
683			`endmodule`