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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [rtl/] [verilog/] [wb_conmax_msel.v] - Blame information for rev 7

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Connection Matrix Master Select                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_conmax_msel.v,v 1.1.1.1 2001-10-19 11:01:38 rudi Exp $
//
//  $Date: 2001-10-19 11:01:38 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
 
`include "wb_conmax_defines.v"
 
module wb_conmax_msel(
                clk_i, rst_i,
                conf, req, sel, next
        );
 
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
 
parameter       [1:0]    pri_sel = 2'd0;
 
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
 
input           clk_i, rst_i;
input   [15:0]   conf;
input   [7:0]    req;
output  [2:0]    sel;
input           next;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire    [1:0]    pri0, pri1, pri2, pri3;
wire    [1:0]    pri4, pri5, pri6, pri7;
wire    [1:0]    pri_out_d;
reg     [1:0]    pri_out;
 
wire    [7:0]    req_p0, req_p1, req_p2, req_p3;
wire    [2:0]    gnt_p0, gnt_p1, gnt_p2, gnt_p3;
 
reg     [2:0]    sel1, sel2;
wire    [2:0]    sel;
 
////////////////////////////////////////////////////////////////////
//
// Priority Select logic
//
 
assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0];
assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0;
 
assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2];
assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0;
 
assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4];
assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0;
 
assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6];
assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0;
 
assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8];
assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0;
 
assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10];
assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0;
 
assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12];
assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0;
 
assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14];
assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0;
 
// Priority Encoder
wb_conmax_pri_enc #(pri_sel) pri_enc(
        .valid(         req             ),
        .pri0(          pri0            ),
        .pri1(          pri1            ),
        .pri2(          pri2            ),
        .pri3(          pri3            ),
        .pri4(          pri4            ),
        .pri5(          pri5            ),
        .pri6(          pri6            ),
        .pri7(          pri7            ),
        .pri_out(       pri_out_d       )
        );
 
always @(posedge clk_i)
        if(rst_i)       pri_out <= #1 2'h0;
        else
        if(next)        pri_out <= #1 pri_out_d;
 
////////////////////////////////////////////////////////////////////
//
// Arbiters
//
 
assign req_p0[0] = req[0] & (pri0 == 2'd0);
assign req_p0[1] = req[1] & (pri1 == 2'd0);
assign req_p0[2] = req[2] & (pri2 == 2'd0);
assign req_p0[3] = req[3] & (pri3 == 2'd0);
assign req_p0[4] = req[4] & (pri4 == 2'd0);
assign req_p0[5] = req[5] & (pri5 == 2'd0);
assign req_p0[6] = req[6] & (pri6 == 2'd0);
assign req_p0[7] = req[7] & (pri7 == 2'd0);
 
assign req_p1[0] = req[0] & (pri0 == 2'd1);
assign req_p1[1] = req[1] & (pri1 == 2'd1);
assign req_p1[2] = req[2] & (pri2 == 2'd1);
assign req_p1[3] = req[3] & (pri3 == 2'd1);
assign req_p1[4] = req[4] & (pri4 == 2'd1);
assign req_p1[5] = req[5] & (pri5 == 2'd1);
assign req_p1[6] = req[6] & (pri6 == 2'd1);
assign req_p1[7] = req[7] & (pri7 == 2'd1);
 
assign req_p2[0] = req[0] & (pri0 == 2'd2);
assign req_p2[1] = req[1] & (pri1 == 2'd2);
assign req_p2[2] = req[2] & (pri2 == 2'd2);
assign req_p2[3] = req[3] & (pri3 == 2'd2);
assign req_p2[4] = req[4] & (pri4 == 2'd2);
assign req_p2[5] = req[5] & (pri5 == 2'd2);
assign req_p2[6] = req[6] & (pri6 == 2'd2);
assign req_p2[7] = req[7] & (pri7 == 2'd2);
 
assign req_p3[0] = req[0] & (pri0 == 2'd3);
assign req_p3[1] = req[1] & (pri1 == 2'd3);
assign req_p3[2] = req[2] & (pri2 == 2'd3);
assign req_p3[3] = req[3] & (pri3 == 2'd3);
assign req_p3[4] = req[4] & (pri4 == 2'd3);
assign req_p3[5] = req[5] & (pri5 == 2'd3);
assign req_p3[6] = req[6] & (pri6 == 2'd3);
assign req_p3[7] = req[7] & (pri7 == 2'd3);
 
wb_conmax_arb arb0(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p0          ),
        .gnt(           gnt_p0          ),
        .next(          1'b0            )
        );
 
wb_conmax_arb arb1(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p1          ),
        .gnt(           gnt_p1          ),
        .next(          1'b0            )
        );
 
wb_conmax_arb arb2(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p2          ),
        .gnt(           gnt_p2          ),
        .next(          1'b0            )
        );
 
wb_conmax_arb arb3(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p3          ),
        .gnt(           gnt_p3          ),
        .next(          1'b0            )
        );
 
////////////////////////////////////////////////////////////////////
//
// Final Master Select
//
 
always @(pri_out or gnt_p0 or gnt_p1)
        if(pri_out[0])   sel1 = gnt_p1;
        else            sel1 = gnt_p0;
 
 
always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3)
        case(pri_out)
           2'd0: sel2 = gnt_p0;
           2'd1: sel2 = gnt_p1;
           2'd2: sel2 = gnt_p2;
           2'd3: sel2 = gnt_p3;
        endcase
 
 
assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 );
 
endmodule
 

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [rtl/] [verilog/] [wb_conmax_msel.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Connection Matrix Master Select ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_conmax_msel.v,v 1.1.1.1 2001-10-19 11:01:38 rudi Exp $`
41			`//`
42			`// $Date: 2001-10-19 11:01:38 $`
43			`// $Revision: 1.1.1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53			`//`
54
55			`include "wb_conmax_defines.v"
56
57			`module wb_conmax_msel(`
58			`clk_i, rst_i,`
59			`conf, req, sel, next`
60			`);`
61
62			`////////////////////////////////////////////////////////////////////`
63			`//`
64			`// Module Parameters`
65			`//`
66
67			`parameter [1:0] pri_sel = 2'd0;`
68
69			`////////////////////////////////////////////////////////////////////`
70			`//`
71			`// Module IOs`
72			`//`
73
74			`input clk_i, rst_i;`
75			`input [15:0] conf;`
76			`input [7:0] req;`
77			`output [2:0] sel;`
78			`input next;`
79
80			`////////////////////////////////////////////////////////////////////`
81			`//`
82			`// Local Wires`
83			`//`
84
85			`wire [1:0] pri0, pri1, pri2, pri3;`
86			`wire [1:0] pri4, pri5, pri6, pri7;`
87			`wire [1:0] pri_out_d;`
88			`reg [1:0] pri_out;`
89
90			`wire [7:0] req_p0, req_p1, req_p2, req_p3;`
91			`wire [2:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3;`
92
93			`reg [2:0] sel1, sel2;`
94			`wire [2:0] sel;`
95
96			`////////////////////////////////////////////////////////////////////`
97			`//`
98			`// Priority Select logic`
99			`//`
100
101			`assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0];`
102			`assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0;`
103
104			`assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2];`
105			`assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0;`
106
107			`assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4];`
108			`assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0;`
109
110			`assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6];`
111			`assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0;`
112
113			`assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8];`
114			`assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0;`
115
116			`assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10];`
117			`assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0;`
118
119			`assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12];`
120			`assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0;`
121
122			`assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14];`
123			`assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0;`
124
125			`// Priority Encoder`
126			`wb_conmax_pri_enc #(pri_sel) pri_enc(`
127			`.valid( req ),`
128			`.pri0( pri0 ),`
129			`.pri1( pri1 ),`
130			`.pri2( pri2 ),`
131			`.pri3( pri3 ),`
132			`.pri4( pri4 ),`
133			`.pri5( pri5 ),`
134			`.pri6( pri6 ),`
135			`.pri7( pri7 ),`
136			`.pri_out( pri_out_d )`
137			`);`
138
139			`always @(posedge clk_i)`
140			`if(rst_i) pri_out <= #1 2'h0;`
141			`else`
142			`if(next) pri_out <= #1 pri_out_d;`
143
144			`////////////////////////////////////////////////////////////////////`
145			`//`
146			`// Arbiters`
147			`//`
148
149			`assign req_p0[0] = req[0] & (pri0 == 2'd0);`
150			`assign req_p0[1] = req[1] & (pri1 == 2'd0);`
151			`assign req_p0[2] = req[2] & (pri2 == 2'd0);`
152			`assign req_p0[3] = req[3] & (pri3 == 2'd0);`
153			`assign req_p0[4] = req[4] & (pri4 == 2'd0);`
154			`assign req_p0[5] = req[5] & (pri5 == 2'd0);`
155			`assign req_p0[6] = req[6] & (pri6 == 2'd0);`
156			`assign req_p0[7] = req[7] & (pri7 == 2'd0);`
157
158			`assign req_p1[0] = req[0] & (pri0 == 2'd1);`
159			`assign req_p1[1] = req[1] & (pri1 == 2'd1);`
160			`assign req_p1[2] = req[2] & (pri2 == 2'd1);`
161			`assign req_p1[3] = req[3] & (pri3 == 2'd1);`
162			`assign req_p1[4] = req[4] & (pri4 == 2'd1);`
163			`assign req_p1[5] = req[5] & (pri5 == 2'd1);`
164			`assign req_p1[6] = req[6] & (pri6 == 2'd1);`
165			`assign req_p1[7] = req[7] & (pri7 == 2'd1);`
166
167			`assign req_p2[0] = req[0] & (pri0 == 2'd2);`
168			`assign req_p2[1] = req[1] & (pri1 == 2'd2);`
169			`assign req_p2[2] = req[2] & (pri2 == 2'd2);`
170			`assign req_p2[3] = req[3] & (pri3 == 2'd2);`
171			`assign req_p2[4] = req[4] & (pri4 == 2'd2);`
172			`assign req_p2[5] = req[5] & (pri5 == 2'd2);`
173			`assign req_p2[6] = req[6] & (pri6 == 2'd2);`
174			`assign req_p2[7] = req[7] & (pri7 == 2'd2);`
175
176			`assign req_p3[0] = req[0] & (pri0 == 2'd3);`
177			`assign req_p3[1] = req[1] & (pri1 == 2'd3);`
178			`assign req_p3[2] = req[2] & (pri2 == 2'd3);`
179			`assign req_p3[3] = req[3] & (pri3 == 2'd3);`
180			`assign req_p3[4] = req[4] & (pri4 == 2'd3);`
181			`assign req_p3[5] = req[5] & (pri5 == 2'd3);`
182			`assign req_p3[6] = req[6] & (pri6 == 2'd3);`
183			`assign req_p3[7] = req[7] & (pri7 == 2'd3);`
184
185			`wb_conmax_arb arb0(`
186			`.clk( clk_i ),`
187			`.rst( rst_i ),`
188			`.req( req_p0 ),`
189			`.gnt( gnt_p0 ),`
190			`.next( 1'b0 )`
191			`);`
192
193			`wb_conmax_arb arb1(`
194			`.clk( clk_i ),`
195			`.rst( rst_i ),`
196			`.req( req_p1 ),`
197			`.gnt( gnt_p1 ),`
198			`.next( 1'b0 )`
199			`);`
200
201			`wb_conmax_arb arb2(`
202			`.clk( clk_i ),`
203			`.rst( rst_i ),`
204			`.req( req_p2 ),`
205			`.gnt( gnt_p2 ),`
206			`.next( 1'b0 )`
207			`);`
208
209			`wb_conmax_arb arb3(`
210			`.clk( clk_i ),`
211			`.rst( rst_i ),`
212			`.req( req_p3 ),`
213			`.gnt( gnt_p3 ),`
214			`.next( 1'b0 )`
215			`);`
216
217			`////////////////////////////////////////////////////////////////////`
218			`//`
219			`// Final Master Select`
220			`//`
221
222			`always @(pri_out or gnt_p0 or gnt_p1)`
223			`if(pri_out[0]) sel1 = gnt_p1;`
224			`else sel1 = gnt_p0;`
225
226
227			`always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3)`
228			`case(pri_out)`
229			`2'd0: sel2 = gnt_p0;`
230			`2'd1: sel2 = gnt_p1;`
231			`2'd2: sel2 = gnt_p2;`
232			`2'd3: sel2 = gnt_p3;`
233			`endcase`
234
235
236			`assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 );`
237
238			`endmodule`
239