OpenCores
URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [sim/] [rtl_sim/] [run/] [ncwork/] [hdl.var] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 parrado
#*****************************************************************************
2
# NCSIM hdl.var template                                                     *
3
#*****************************************************************************
4
 
5
#This file allows commonly used tool setups to be invoked automatically.
6
#All the switches may be alternatively specifed on the command line.
7
 
8
#reference the tool installation hdl.var - DO NOT REMOVE
9
 
10
INCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var
11
 
12
# These are default settings for NCVLOG, NCVHDL, NCELAB, NCSIM
13
# See below for commonly used switches.
14
 
15
DEFINE NCVLOGOPTS -NOCOPYRIGHT -UPDATE
16
DEFINE NCVHDLOPTS -NOCOPYRIGHT -UPDATE
17
DEFINE NCELABOPTS -NOCOPYRIGHT
18
DEFINE NCSIMOPTS  -NOCOPYRIGHT -NOKEY -STATUS
19
 
20
#Maps the work library to a logical library.
21
#This library will contain the compiled design units
22
#Can be overriden on the command line with -work 
23
#DEFINE WORK work
24
DEFINE work ../ncwork
25
 
26
# Define valid Verilog file extensions
27
DEFINE VERILOG_SUFFIX (.v, .vr, .vb, .vg)
28
 
29
# Define valid VHDL file extensions
30
DEFINE VHDL_SUFFIX (.vhd, .vhdl)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.