OpenCores
URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [bench/] [verilog/] [tests.v] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 parrado 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
3 
////  WISHBONE Connection Matrix Test Cases                      ////
4 
////                                                             ////
5 
////                                                             ////
6 
////  Author: Rudolf Usselmann                                   ////
7 
////          rudi@asics.ws                                      ////
8 
////                                                             ////
9 
////                                                             ////
10 
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
11 
////                                                             ////
12 
/////////////////////////////////////////////////////////////////////
13 
////                                                             ////
14 
//// Copyright (C) 2000 Rudolf Usselmann                         ////
15 
////                    rudi@asics.ws                            ////
16 
////                                                             ////
17 
//// This source file may be used and distributed without        ////
18 
//// restriction provided that this copyright statement is not   ////
19 
//// removed from the file and that any derivative work contains ////
20 
//// the original copyright notice and the associated disclaimer.////
21 
////                                                             ////
22 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
23 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
24 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
25 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
26 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
27 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
28 
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
29 
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
30 
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
31 
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
32 
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
33 
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
34 
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
35 
////                                                             ////
36 
/////////////////////////////////////////////////////////////////////
37 
 
38 
//  CVS Log
39 
//
40 
//  $Id: tests.v,v 1.1.1.1 2001-10-19 11:04:27 rudi Exp $
41 
//
42 
//  $Date: 2001-10-19 11:04:27 $
43 
//  $Revision: 1.1.1.1 $
44 
//  $Author: rudi $
45 
//  $Locker:  $
46 
//  $State: Exp $
47 
//
48 
// Change History:
49 
//               $Log: not supported by cvs2svn $
50 
//
51 
//
52 
//
53 
//
54 
//
55 
 
56 
 
57 
task show_errors;
58 
 
59 
begin
60 
 
61 
$display("\n");
62 
$display("     +--------------------+");
63 
$display("     |  Total ERRORS: %0d   |", error_cnt);
64 
$display("     +--------------------+");
65 
 
66 
end
67 
endtask
68 
 
69 
 
70 
task init_all_mem;
71 
 
72 
begin
73 
        s0.fill_mem(1);
74 
        s1.fill_mem(1);
75 
        s2.fill_mem(1);
76 
        s3.fill_mem(1);
77 
        s4.fill_mem(1);
78 
        s5.fill_mem(1);
79 
        s6.fill_mem(1);
80 
        s7.fill_mem(1);
81 
        s8.fill_mem(1);
82 
        s9.fill_mem(1);
83 
        s10.fill_mem(1);
84 
        s11.fill_mem(1);
85 
        s12.fill_mem(1);
86 
        s13.fill_mem(1);
87 
        s14.fill_mem(1);
88 
        s15.fill_mem(1);
89 
 
90 
        m0.mem_fill;
91 
        m1.mem_fill;
92 
        m2.mem_fill;
93 
        m3.mem_fill;
94 
        m4.mem_fill;
95 
        m5.mem_fill;
96 
        m6.mem_fill;
97 
        m7.mem_fill;
98 
 
99 
end
100 
endtask
101 
 
102 
 
103 
task verify;
104 
input   master;
105 
input   slave;
106 
input   count;
107 
 
108 
integer         master, slave, count;
109 
begin
110 
verify_sub(master,slave,count,0,0);
111 
end
112 
endtask
113 
 
114 
 
115 
task verify_sub;
116 
input   master;
117 
input   slave;
118 
input   count;
119 
input   mo;
120 
input   so;
121 
 
122 
integer         master, slave, count;
123 
integer         mo, so;
124 
integer         o;
125 
integer         n;
126 
reg     [31:0]   mdata, sdata;
127 
 
128 
begin
129 
 
130 
//$display("V2: %0d %0d %0d %0d %0d",master, slave, count, mo,so);
131 
 
132 
for(n=0;n<count;n=n+1)
133 
   begin
134 
        case(master)
135 
           0: mdata = m0.mem[n+mo];
136 
           1: mdata = m1.mem[n+mo];
137 
           2: mdata = m2.mem[n+mo];
138 
           3: mdata = m3.mem[n+mo];
139 
           4: mdata = m4.mem[n+mo];
140 
           5: mdata = m5.mem[n+mo];
141 
           6: mdata = m6.mem[n+mo];
142 
           7: mdata = m7.mem[n+mo];
143 
           default:
144 
                begin
145 
                $display("ERROR: Illegal Master %0d", master);
146 
                $finish;
147 
                end
148 
        endcase
149 
 
150 
        o = 0;
151 
        case(master)
152 
           0: o = 16'h000;
153 
           1: o = 16'h040;
154 
           2: o = 16'h080;
155 
           3: o = 16'h0c0;
156 
           4: o = 16'h100;
157 
           5: o = 16'h140;
158 
           6: o = 16'h180;
159 
           7: o = 16'h1c0;
160 
        endcase
161 
 
162 
        case(slave)
163 
           0: sdata = s0.mem[n+o+so];
164 
           1: sdata = s1.mem[n+o+so];
165 
           2: sdata = s2.mem[n+o+so];
166 
           3: sdata = s3.mem[n+o+so];
167 
           4: sdata = s4.mem[n+o+so];
168 
           5: sdata = s5.mem[n+o+so];
169 
           6: sdata = s6.mem[n+o+so];
170 
           7: sdata = s7.mem[n+o+so];
171 
           8: sdata = s8.mem[n+o+so];
172 
           9: sdata = s9.mem[n+o+so];
173 
           10: sdata = s10.mem[n+o+so];
174 
           11: sdata = s11.mem[n+o+so];
175 
           12: sdata = s12.mem[n+o+so];
176 
           13: sdata = s13.mem[n+o+so];
177 
           14: sdata = s14.mem[n+o+so];
178 
           15: sdata = s15.mem[n+o+so];
179 
           default:
180 
                begin
181 
                $display("ERROR: Illegal Slave %0d", slave);
182 
                $finish;
183 
                end
184 
        endcase
185 
 
186 
        //$display("INFO: Master[%0d]: %h - Slave[%0d]: %h (%0t)",
187 
        //      master, mdata, slave, sdata, $time);
188 
 
189 
        if(mdata !== sdata)
190 
           begin
191 
                $display("ERROR: Master[%0d][%0d]: %h - Slave[%0d]: %h (%0t)",
192 
                master, n, mdata, slave, sdata, $time);
193 
                error_cnt = error_cnt + 1;
194 
           end
195 
   end
196 
end
197 
 
198 
endtask
199 
 
200 
 
201 
task test_arb1;
202 
 
203 
integer n, del;
204 
reg     [31:0]   data;
205 
 
206 
begin
207 
 
208 
        $display("\n\n");
209 
        $display("*****************************************************");
210 
        $display("*** Arb. 1 Test ...                               ***");
211 
        $display("*****************************************************\n");
212 
 
213 
del = 4;
214 
for(del = 0;del < 5; del=del+1 )
215 
   begin
216 
        $display("Delay: %0d", del);
217 
        init_all_mem;
218 
        m1.wb_wr1( 32'hff00_0000, 4'hf, 32'h0000_a5ff);
219 
 
220 
        fork
221 
           begin
222 
                m0.wb_rd_mult( 32'h0000_0000 + (0 << 28), 4'hf, del, 4);
223 
                m0.wb_rd1( 32'hff00_0000, 4'hf, data);
224 
                if(data !== 32'h0000_a5ff)
225 
                   begin
226 
                        $display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
227 
                        error_cnt = error_cnt + 1;
228 
                   end
229 
                m0.wb_wr_mult( 32'h0000_0010 + (0 << 28), 4'hf, del, 4);
230 
                m0.wb_rd_mult( 32'h0000_0020 + (0 << 28), 4'hf, del, 4);
231 
                m0.wb_wr_mult( 32'h0000_0030 + (0 << 28), 4'hf, del, 4);
232 
           end
233 
 
234 
           begin
235 
                m1.wb_wr_mult( 32'h0000_0100 + (0 << 28), 4'hf, del, 4);
236 
                m1.wb_rd_mult( 32'h0000_0110 + (0 << 28), 4'hf, del, 4);
237 
                m1.wb_rd1( 32'hff00_0000, 4'hf, data);
238 
                if(data !== 32'h0000_a5ff)
239 
                   begin
240 
                        $display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
241 
                        error_cnt = error_cnt + 1;
242 
                   end
243 
                m1.wb_wr_mult( 32'h0000_0120 + (0 << 28), 4'hf, del, 4);
244 
                m1.wb_rd_mult( 32'h0000_0130 + (0 << 28), 4'hf, del, 4);
245 
           end
246 
 
247 
           begin
248 
                m2.wb_rd_mult( 32'h0000_0200 + (0 << 28), 4'hf, del, 4);
249 
                m2.wb_wr_mult( 32'h0000_0210 + (0 << 28), 4'hf, del, 4);
250 
                m2.wb_rd_mult( 32'h0000_0220 + (0 << 28), 4'hf, del, 4);
251 
                m2.wb_rd1( 32'hff00_0000, 4'hf, data);
252 
                if(data !== 32'h0000_a5ff)
253 
                   begin
254 
                        $display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
255 
                        error_cnt = error_cnt + 1;
256 
                   end
257 
                m2.wb_wr_mult( 32'h0000_0230 + (0 << 28), 4'hf, del, 4);
258 
           end
259 
 
260 
           begin
261 
                m3.wb_wr_mult( 32'h0000_0300 + (0 << 28), 4'hf, del, 4);
262 
                m3.wb_rd_mult( 32'h0000_0310 + (0 << 28), 4'hf, del, 4);
263 
                m3.wb_wr_mult( 32'h0000_0320 + (0 << 28), 4'hf, del, 4);
264 
                m3.wb_rd_mult( 32'h0000_0330 + (0 << 28), 4'hf, del, 4);
265 
                m3.wb_rd1( 32'hff00_0000, 4'hf, data);
266 
                if(data !== 32'h0000_a5ff)
267 
                   begin
268 
                        $display("ERROR: RF read mismatch: Exp. a5ff, Got %h", data);
269 
                        error_cnt = error_cnt + 1;
270 
                   end
271 
           end
272 
 
273 
           begin
274 
                m4.wb_rd_mult( 32'h0000_0400 + (1 << 28), 4'hf, del, 4);
275 
                m4.wb_wr_mult( 32'h0000_0410 + (1 << 28), 4'hf, del, 4);
276 
                m4.wb_rd_mult( 32'h0000_0420 + (1 << 28), 4'hf, del, 4);
277 
                m4.wb_wr_mult( 32'h0000_0430 + (1 << 28), 4'hf, del, 4);
278 
           end
279 
 
280 
           begin
281 
                m5.wb_rd_mult( 32'h0000_0500 + (1 << 28), 4'hf, del, 4);
282 
                m5.wb_wr_mult( 32'h0000_0510 + (1 << 28), 4'hf, del, 4);
283 
                m5.wb_rd_mult( 32'h0000_0520 + (1 << 28), 4'hf, del, 4);
284 
                m5.wb_wr_mult( 32'h0000_0530 + (1 << 28), 4'hf, del, 4);
285 
           end
286 
 
287 
           begin
288 
                m6.wb_wr_mult( 32'h0000_0600 + (15 << 28), 4'hf, del, 4);
289 
                m6.wb_rd_mult( 32'h0000_0610 + (15 << 28), 4'hf, del, 4);
290 
                m6.wb_wr_mult( 32'h0000_0620 + (15 << 28), 4'hf, del, 4);
291 
                m6.wb_rd_mult( 32'h0000_0630 + (15 << 28), 4'hf, del, 4);
292 
           end
293 
 
294 
           begin
295 
                m7.wb_wr_mult( 32'h0000_0700 + (15 << 28), 4'hf, del, 4);
296 
                m7.wb_rd_mult( 32'h0000_0710 + (15 << 28), 4'hf, del, 4);
297 
                m7.wb_wr_mult( 32'h0000_0720 + (15 << 28), 4'hf, del, 4);
298 
                m7.wb_rd_mult( 32'h0000_0730 + (15 << 28), 4'hf, del, 4);
299 
           end
300 
        join
301 
 
302 
        verify(0,0,16);
303 
        verify(1,0,16);
304 
        verify(2,0,16);
305 
        verify(3,0,16);
306 
        verify(4,1,16);
307 
        verify(5,1,16);
308 
        verify(6,15,16);
309 
        verify(7,15,16);
310 
   end
311 
        show_errors;
312 
        $display("*****************************************************");
313 
        $display("*** Test DONE ...                                 ***");
314 
        $display("*****************************************************\n\n");
315 
 
316 
end
317 
endtask
318 
 
319 
 
320 
task test_arb2;
321 
 
322 
integer         m, del, siz;
323 
integer         n, a, b;
324 
time            t[0:7];
325 
reg     [1:0]    p[0:7];
326 
 
327 
begin
328 
 
329 
        $display("\n\n");
330 
        $display("*****************************************************");
331 
        $display("*** Arb. 2 Test ...                               ***");
332 
        $display("*****************************************************\n");
333 
 
334 
 
335 
siz = 4;
336 
del = 0;
337 
m=0;
338 
for(m=0;m<32;m=m+1)
339 
for(del=0;del<7;del=del+1)
340 
for(siz=1;siz<5;siz=siz+1)
341 
   begin
342 
 
343 
        init_all_mem;
344 
        $display("Mode: %0d del: %0d, siz: %0d", m, del, siz);
345 
 
346 
        case(m)
347 
           0:
348 
                begin
349 
                p[7] = 2'd3;    // M 7
350 
                p[6] = 2'd1;    // M 6
351 
                p[5] = 2'd2;    // M 5
352 
                p[4] = 2'd3;    // M 4
353 
                p[3] = 2'd0;    // M 3
354 
                p[2] = 2'd1;    // M 2
355 
                p[1] = 2'd0;    // M 1
356 
                p[0] = 2'd2;     // M 0
357 
                end
358 
 
359 
            4:
360 
                begin
361 
                p[7] = 2'd0;    // M 7
362 
                p[6] = 2'd1;    // M 6
363 
                p[5] = 2'd2;    // M 5
364 
                p[4] = 2'd3;    // M 4
365 
                p[3] = 2'd3;    // M 3
366 
                p[2] = 2'd2;    // M 2
367 
                p[1] = 2'd1;    // M 1
368 
                p[0] = 2'd0;     // M 0
369 
                end
370 
 
371 
            8:
372 
                begin
373 
                p[7] = 2'd3;    // M 7
374 
                p[6] = 2'd2;    // M 6
375 
                p[5] = 2'd1;    // M 5
376 
                p[4] = 2'd0;    // M 4
377 
                p[3] = 2'd0;    // M 3
378 
                p[2] = 2'd1;    // M 2
379 
                p[1] = 2'd2;    // M 1
380 
                p[0] = 2'd3;     // M 0
381 
                end
382 
 
383 
            12:
384 
                begin
385 
                p[7] = 2'd3;    // M 7
386 
                p[6] = 2'd3;    // M 6
387 
                p[5] = 2'd3;    // M 5
388 
                p[4] = 2'd0;    // M 4
389 
                p[3] = 2'd0;    // M 3
390 
                p[2] = 2'd0;    // M 2
391 
                p[1] = 2'd1;    // M 1
392 
                p[0] = 2'd1;     // M 0
393 
                end
394 
 
395 
            16:
396 
                begin
397 
                p[7] = 2'd0;    // M 7
398 
                p[6] = 2'd0;    // M 6
399 
                p[5] = 2'd0;    // M 5
400 
                p[4] = 2'd0;    // M 4
401 
                p[3] = 2'd1;    // M 3
402 
                p[2] = 2'd1;    // M 2
403 
                p[1] = 2'd3;    // M 1
404 
                p[0] = 2'd3;     // M 0
405 
                end
406 
 
407 
            20:
408 
                begin
409 
                p[7] = 2'd3;    // M 7
410 
                p[6] = 2'd0;    // M 6
411 
                p[5] = 2'd2;    // M 5
412 
                p[4] = 2'd0;    // M 4
413 
                p[3] = 2'd1;    // M 3
414 
                p[2] = 2'd0;    // M 2
415 
                p[1] = 2'd0;    // M 1
416 
                p[0] = 2'd0;     // M 0
417 
                end
418 
 
419 
            24:
420 
                begin
421 
                p[7] = 2'd0;    // M 7
422 
                p[6] = 2'd0;    // M 6
423 
                p[5] = 2'd1;    // M 5
424 
                p[4] = 2'd0;    // M 4
425 
                p[3] = 2'd0;    // M 3
426 
                p[2] = 2'd2;    // M 2
427 
                p[1] = 2'd0;    // M 1
428 
                p[0] = 2'd3;     // M 0
429 
                end
430 
 
431 
            28:
432 
                begin
433 
                p[7] = 2'd0;    // M 7
434 
                p[6] = 2'd0;    // M 6
435 
                p[5] = 2'd1;    // M 5
436 
                p[4] = 2'd0;    // M 4
437 
                p[3] = 2'd0;    // M 3
438 
                p[2] = 2'd0;    // M 2
439 
                p[1] = 2'd0;    // M 1
440 
                p[0] = 2'd3;     // M 0
441 
                end
442 
 
443 
            default:
444 
                begin
445 
                p[7] = p[7] + 1;// M 7
446 
                p[6] = p[6] + 1;// M 6
447 
                p[5] = p[5] + 1;// M 5
448 
                p[4] = p[4] + 1;// M 4
449 
                p[3] = p[3] + 1;// M 3
450 
                p[2] = p[2] + 1;// M 2
451 
                p[1] = p[1] + 1;// M 1
452 
                p[0] = p[0] + 1;// M 0
453 
                end
454 
        endcase
455 
 
456 
        m1.wb_wr1( 32'hff00_0000, 4'hf, {16'h0000, p[7], p[6], p[5],
457 
                        p[4], p[3], p[2], p[1], p[0]} );
458 
 
459 
        @(posedge clk);
460 
        fork
461 
           begin
462 
                repeat(del)     @(posedge clk);
463 
                m0.wb_wr_mult( 32'h0000_0000             , 4'hf, del, siz);
464 
                repeat(del)     @(posedge clk);
465 
                m0.wb_rd_mult( 32'h0000_0000 + (siz *  4), 4'hf, del, siz);
466 
                repeat(del)     @(posedge clk);
467 
                m0.wb_wr_mult( 32'h0000_0000 + (siz *  8), 4'hf, del, siz);
468 
                repeat(del)     @(posedge clk);
469 
                m0.wb_rd_mult( 32'h0000_0000 + (siz * 12), 4'hf, del, siz);
470 
                t[0] = $time;
471 
           end
472 
 
473 
           begin
474 
                repeat(del)     @(posedge clk);
475 
                m1.wb_rd_mult( 32'h0000_0100             , 4'hf, del, siz);
476 
                repeat(del)     @(posedge clk);
477 
                m1.wb_wr_mult( 32'h0000_0100 + (siz *  4), 4'hf, del, siz);
478 
                repeat(del)     @(posedge clk);
479 
                m1.wb_rd_mult( 32'h0000_0100 + (siz *  8), 4'hf, del, siz);
480 
                repeat(del)     @(posedge clk);
481 
                m1.wb_wr_mult( 32'h0000_0100 + (siz * 12), 4'hf, del, siz);
482 
                t[1] = $time;
483 
           end
484 
 
485 
           begin
486 
                repeat(del)     @(posedge clk);
487 
                m2.wb_wr_mult( 32'h0000_0200             , 4'hf, del, siz);
488 
                repeat(del)     @(posedge clk);
489 
                m2.wb_rd_mult( 32'h0000_0200 + (siz *  4), 4'hf, del, siz);
490 
                repeat(del)     @(posedge clk);
491 
                m2.wb_wr_mult( 32'h0000_0200 + (siz *  8), 4'hf, del, siz);
492 
                repeat(del)     @(posedge clk);
493 
                m2.wb_rd_mult( 32'h0000_0200 + (siz * 12), 4'hf, del, siz);
494 
                t[2] = $time;
495 
           end
496 
 
497 
           begin
498 
                repeat(del)     @(posedge clk);
499 
                m3.wb_rd_mult( 32'h0000_0300             , 4'hf, del, siz);
500 
                repeat(del)     @(posedge clk);
501 
                m3.wb_wr_mult( 32'h0000_0300 + (siz *  4), 4'hf, del, siz);
502 
                repeat(del)     @(posedge clk);
503 
                m3.wb_rd_mult( 32'h0000_0300 + (siz *  8), 4'hf, del, siz);
504 
                repeat(del)     @(posedge clk);
505 
                m3.wb_wr_mult( 32'h0000_0300 + (siz * 12), 4'hf, del, siz);
506 
                t[3] = $time;
507 
           end
508 
 
509 
           begin
510 
                repeat(del)     @(posedge clk);
511 
                m4.wb_wr_mult( 32'h0000_0400             , 4'hf, del, siz);
512 
                repeat(del)     @(posedge clk);
513 
                m4.wb_rd_mult( 32'h0000_0400 + (siz *  4), 4'hf, del, siz);
514 
                repeat(del)     @(posedge clk);
515 
                m4.wb_wr_mult( 32'h0000_0400 + (siz *  8), 4'hf, del, siz);
516 
                repeat(del)     @(posedge clk);
517 
                m4.wb_rd_mult( 32'h0000_0400 + (siz * 12), 4'hf, del, siz);
518 
                t[4] = $time;
519 
           end
520 
 
521 
           begin
522 
                repeat(del)     @(posedge clk);
523 
                m5.wb_rd_mult( 32'h0000_0500             , 4'hf, del, siz);
524 
                repeat(del)     @(posedge clk);
525 
                m5.wb_wr_mult( 32'h0000_0500 + (siz *  4), 4'hf, del, siz);
526 
                repeat(del)     @(posedge clk);
527 
                m5.wb_rd_mult( 32'h0000_0500 + (siz *  8), 4'hf, del, siz);
528 
                repeat(del)     @(posedge clk);
529 
                m5.wb_wr_mult( 32'h0000_0500 + (siz * 12), 4'hf, del, siz);
530 
                t[5] = $time;
531 
           end
532 
 
533 
           begin
534 
                repeat(del)     @(posedge clk);
535 
                m6.wb_wr_mult( 32'h0000_0600             , 4'hf, del, siz);
536 
                repeat(del)     @(posedge clk);
537 
                m6.wb_rd_mult( 32'h0000_0600 + (siz *  4), 4'hf, del, siz);
538 
                repeat(del)     @(posedge clk);
539 
                m6.wb_wr_mult( 32'h0000_0600 + (siz *  8), 4'hf, del, siz);
540 
                repeat(del)     @(posedge clk);
541 
                m6.wb_rd_mult( 32'h0000_0600 + (siz * 12), 4'hf, del, siz);
542 
                t[6] = $time;
543 
           end
544 
 
545 
           begin
546 
                repeat(del)     @(posedge clk);
547 
                m7.wb_wr_mult( 32'h0000_0700             , 4'hf, del, siz);
548 
                repeat(del)     @(posedge clk);
549 
                m7.wb_rd_mult( 32'h0000_0700 + (siz *  4), 4'hf, del, siz);
550 
                repeat(del)     @(posedge clk);
551 
                m7.wb_wr_mult( 32'h0000_0700 + (siz *  8), 4'hf, del, siz);
552 
                repeat(del)     @(posedge clk);
553 
                m7.wb_rd_mult( 32'h0000_0700 + (siz * 12), 4'hf, del, siz);
554 
                t[7] = $time;
555 
           end
556 
 
557 
        join
558 
 
559 
        verify(0,0,siz*4);
560 
        verify(1,0,siz*4);
561 
        verify(2,0,siz*4);
562 
        verify(3,0,siz*4);
563 
        verify(4,0,siz*4);
564 
        verify(5,0,siz*4);
565 
        verify(6,0,siz*4);
566 
        verify(7,0,siz*4);
567 
 
568 
        for(a=0;a<8;a=a+1)
569 
        for(b=0;b<8;b=b+1)
570 
                if((t[a] < t[b]) & (p[a] <= p[b]) & (p[a] != p[b]) )
571 
                   begin
572 
                        $display("ERROR: Master %0d compleated before Master %0d", a, b);
573 
                        $display("       M[%0d] pri: %0d (t: %0t)", a, p[a], t[a]);
574 
                        $display("       M[%0d] pri: %0d (t: %0t)", b, p[b], t[b]);
575 
                        error_cnt = error_cnt + 1;
576 
                   end
577 
   end
578 
 
579 
        show_errors;
580 
        $display("*****************************************************");
581 
        $display("*** Test DONE ...                                 ***");
582 
        $display("*****************************************************\n\n");
583 
 
584 
end
585 
endtask
586 
 
587 
 
588 
 
589 
task test_dp1;
590 
 
591 
integer n;
592 
reg     [3:0]    s0, s1, s2, s3, s4, s5, s6, s7;
593 
 
594 
begin
595 
 
596 
        $display("\n\n");
597 
        $display("*****************************************************");
598 
        $display("*** Datapath 1 Test ...                           ***");
599 
        $display("*****************************************************\n");
600 
 
601 
s0 = 0;
602 
s1 = 1;
603 
s2 = 2;
604 
s3 = 3;
605 
s4 = 4;
606 
s5 = 5;
607 
s6 = 6;
608 
s7 = 7;
609 
 
610 
for(n=0;n<16;n=n+1)
611 
   begin
612 
        init_all_mem;
613 
        $display("Mode: %0d", n);
614 
 
615 
        fork
616 
 
617 
        begin
618 
                m0.wb_wr_mult( 32'h0000_0000 + (s0 << 28), 4'hf, 0, 4);
619 
                m0.wb_rd_mult( 32'h0000_0010 + (s0 << 28), 4'hf, 0, 4);
620 
                m0.wb_wr_mult( 32'h0000_0020 + (s0 << 28), 4'hf, 0, 4);
621 
                m0.wb_rd_mult( 32'h0000_0030 + (s0 << 28), 4'hf, 0, 4);
622 
        end
623 
 
624 
        begin
625 
                m1.wb_wr_mult( 32'h0000_0100 + (s1 << 28), 4'hf, 0, 4);
626 
                m1.wb_rd_mult( 32'h0000_0110 + (s1 << 28), 4'hf, 0, 4);
627 
                m1.wb_wr_mult( 32'h0000_0120 + (s1 << 28), 4'hf, 0, 4);
628 
                m1.wb_rd_mult( 32'h0000_0130 + (s1 << 28), 4'hf, 0, 4);
629 
        end
630 
 
631 
        begin
632 
                m2.wb_wr_mult( 32'h0000_0200 + (s2 << 28), 4'hf, 0, 4);
633 
                m2.wb_rd_mult( 32'h0000_0210 + (s2 << 28), 4'hf, 0, 4);
634 
                m2.wb_wr_mult( 32'h0000_0220 + (s2 << 28), 4'hf, 0, 4);
635 
                m2.wb_rd_mult( 32'h0000_0230 + (s2 << 28), 4'hf, 0, 4);
636 
        end
637 
 
638 
        begin
639 
                m3.wb_wr_mult( 32'h0000_0300 + (s3 << 28), 4'hf, 0, 4);
640 
                m3.wb_rd_mult( 32'h0000_0310 + (s3 << 28), 4'hf, 0, 4);
641 
                m3.wb_wr_mult( 32'h0000_0320 + (s3 << 28), 4'hf, 0, 4);
642 
                m3.wb_rd_mult( 32'h0000_0330 + (s3 << 28), 4'hf, 0, 4);
643 
        end
644 
 
645 
        begin
646 
                m4.wb_wr_mult( 32'h0000_0400 + (s4 << 28), 4'hf, 0, 4);
647 
                m4.wb_rd_mult( 32'h0000_0410 + (s4 << 28), 4'hf, 0, 4);
648 
                m4.wb_wr_mult( 32'h0000_0420 + (s4 << 28), 4'hf, 0, 4);
649 
                m4.wb_rd_mult( 32'h0000_0430 + (s4 << 28), 4'hf, 0, 4);
650 
        end
651 
 
652 
        begin
653 
                m5.wb_wr_mult( 32'h0000_0500 + (s5 << 28), 4'hf, 0, 4);
654 
                m5.wb_rd_mult( 32'h0000_0510 + (s5 << 28), 4'hf, 0, 4);
655 
                m5.wb_wr_mult( 32'h0000_0520 + (s5 << 28), 4'hf, 0, 4);
656 
                m5.wb_rd_mult( 32'h0000_0530 + (s5 << 28), 4'hf, 0, 4);
657 
        end
658 
 
659 
        begin
660 
                m6.wb_wr_mult( 32'h0000_0600 + (s6 << 28), 4'hf, 0, 4);
661 
                m6.wb_rd_mult( 32'h0000_0610 + (s6 << 28), 4'hf, 0, 4);
662 
                m6.wb_wr_mult( 32'h0000_0620 + (s6 << 28), 4'hf, 0, 4);
663 
                m6.wb_rd_mult( 32'h0000_0630 + (s6 << 28), 4'hf, 0, 4);
664 
        end
665 
 
666 
        begin
667 
                m7.wb_wr_mult( 32'h0000_0700 + (s7 << 28), 4'hf, 0, 4);
668 
                m7.wb_rd_mult( 32'h0000_0710 + (s7 << 28), 4'hf, 0, 4);
669 
                m7.wb_wr_mult( 32'h0000_0720 + (s7 << 28), 4'hf, 0, 4);
670 
                m7.wb_rd_mult( 32'h0000_0730 + (s7 << 28), 4'hf, 0, 4);
671 
        end
672 
 
673 
        join
674 
 
675 
        verify(0,s0,16);
676 
        verify(1,s1,16);
677 
        verify(2,s2,16);
678 
        verify(3,s3,16);
679 
        verify(4,s4,16);
680 
        verify(5,s5,16);
681 
        verify(6,s6,16);
682 
        verify(7,s7,16);
683 
 
684 
        @(posedge clk);
685 
 
686 
        s0 = s0 + 1;
687 
        s1 = s1 + 1;
688 
        s2 = s2 + 1;
689 
        s3 = s3 + 1;
690 
        s4 = s4 + 1;
691 
        s5 = s5 + 1;
692 
        s6 = s6 + 1;
693 
        s7 = s7 + 1;
694 
 
695 
        @(posedge clk);
696 
 
697 
   end
698 
 
699 
        show_errors;
700 
        $display("*****************************************************");
701 
        $display("*** Test DONE ...                                 ***");
702 
        $display("*****************************************************\n\n");
703 
 
704 
end
705 
endtask
706 
 
707 
task test_dp2;
708 
 
709 
integer del;
710 
integer x0, x1, x2, x3, x4, x5, x6, x7;
711 
reg     [3:0]    m;
712 
 
713 
begin
714 
 
715 
        $display("\n\n");
716 
        $display("*****************************************************");
717 
        $display("*** Datapath 2 Test ...                           ***");
718 
        $display("*****************************************************\n");
719 
 
720 
del=0;
721 
for(del=0;del<5;del=del+1)
722 
   begin
723 
        init_all_mem;
724 
        $display("Delay: %0d", del);
725 
 
726 
        fork
727 
 
728 
        begin
729 
                for(x0=0;x0<16;x0=x0+1)
730 
                        m0.wb_rd_mult( 32'h0000_0000 + ((0+x0) << 28) + (x0<<4), 4'hf, del, 4);
731 
        end
732 
 
733 
        begin
734 
                for(x1=0;x1<16;x1=x1+1)
735 
                        m1.wb_rd_mult( 32'h0000_0100 + ((1+x1) << 28) + (x1<<4), 4'hf, del, 4);
736 
        end
737 
 
738 
        begin
739 
                for(x2=0;x2<16;x2=x2+1)
740 
                        m2.wb_rd_mult( 32'h0000_0200 + ((2+x2) << 28) + (x2<<4), 4'hf, del, 4);
741 
 
742 
        end
743 
 
744 
        begin
745 
                for(x3=0;x3<16;x3=x3+1)
746 
                        m3.wb_rd_mult( 32'h0000_0300 + ((3+x3) << 28) + (x3<<4), 4'hf, del, 4);
747 
        end
748 
 
749 
        begin
750 
                for(x4=0;x4<16;x4=x4+1)
751 
                        m4.wb_rd_mult( 32'h0000_0400 + ((4+x4) << 28) + (x4<<4), 4'hf, del, 4);
752 
        end
753 
 
754 
        begin
755 
                for(x5=0;x5<16;x5=x5+1)
756 
                        m5.wb_rd_mult( 32'h0000_0500 + ((5+x5) << 28) + (x5<<4), 4'hf, del, 4);
757 
        end
758 
 
759 
        begin
760 
                for(x6=0;x6<16;x6=x6+1)
761 
                        m6.wb_rd_mult( 32'h0000_0600 + ((6+x6) << 28) + (x6<<4), 4'hf, del, 4);
762 
        end
763 
 
764 
        begin
765 
                for(x7=0;x7<16;x7=x7+1)
766 
                        m7.wb_rd_mult( 32'h0000_0700 + ((7+x7) << 28) + (x7<<4), 4'hf, del, 4);
767 
        end
768 
        join
769 
 
770 
        for(x1=0;x1<8;x1=x1+1)
771 
        for(x0=0;x0<16;x0=x0+1)
772 
           begin
773 
                m = x0+x1;
774 
                verify_sub(x1,m,4,(x0*4),(x0*4));
775 
           end
776 
 
777 
   end
778 
 
779 
        show_errors;
780 
        $display("*****************************************************");
781 
        $display("*** Test DONE ...                                 ***");
782 
        $display("*****************************************************\n\n");
783 
 
784 
end
785 
endtask
786 
 
787 
 
788 
task test_rf;
789 
 
790 
integer n, m;
791 
reg     [31:0]   wdata[0:15];
792 
reg     [31:0]   rdata[0:15];
793 
reg     [15:0]   rtmp, wtmp;
794 
 
795 
begin
796 
 
797 
        $display("\n\n");
798 
        $display("*****************************************************");
799 
        $display("*** Register File Test ...                        ***");
800 
        $display("*****************************************************\n");
801 
 
802 
for(m=0;m<5;m=m+1)
803 
   begin
804 
        $display("Mode: %0d", m);
805 
 
806 
        for(n=0;n<16;n=n+1)
807 
                wdata[n] = $random;
808 
 
809 
        for(n=0;n<16;n=n+1)
810 
                case(m)
811 
                   0: m0.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
812 
                   1: m3.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
813 
                   2: m5.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
814 
                   3: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
815 
                   4: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
816 
                endcase
817 
 
818 
        for(n=0;n<16;n=n+1)
819 
                case(m)
820 
                   0: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
821 
                   1: m3.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
822 
                   2: m6.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
823 
                   3: m0.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
824 
                   4: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
825 
                endcase
826 
 
827 
        for(n=0;n<16;n=n+1)
828 
           begin
829 
                rtmp = rdata[n];
830 
                wtmp = wdata[n];
831 
                if(rtmp !== wtmp)
832 
                   begin
833 
                        $display("ERROR: RF[%0d] Mismatch. Expected: %h, Got: %h (%0t)",
834 
                        n, wtmp, rtmp, $time);
835 
                   end
836 
           end
837 
   end
838 
 
839 
        show_errors;
840 
        $display("*****************************************************");
841 
        $display("*** Test DONE ...                                 ***");
842 
        $display("*****************************************************\n\n");
843 
 
844 
 
845 
end
846 
endtask
847 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.