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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 7

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.2 2002-10-03 05:40:03 rudi Exp $
//
//  $Date: 2002-10-03 05:40:03 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/10/19 11:04:23  rudi
//               WISHBONE CONMAX IP Core
//
//
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   mem[mem_size:0];
integer         cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
cnt = 0;
cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
adr = $random;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
adr = $random;
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        //adr = 32'hxxxx_xxxx;
        adr = $random;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
cnt = cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
cnt = cnt + wcount;
end
endtask
 
 
 
 
task wb_wmr;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = mem[n + cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cnt = cnt + wcount;
stb=0;
repeat(delay)   @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
cnt = cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
 
cyc = 0;
stb = 0;
we  = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
//@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
adr = $random;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
adr = $random;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = $random;
end
endtask
 
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
//@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        mem[n + cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        //adr = 32'hxxxx_xxxx;
        adr = $random;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
mem[n + cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hffff_ffff;
//adr = 32'hxxxx_xxxx;
adr = $random;
 
cnt = cnt + count;
end
endtask
 
endmodule

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
13			`//// www.asics.ws ////`
14			`//// rudi@asics.ws ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
22			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
23			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
24			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
25			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
26			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
27			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
28			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
29			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
30			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
31			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
32			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
33			`//// POSSIBILITY OF SUCH DAMAGE. ////`
34			`//// ////`
35			`/////////////////////////////////////////////////////////////////////`
36
37			`// CVS Log`
38			`//`
39			`// $Id: wb_mast_model.v,v 1.2 2002-10-03 05:40:03 rudi Exp $`
40			`//`
41			`// $Date: 2002-10-03 05:40:03 $`
42			`// $Revision: 1.2 $`
43			`// $Author: rudi $`
44			`// $Locker: $`
45			`// $State: Exp $`
46			`//`
47			`// Change History:`
48			`// $Log: not supported by cvs2svn $`
49			`// Revision 1.1.1.1 2001/10/19 11:04:23 rudi`
50			`// WISHBONE CONMAX IP Core`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56
57			`include "wb_model_defines.v"
58
59			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
60
61			`input clk, rst;`
62			`output [31:0] adr;`
63			`input [31:0] din;`
64			`output [31:0] dout;`
65			`output cyc, stb;`
66			`output [3:0] sel;`
67			`output we;`
68			`input ack, err, rty;`
69
70			`////////////////////////////////////////////////////////////////////`
71			`//`
72			`// Local Wires`
73			`//`
74
75			`parameter mem_size = 4096;`
76
77			`reg [31:0] adr;`
78			`reg [31:0] dout;`
79			`reg cyc, stb;`
80			`reg [3:0] sel;`
81			`reg we;`
82
83			`reg [31:0] mem[mem_size:0];`
84			`integer cnt;`
85
86			`////////////////////////////////////////////////////////////////////`
87			`//`
88			`// Memory Logic`
89			`//`
90
91			`initial`
92			`begin`
93			`//adr = 32'hxxxx_xxxx;`
94			`//adr = 0;`
95			`adr = 32'hffff_ffff;`
96			`dout = 32'hxxxx_xxxx;`
97			`cyc = 0;`
98			`stb = 0;`
99			`sel = 4'hx;`
100			`we = 1'hx;`
101			`cnt = 0;`
102			`#1;`
103			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
104			`end`
105
106
107
108			`task mem_fill;`
109
110			`integer n;`
111			`begin`
112			`cnt = 0;`
113			`cnt = 0;`
114			`for(n=0;n<mem_size;n=n+1)`
115			`begin`
116			`mem[n] = $random;`
117			`end`
118			`end`
119			`endtask`
120
121			`////////////////////////////////////////////////////////////////////`
122			`//`
123			`// Write 1 Word Task`
124			`//`
125
126			`task wb_wr1;`
127			`input [31:0] a;`
128			`input [3:0] s;`
129			`input [31:0] d;`
130
131			`begin`
132
133			`//@(posedge clk);`
134			`#1;`
135			`adr = a;`
136			`dout = d;`
137			`cyc = 1;`
138			`stb = 1;`
139			`we=1;`
140			`sel = s;`
141
142			`@(posedge clk);`
143			`while(~ack & ~err) @(posedge clk);`
144			`#1;`
145			`cyc=0;`
146			`stb=0;`
147			`adr = 32'hxxxx_xxxx;`
148			`//adr = 32'hffff_ffff;`
149			`//adr = 0;`
150			`dout = 32'hxxxx_xxxx;`
151			`we = 1'hx;`
152			`sel = 4'hx;`
153			`adr = $random;`
154
155			`end`
156			`endtask`
157
158			`////////////////////////////////////////////////////////////////////`
159			`//`
160			`// Write 4 Words Task`
161			`//`
162
163			`task wb_wr4;`
164			`input [31:0] a;`
165			`input [3:0] s;`
166			`input delay;`
167			`input [31:0] d1;`
168			`input [31:0] d2;`
169			`input [31:0] d3;`
170			`input [31:0] d4;`
171
172			`integer delay;`
173
174			`begin`
175
176			`@(posedge clk);`
177			`#1;`
178			`cyc = 1;`
179			`sel = s;`
180
181			`adr = $random;`
182			`repeat(delay)`
183			`begin`
184			`@(posedge clk);`
185			`#1;`
186			`end`
187			`adr = a;`
188			`dout = d1;`
189			`stb = 1;`
190			`we=1;`
191			`while(~ack & ~err) @(posedge clk);`
192			`#2;`
193			`stb=0;`
194			`we=1'bx;`
195			`dout = 32'hxxxx_xxxx;`
196			`adr = $random;`
197
198
199			`repeat(delay)`
200			`begin`
201			`@(posedge clk);`
202			`#1;`
203			`end`
204			`stb=1;`
205			`adr = a+4;`
206			`dout = d2;`
207			`we=1;`
208			`@(posedge clk);`
209			`while(~ack & ~err) @(posedge clk);`
210			`#2;`
211			`stb=0;`
212			`we=1'bx;`
213			`dout = 32'hxxxx_xxxx;`
214
215			`repeat(delay)`
216			`begin`
217			`@(posedge clk);`
218			`#1;`
219			`end`
220			`stb=1;`
221			`adr = a+8;`
222			`dout = d3;`
223			`we=1;`
224			`@(posedge clk);`
225			`while(~ack & ~err) @(posedge clk);`
226			`#2;`
227			`stb=0;`
228			`we=1'bx;`
229			`dout = 32'hxxxx_xxxx;`
230			`adr = $random;`
231
232			`repeat(delay)`
233			`begin`
234			`@(posedge clk);`
235			`#1;`
236			`end`
237			`stb=1;`
238			`adr = a+12;`
239			`dout = d4;`
240			`we=1;`
241			`@(posedge clk);`
242			`while(~ack & ~err) @(posedge clk);`
243			`#1;`
244			`stb=0;`
245			`cyc=0;`
246
247			`adr = 32'hxxxx_xxxx;`
248			`adr = $random;`
249			`//adr = 0;`
250			`//adr = 32'hffff_ffff;`
251			`dout = 32'hxxxx_xxxx;`
252			`we = 1'hx;`
253			`sel = 4'hx;`
254
255			`end`
256			`endtask`
257
258
259			`task wb_wr_mult;`
260			`input [31:0] a;`
261			`input [3:0] s;`
262			`input delay;`
263			`input count;`
264
265			`integer delay;`
266			`integer count;`
267			`integer n;`
268
269			`begin`
270
271			`//@(posedge clk);`
272			`#1;`
273			`cyc = 1;`
274			`adr = $random;`
275			`for(n=0;n<count;n=n+1)`
276			`begin`
277			`repeat(delay)`
278			`begin`
279			`@(posedge clk);`
280			`#1;`
281			`end`
282			`adr = a + (n*4);`
283			`dout = mem[n + cnt];`
284			`stb = 1;`
285			`we=1;`
286			`sel = s;`
287			`if(n!=0) @(posedge clk);`
288			`while(~ack & ~err) @(posedge clk);`
289			`#2;`
290			`stb=0;`
291			`we=1'bx;`
292			`sel = 4'hx;`
293			`dout = 32'hxxxx_xxxx;`
294			`//adr = 32'hxxxx_xxxx;`
295			`adr = $random;`
296			`end`
297
298			`cyc=0;`
299
300			`adr = 32'hxxxx_xxxx;`
301			`//adr = 32'hffff_ffff;`
302
303			`cnt = cnt + count;`
304			`end`
305			`endtask`
306
307
308			`task wb_rmw;`
309			`input [31:0] a;`
310			`input [3:0] s;`
311			`input delay;`
312			`input rcount;`
313			`input wcount;`
314
315			`integer delay;`
316			`integer rcount;`
317			`integer wcount;`
318			`integer n;`
319
320			`begin`
321
322			`@(posedge clk);`
323			`#1;`
324			`cyc = 1;`
325			`we = 0;`
326			`sel = s;`
327			`repeat(delay) @(posedge clk);`
328
329			`for(n=0;n<rcount-1;n=n+1)`
330			`begin`
331			`adr = a + (n*4);`
332			`stb = 1;`
333			`while(~ack & ~err) @(posedge clk);`
334			`mem[n + cnt] = din;`
335			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
336			`#2;`
337			`stb=0;`
338			`we = 1'hx;`
339			`sel = 4'hx;`
340			`adr = 32'hxxxx_xxxx;`
341			`repeat(delay)`
342			`begin`
343			`@(posedge clk);`
344			`#1;`
345			`end`
346			`we = 0;`
347			`sel = s;`
348			`end`
349
350			`adr = a+(n*4);`
351			`stb = 1;`
352			`@(posedge clk);`
353			`while(~ack & ~err) @(posedge clk);`
354			`mem[n + cnt] = din;`
355			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
356			`#1;`
357			`stb=0;`
358			`we = 1'hx;`
359			`sel = 4'hx;`
360			`adr = 32'hxxxx_xxxx;`
361
362			`cnt = cnt + rcount;`
363
364			`//@(posedge clk);`
365
366
367			`for(n=0;n<wcount;n=n+1)`
368			`begin`
369			`repeat(delay)`
370			`begin`
371			`@(posedge clk);`
372			`#1;`
373			`end`
374			`adr = a + (n*4);`
375			`dout = mem[n + cnt];`
376			`stb = 1;`
377			`we=1;`
378			`sel = s;`
379			`// if(n!=0)`
380			`@(posedge clk);`
381			`while(~ack & ~err) @(posedge clk);`
382			`#2;`
383			`stb=0;`
384			`we=1'bx;`
385			`sel = 4'hx;`
386			`dout = 32'hxxxx_xxxx;`
387			`adr = 32'hxxxx_xxxx;`
388			`end`
389
390			`cyc=0;`
391
392			`adr = 32'hxxxx_xxxx;`
393			`//adr = 32'hffff_ffff;`
394
395			`cnt = cnt + wcount;`
396			`end`
397			`endtask`
398
399
400
401
402			`task wb_wmr;`
403			`input [31:0] a;`
404			`input [3:0] s;`
405			`input delay;`
406			`input rcount;`
407			`input wcount;`
408
409			`integer delay;`
410			`integer rcount;`
411			`integer wcount;`
412			`integer n;`
413
414			`begin`
415
416			`@(posedge clk);`
417			`#1;`
418			`cyc = 1;`
419			`we = 1'bx;`
420			`sel = 4'hx;`
421			`sel = s;`
422
423			`for(n=0;n<wcount;n=n+1)`
424			`begin`
425			`repeat(delay)`
426			`begin`
427			`@(posedge clk);`
428			`#1;`
429			`end`
430			`adr = a + (n*4);`
431			`dout = mem[n + cnt];`
432			`stb = 1;`
433			`we=1;`
434			`sel = s;`
435			`@(posedge clk);`
436			`while(~ack & ~err) @(posedge clk);`
437			`#2;`
438			`stb=0;`
439			`we=1'bx;`
440			`sel = 4'hx;`
441			`dout = 32'hxxxx_xxxx;`
442			`adr = 32'hxxxx_xxxx;`
443			`end`
444
445			`cnt = cnt + wcount;`
446			`stb=0;`
447			`repeat(delay) @(posedge clk);`
448			`#1;`
449
450			`sel = s;`
451			`we = 0;`
452			`for(n=0;n<rcount-1;n=n+1)`
453			`begin`
454			`adr = a + (n*4);`
455			`stb = 1;`
456			`while(~ack & ~err) @(posedge clk);`
457			`mem[n + cnt] = din;`
458			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
459			`#2;`
460			`stb=0;`
461			`we = 1'hx;`
462			`sel = 4'hx;`
463			`adr = 32'hxxxx_xxxx;`
464			`repeat(delay)`
465			`begin`
466			`@(posedge clk);`
467			`#1;`
468			`end`
469			`we = 0;`
470			`sel = s;`
471			`end`
472
473			`adr = a+(n*4);`
474			`stb = 1;`
475			`@(posedge clk);`
476			`while(~ack & ~err) @(posedge clk);`
477			`mem[n + cnt] = din;`
478			`cnt = cnt + rcount;`
479			`//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );`
480			`#1;`
481
482			`cyc = 0;`
483			`stb = 0;`
484			`we = 1'hx;`
485			`sel = 4'hx;`
486			`adr = 32'hxxxx_xxxx;`
487
488			`end`
489			`endtask`
490
491
492
493
494			`////////////////////////////////////////////////////////////////////`
495			`//`
496			`// Read 1 Word Task`
497			`//`
498
499			`task wb_rd1;`
500			`input [31:0] a;`
501			`input [3:0] s;`
502			`output [31:0] d;`
503
504			`begin`
505
506			`//@(posedge clk);`
507			`#1;`
508			`adr = a;`
509			`cyc = 1;`
510			`stb = 1;`
511			`we = 0;`
512			`sel = s;`
513
514			`//@(posedge clk);`
515			`while(~ack & ~err) @(posedge clk);`
516			`d = din;`
517			`#1;`
518			`cyc=0;`
519			`stb=0;`
520			`//adr = 32'hxxxx_xxxx;`
521			`//adr = 0;`
522			`adr = 32'hffff_ffff;`
523			`dout = 32'hxxxx_xxxx;`
524			`we = 1'hx;`
525			`sel = 4'hx;`
526			`adr = $random;`
527
528			`end`
529			`endtask`
530
531
532			`////////////////////////////////////////////////////////////////////`
533			`//`
534			`// Read 4 Words Task`
535			`//`
536
537
538			`task wb_rd4;`
539			`input [31:0] a;`
540			`input [3:0] s;`
541			`input delay;`
542			`output [31:0] d1;`
543			`output [31:0] d2;`
544			`output [31:0] d3;`
545			`output [31:0] d4;`
546
547			`integer delay;`
548			`begin`
549
550			`@(posedge clk);`
551			`#1;`
552			`cyc = 1;`
553			`we = 0;`
554			`adr = $random;`
555			`sel = s;`
556			`repeat(delay) @(posedge clk);`
557
558			`adr = a;`
559			`stb = 1;`
560			`while(~ack & ~err) @(posedge clk);`
561			`d1 = din;`
562			`#2;`
563			`stb=0;`
564			`we = 1'hx;`
565			`sel = 4'hx;`
566			`adr = $random;`
567			`repeat(delay)`
568			`begin`
569			`@(posedge clk);`
570			`#1;`
571			`end`
572			`we = 0;`
573			`sel = s;`
574
575			`adr = a+4;`
576			`stb = 1;`
577			`@(posedge clk);`
578			`while(~ack & ~err) @(posedge clk);`
579			`d2 = din;`
580			`#2;`
581			`stb=0;`
582			`we = 1'hx;`
583			`sel = 4'hx;`
584			`adr = $random;`
585			`repeat(delay)`
586			`begin`
587			`@(posedge clk);`
588			`#1;`
589			`end`
590			`we = 0;`
591			`sel = s;`
592
593
594			`adr = a+8;`
595			`stb = 1;`
596			`@(posedge clk);`
597			`while(~ack & ~err) @(posedge clk);`
598			`d3 = din;`
599			`#2;`
600			`stb=0;`
601			`we = 1'hx;`
602			`sel = 4'hx;`
603			`adr = $random;`
604			`repeat(delay)`
605			`begin`
606			`@(posedge clk);`
607			`#1;`
608			`end`
609			`we = 0;`
610			`sel = s;`
611
612			`adr = a+12;`
613			`stb = 1;`
614			`@(posedge clk);`
615			`while(~ack & ~err) @(posedge clk);`
616			`d4 = din;`
617			`#1;`
618			`stb=0;`
619			`cyc=0;`
620			`we = 1'hx;`
621			`sel = 4'hx;`
622			`adr = 32'hffff_ffff;`
623			`adr = $random;`
624			`end`
625			`endtask`
626
627
628
629			`task wb_rd_mult;`
630			`input [31:0] a;`
631			`input [3:0] s;`
632			`input delay;`
633			`input count;`
634
635			`integer delay;`
636			`integer count;`
637			`integer n;`
638
639			`begin`
640
641			`//@(posedge clk);`
642			`#1;`
643			`cyc = 1;`
644			`we = 0;`
645			`sel = s;`
646			`repeat(delay) @(posedge clk);`
647
648			`for(n=0;n<count-1;n=n+1)`
649			`begin`
650			`adr = a + (n*4);`
651			`stb = 1;`
652			`while(~ack & ~err) @(posedge clk);`
653			`mem[n + cnt] = din;`
654			`#2;`
655			`stb=0;`
656			`we = 1'hx;`
657			`sel = 4'hx;`
658			`//adr = 32'hxxxx_xxxx;`
659			`adr = $random;`
660			`repeat(delay)`
661			`begin`
662			`@(posedge clk);`
663			`#1;`
664			`end`
665			`we = 0;`
666			`sel = s;`
667			`end`
668
669			`adr = a+(n*4);`
670			`stb = 1;`
671			`@(posedge clk);`
672			`while(~ack & ~err) @(posedge clk);`
673			`mem[n + cnt] = din;`
674			`#1;`
675			`stb=0;`
676			`cyc=0;`
677			`we = 1'hx;`
678			`sel = 4'hx;`
679			`//adr = 32'hffff_ffff;`
680			`//adr = 32'hxxxx_xxxx;`
681			`adr = $random;`
682
683			`cnt = cnt + count;`
684			`end`
685			`endtask`
686
687			`endmodule`