URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [rtl/] [verilog/] [wb_conmax_msel.v] - Blame information for rev 7

Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Connection Matrix Master Select                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_conmax_msel.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
//
//  $Date: 2002-10-03 05:40:07 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/10/19 11:01:38  rudi
//               WISHBONE CONMAX IP Core
//
//
//
//
//
 
`include "wb_conmax_defines.v"
 
module wb_conmax_msel(
                clk_i, rst_i,
                conf, req, sel, next
        );
 
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
 
parameter       [1:0]    pri_sel = 2'd0;
 
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
 
input           clk_i, rst_i;
input   [15:0]   conf;
input   [7:0]    req;
output  [2:0]    sel;
input           next;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire    [1:0]    pri0, pri1, pri2, pri3;
wire    [1:0]    pri4, pri5, pri6, pri7;
wire    [1:0]    pri_out_d;
reg     [1:0]    pri_out;
 
wire    [7:0]    req_p0, req_p1, req_p2, req_p3;
wire    [2:0]    gnt_p0, gnt_p1, gnt_p2, gnt_p3;
 
reg     [2:0]    sel1, sel2;
wire    [2:0]    sel;
 
////////////////////////////////////////////////////////////////////
//
// Priority Select logic
//
 
assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0];
assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0;
 
assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2];
assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0;
 
assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4];
assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0;
 
assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6];
assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0;
 
assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8];
assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0;
 
assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10];
assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0;
 
assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12];
assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0;
 
assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14];
assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0;
 
// Priority Encoder
wb_conmax_pri_enc #(pri_sel) pri_enc(
        .valid(         req             ),
        .pri0(          pri0            ),
        .pri1(          pri1            ),
        .pri2(          pri2            ),
        .pri3(          pri3            ),
        .pri4(          pri4            ),
        .pri5(          pri5            ),
        .pri6(          pri6            ),
        .pri7(          pri7            ),
        .pri_out(       pri_out_d       )
        );
 
always @(posedge clk_i)
        if(rst_i)       pri_out <= #1 2'h0;
        else
        if(next)        pri_out <= #1 pri_out_d;
 
////////////////////////////////////////////////////////////////////
//
// Arbiters
//
 
assign req_p0[0] = req[0] & (pri0 == 2'd0);
assign req_p0[1] = req[1] & (pri1 == 2'd0);
assign req_p0[2] = req[2] & (pri2 == 2'd0);
assign req_p0[3] = req[3] & (pri3 == 2'd0);
assign req_p0[4] = req[4] & (pri4 == 2'd0);
assign req_p0[5] = req[5] & (pri5 == 2'd0);
assign req_p0[6] = req[6] & (pri6 == 2'd0);
assign req_p0[7] = req[7] & (pri7 == 2'd0);
 
assign req_p1[0] = req[0] & (pri0 == 2'd1);
assign req_p1[1] = req[1] & (pri1 == 2'd1);
assign req_p1[2] = req[2] & (pri2 == 2'd1);
assign req_p1[3] = req[3] & (pri3 == 2'd1);
assign req_p1[4] = req[4] & (pri4 == 2'd1);
assign req_p1[5] = req[5] & (pri5 == 2'd1);
assign req_p1[6] = req[6] & (pri6 == 2'd1);
assign req_p1[7] = req[7] & (pri7 == 2'd1);
 
assign req_p2[0] = req[0] & (pri0 == 2'd2);
assign req_p2[1] = req[1] & (pri1 == 2'd2);
assign req_p2[2] = req[2] & (pri2 == 2'd2);
assign req_p2[3] = req[3] & (pri3 == 2'd2);
assign req_p2[4] = req[4] & (pri4 == 2'd2);
assign req_p2[5] = req[5] & (pri5 == 2'd2);
assign req_p2[6] = req[6] & (pri6 == 2'd2);
assign req_p2[7] = req[7] & (pri7 == 2'd2);
 
assign req_p3[0] = req[0] & (pri0 == 2'd3);
assign req_p3[1] = req[1] & (pri1 == 2'd3);
assign req_p3[2] = req[2] & (pri2 == 2'd3);
assign req_p3[3] = req[3] & (pri3 == 2'd3);
assign req_p3[4] = req[4] & (pri4 == 2'd3);
assign req_p3[5] = req[5] & (pri5 == 2'd3);
assign req_p3[6] = req[6] & (pri6 == 2'd3);
assign req_p3[7] = req[7] & (pri7 == 2'd3);
 
wb_conmax_arb arb0(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p0          ),
        .gnt(           gnt_p0          ),
        .next(          1'b0            )
        );
 
wb_conmax_arb arb1(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p1          ),
        .gnt(           gnt_p1          ),
        .next(          1'b0            )
        );
 
wb_conmax_arb arb2(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p2          ),
        .gnt(           gnt_p2          ),
        .next(          1'b0            )
        );
 
wb_conmax_arb arb3(
        .clk(           clk_i           ),
        .rst(           rst_i           ),
        .req(           req_p3          ),
        .gnt(           gnt_p3          ),
        .next(          1'b0            )
        );
 
////////////////////////////////////////////////////////////////////
//
// Final Master Select
//
 
always @(pri_out or gnt_p0 or gnt_p1)
        if(pri_out[0])   sel1 = gnt_p1;
        else            sel1 = gnt_p0;
 
 
always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3)
        case(pri_out)
           2'd0: sel2 = gnt_p0;
           2'd1: sel2 = gnt_p1;
           2'd2: sel2 = gnt_p2;
           2'd3: sel2 = gnt_p3;
        endcase
 
 
assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 );
 
endmodule
 

Browse

Tools

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [rtl/] [verilog/] [wb_conmax_msel.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Connection Matrix Master Select ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: wb_conmax_msel.v,v 1.2 2002-10-03 05:40:07 rudi Exp $`
42			`//`
43			`// $Date: 2002-10-03 05:40:07 $`
44			`// $Revision: 1.2 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.1.1.1 2001/10/19 11:01:38 rudi`
52			`// WISHBONE CONMAX IP Core`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			`include "wb_conmax_defines.v"
60
61			`module wb_conmax_msel(`
62			`clk_i, rst_i,`
63			`conf, req, sel, next`
64			`);`
65
66			`////////////////////////////////////////////////////////////////////`
67			`//`
68			`// Module Parameters`
69			`//`
70
71			`parameter [1:0] pri_sel = 2'd0;`
72
73			`////////////////////////////////////////////////////////////////////`
74			`//`
75			`// Module IOs`
76			`//`
77
78			`input clk_i, rst_i;`
79			`input [15:0] conf;`
80			`input [7:0] req;`
81			`output [2:0] sel;`
82			`input next;`
83
84			`////////////////////////////////////////////////////////////////////`
85			`//`
86			`// Local Wires`
87			`//`
88
89			`wire [1:0] pri0, pri1, pri2, pri3;`
90			`wire [1:0] pri4, pri5, pri6, pri7;`
91			`wire [1:0] pri_out_d;`
92			`reg [1:0] pri_out;`
93
94			`wire [7:0] req_p0, req_p1, req_p2, req_p3;`
95			`wire [2:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3;`
96
97			`reg [2:0] sel1, sel2;`
98			`wire [2:0] sel;`
99
100			`////////////////////////////////////////////////////////////////////`
101			`//`
102			`// Priority Select logic`
103			`//`
104
105			`assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0];`
106			`assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0;`
107
108			`assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2];`
109			`assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0;`
110
111			`assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4];`
112			`assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0;`
113
114			`assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6];`
115			`assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0;`
116
117			`assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8];`
118			`assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0;`
119
120			`assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10];`
121			`assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0;`
122
123			`assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12];`
124			`assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0;`
125
126			`assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14];`
127			`assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0;`
128
129			`// Priority Encoder`
130			`wb_conmax_pri_enc #(pri_sel) pri_enc(`
131			`.valid( req ),`
132			`.pri0( pri0 ),`
133			`.pri1( pri1 ),`
134			`.pri2( pri2 ),`
135			`.pri3( pri3 ),`
136			`.pri4( pri4 ),`
137			`.pri5( pri5 ),`
138			`.pri6( pri6 ),`
139			`.pri7( pri7 ),`
140			`.pri_out( pri_out_d )`
141			`);`
142
143			`always @(posedge clk_i)`
144			`if(rst_i) pri_out <= #1 2'h0;`
145			`else`
146			`if(next) pri_out <= #1 pri_out_d;`
147
148			`////////////////////////////////////////////////////////////////////`
149			`//`
150			`// Arbiters`
151			`//`
152
153			`assign req_p0[0] = req[0] & (pri0 == 2'd0);`
154			`assign req_p0[1] = req[1] & (pri1 == 2'd0);`
155			`assign req_p0[2] = req[2] & (pri2 == 2'd0);`
156			`assign req_p0[3] = req[3] & (pri3 == 2'd0);`
157			`assign req_p0[4] = req[4] & (pri4 == 2'd0);`
158			`assign req_p0[5] = req[5] & (pri5 == 2'd0);`
159			`assign req_p0[6] = req[6] & (pri6 == 2'd0);`
160			`assign req_p0[7] = req[7] & (pri7 == 2'd0);`
161
162			`assign req_p1[0] = req[0] & (pri0 == 2'd1);`
163			`assign req_p1[1] = req[1] & (pri1 == 2'd1);`
164			`assign req_p1[2] = req[2] & (pri2 == 2'd1);`
165			`assign req_p1[3] = req[3] & (pri3 == 2'd1);`
166			`assign req_p1[4] = req[4] & (pri4 == 2'd1);`
167			`assign req_p1[5] = req[5] & (pri5 == 2'd1);`
168			`assign req_p1[6] = req[6] & (pri6 == 2'd1);`
169			`assign req_p1[7] = req[7] & (pri7 == 2'd1);`
170
171			`assign req_p2[0] = req[0] & (pri0 == 2'd2);`
172			`assign req_p2[1] = req[1] & (pri1 == 2'd2);`
173			`assign req_p2[2] = req[2] & (pri2 == 2'd2);`
174			`assign req_p2[3] = req[3] & (pri3 == 2'd2);`
175			`assign req_p2[4] = req[4] & (pri4 == 2'd2);`
176			`assign req_p2[5] = req[5] & (pri5 == 2'd2);`
177			`assign req_p2[6] = req[6] & (pri6 == 2'd2);`
178			`assign req_p2[7] = req[7] & (pri7 == 2'd2);`
179
180			`assign req_p3[0] = req[0] & (pri0 == 2'd3);`
181			`assign req_p3[1] = req[1] & (pri1 == 2'd3);`
182			`assign req_p3[2] = req[2] & (pri2 == 2'd3);`
183			`assign req_p3[3] = req[3] & (pri3 == 2'd3);`
184			`assign req_p3[4] = req[4] & (pri4 == 2'd3);`
185			`assign req_p3[5] = req[5] & (pri5 == 2'd3);`
186			`assign req_p3[6] = req[6] & (pri6 == 2'd3);`
187			`assign req_p3[7] = req[7] & (pri7 == 2'd3);`
188
189			`wb_conmax_arb arb0(`
190			`.clk( clk_i ),`
191			`.rst( rst_i ),`
192			`.req( req_p0 ),`
193			`.gnt( gnt_p0 ),`
194			`.next( 1'b0 )`
195			`);`
196
197			`wb_conmax_arb arb1(`
198			`.clk( clk_i ),`
199			`.rst( rst_i ),`
200			`.req( req_p1 ),`
201			`.gnt( gnt_p1 ),`
202			`.next( 1'b0 )`
203			`);`
204
205			`wb_conmax_arb arb2(`
206			`.clk( clk_i ),`
207			`.rst( rst_i ),`
208			`.req( req_p2 ),`
209			`.gnt( gnt_p2 ),`
210			`.next( 1'b0 )`
211			`);`
212
213			`wb_conmax_arb arb3(`
214			`.clk( clk_i ),`
215			`.rst( rst_i ),`
216			`.req( req_p3 ),`
217			`.gnt( gnt_p3 ),`
218			`.next( 1'b0 )`
219			`);`
220
221			`////////////////////////////////////////////////////////////////////`
222			`//`
223			`// Final Master Select`
224			`//`
225
226			`always @(pri_out or gnt_p0 or gnt_p1)`
227			`if(pri_out[0]) sel1 = gnt_p1;`
228			`else sel1 = gnt_p0;`
229
230
231			`always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3)`
232			`case(pri_out)`
233			`2'd0: sel2 = gnt_p0;`
234			`2'd1: sel2 = gnt_p1;`
235			`2'd2: sel2 = gnt_p2;`
236			`2'd3: sel2 = gnt_p3;`
237			`endcase`
238
239
240			`assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 );`
241
242			`endmodule`
243