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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [rtl/] [verilog/] [wb_conmax_rf.v] - Blame information for rev 7

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Connection Matrix Register File                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_conmax_rf.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
//
//  $Date: 2002-10-03 05:40:07 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/10/19 11:01:42  rudi
//               WISHBONE CONMAX IP Core
//
//
//
//
//
 
`include "wb_conmax_defines.v"
 
module wb_conmax_rf(
                clk_i, rst_i,
 
                // Internal Wishbone Interface
                i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,
                i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,
 
                // External Wishbone Interface
                e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,
                e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,
 
                // Configuration Registers
                conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,
                conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15
 
                );
 
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
 
parameter       [3:0]    rf_addr = 4'hf;
parameter               dw      = 32;           // Data bus Width
parameter               aw      = 32;           // Address bus Width
parameter               sw      = dw / 8;       // Number of Select Lines
 
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
 
input           clk_i, rst_i;
 
// Internal Wishbone Interface
input   [dw-1:0] i_wb_data_i;
output  [dw-1:0] i_wb_data_o;
input   [aw-1:0] i_wb_addr_i;
input   [sw-1:0] i_wb_sel_i;
input                   i_wb_we_i;
input                   i_wb_cyc_i;
input                   i_wb_stb_i;
output                  i_wb_ack_o;
output                  i_wb_err_o;
output                  i_wb_rty_o;
 
// External Wishbone Interface
input   [dw-1:0] e_wb_data_i;
output  [dw-1:0] e_wb_data_o;
output  [aw-1:0] e_wb_addr_o;
output  [sw-1:0] e_wb_sel_o;
output                  e_wb_we_o;
output                  e_wb_cyc_o;
output                  e_wb_stb_o;
input                   e_wb_ack_i;
input                   e_wb_err_i;
input                   e_wb_rty_i;
 
// Configuration Registers
output  [15:0]           conf0;
output  [15:0]           conf1;
output  [15:0]           conf2;
output  [15:0]           conf3;
output  [15:0]           conf4;
output  [15:0]           conf5;
output  [15:0]           conf6;
output  [15:0]           conf7;
output  [15:0]           conf8;
output  [15:0]           conf9;
output  [15:0]           conf10;
output  [15:0]           conf11;
output  [15:0]           conf12;
output  [15:0]           conf13;
output  [15:0]           conf14;
output  [15:0]           conf15;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [15:0]   conf0, conf1, conf2, conf3, conf4, conf5;
reg     [15:0]   conf6, conf7, conf8, conf9, conf10, conf11;
reg     [15:0]   conf12, conf13, conf14, conf15;
 
//synopsys infer_multibit "conf0"
//synopsys infer_multibit "conf1"
//synopsys infer_multibit "conf2"
//synopsys infer_multibit "conf3"
//synopsys infer_multibit "conf4"
//synopsys infer_multibit "conf5"
//synopsys infer_multibit "conf6"
//synopsys infer_multibit "conf7"
//synopsys infer_multibit "conf8"
//synopsys infer_multibit "conf9"
//synopsys infer_multibit "conf10"
//synopsys infer_multibit "conf11"
//synopsys infer_multibit "conf12"
//synopsys infer_multibit "conf13"
//synopsys infer_multibit "conf14"
//synopsys infer_multibit "conf15"
 
wire            rf_sel;
reg     [15:0]   rf_dout;
reg             rf_ack;
reg             rf_we;
 
////////////////////////////////////////////////////////////////////
//
// Register File Select Logic
//
 
assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);
 
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
 
always @(posedge clk_i)
        rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;
 
always @(posedge clk_i)
        rf_ack <= #1 rf_sel & !rf_ack;
 
// Writre Logic
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf0 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd0) )         conf0 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf1 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd1) )         conf1 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf2 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd2) )         conf2 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf3 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd3) )         conf3 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf4 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd4) )         conf4 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf5 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd5) )         conf5 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf6 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd6) )         conf6 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf7 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd7) )         conf7 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf8 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd8) )         conf8 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf9 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd9) )         conf9 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf10 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd10) )        conf10 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf11 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd11) )        conf11 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf12 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd12) )        conf12 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf13 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd13) )        conf13 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf14 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd14) )        conf14 <= #1 i_wb_data_i[15:0];
 
always @(posedge clk_i or posedge rst_i)
        if(rst_i)                                       conf15 <= #1 16'h0;
        else
        if(rf_we & (i_wb_addr_i[5:2] == 4'd15) )        conf15 <= #1 i_wb_data_i[15:0];
 
// Read Logic
always @(posedge clk_i)
        if(!rf_sel)     rf_dout <= #1 16'h0;
        else
        case(i_wb_addr_i[5:2])
           4'd0:        rf_dout <= #1 conf0;
           4'd1:        rf_dout <= #1 conf1;
           4'd2:        rf_dout <= #1 conf2;
           4'd3:        rf_dout <= #1 conf3;
           4'd4:        rf_dout <= #1 conf4;
           4'd5:        rf_dout <= #1 conf5;
           4'd6:        rf_dout <= #1 conf6;
           4'd7:        rf_dout <= #1 conf7;
           4'd8:        rf_dout <= #1 conf8;
           4'd9:        rf_dout <= #1 conf9;
           4'd10:       rf_dout <= #1 conf10;
           4'd11:       rf_dout <= #1 conf11;
           4'd12:       rf_dout <= #1 conf12;
           4'd13:       rf_dout <= #1 conf13;
           4'd14:       rf_dout <= #1 conf14;
           4'd15:       rf_dout <= #1 conf15;
        endcase
 
////////////////////////////////////////////////////////////////////
//
// Register File By-Pass Logic
//
 
assign e_wb_addr_o = i_wb_addr_i;
assign e_wb_sel_o  = i_wb_sel_i;
assign e_wb_data_o = i_wb_data_i;
 
assign e_wb_cyc_o  = rf_sel ? 1'b0 : i_wb_cyc_i;
assign e_wb_stb_o  = i_wb_stb_i;
assign e_wb_we_o   = i_wb_we_i;
 
assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;
assign i_wb_ack_o  = rf_sel ? rf_ack  : e_wb_ack_i;
assign i_wb_err_o  = rf_sel ? 1'b0    : e_wb_err_i;
assign i_wb_rty_o  = rf_sel ? 1'b0    : e_wb_rty_i;
 
endmodule

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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [rtl/] [verilog/] [wb_conmax_rf.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	parrado	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Connection Matrix Register File ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: wb_conmax_rf.v,v 1.2 2002-10-03 05:40:07 rudi Exp $`
42			`//`
43			`// $Date: 2002-10-03 05:40:07 $`
44			`// $Revision: 1.2 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.1.1.1 2001/10/19 11:01:42 rudi`
52			`// WISHBONE CONMAX IP Core`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			`include "wb_conmax_defines.v"
60
61			`module wb_conmax_rf(`
62			`clk_i, rst_i,`
63
64			`// Internal Wishbone Interface`
65			`i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,`
66			`i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,`
67
68			`// External Wishbone Interface`
69			`e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,`
70			`e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,`
71
72			`// Configuration Registers`
73			`conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,`
74			`conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15`
75
76			`);`
77
78			`////////////////////////////////////////////////////////////////////`
79			`//`
80			`// Module Parameters`
81			`//`
82
83			`parameter [3:0] rf_addr = 4'hf;`
84			`parameter dw = 32; // Data bus Width`
85			`parameter aw = 32; // Address bus Width`
86			`parameter sw = dw / 8; // Number of Select Lines`
87
88			`////////////////////////////////////////////////////////////////////`
89			`//`
90			`// Module IOs`
91			`//`
92
93			`input clk_i, rst_i;`
94
95			`// Internal Wishbone Interface`
96			`input [dw-1:0] i_wb_data_i;`
97			`output [dw-1:0] i_wb_data_o;`
98			`input [aw-1:0] i_wb_addr_i;`
99			`input [sw-1:0] i_wb_sel_i;`
100			`input i_wb_we_i;`
101			`input i_wb_cyc_i;`
102			`input i_wb_stb_i;`
103			`output i_wb_ack_o;`
104			`output i_wb_err_o;`
105			`output i_wb_rty_o;`
106
107			`// External Wishbone Interface`
108			`input [dw-1:0] e_wb_data_i;`
109			`output [dw-1:0] e_wb_data_o;`
110			`output [aw-1:0] e_wb_addr_o;`
111			`output [sw-1:0] e_wb_sel_o;`
112			`output e_wb_we_o;`
113			`output e_wb_cyc_o;`
114			`output e_wb_stb_o;`
115			`input e_wb_ack_i;`
116			`input e_wb_err_i;`
117			`input e_wb_rty_i;`
118
119			`// Configuration Registers`
120			`output [15:0] conf0;`
121			`output [15:0] conf1;`
122			`output [15:0] conf2;`
123			`output [15:0] conf3;`
124			`output [15:0] conf4;`
125			`output [15:0] conf5;`
126			`output [15:0] conf6;`
127			`output [15:0] conf7;`
128			`output [15:0] conf8;`
129			`output [15:0] conf9;`
130			`output [15:0] conf10;`
131			`output [15:0] conf11;`
132			`output [15:0] conf12;`
133			`output [15:0] conf13;`
134			`output [15:0] conf14;`
135			`output [15:0] conf15;`
136
137			`////////////////////////////////////////////////////////////////////`
138			`//`
139			`// Local Wires`
140			`//`
141
142			`reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5;`
143			`reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11;`
144			`reg [15:0] conf12, conf13, conf14, conf15;`
145
146			`//synopsys infer_multibit "conf0"`
147			`//synopsys infer_multibit "conf1"`
148			`//synopsys infer_multibit "conf2"`
149			`//synopsys infer_multibit "conf3"`
150			`//synopsys infer_multibit "conf4"`
151			`//synopsys infer_multibit "conf5"`
152			`//synopsys infer_multibit "conf6"`
153			`//synopsys infer_multibit "conf7"`
154			`//synopsys infer_multibit "conf8"`
155			`//synopsys infer_multibit "conf9"`
156			`//synopsys infer_multibit "conf10"`
157			`//synopsys infer_multibit "conf11"`
158			`//synopsys infer_multibit "conf12"`
159			`//synopsys infer_multibit "conf13"`
160			`//synopsys infer_multibit "conf14"`
161			`//synopsys infer_multibit "conf15"`
162
163			`wire rf_sel;`
164			`reg [15:0] rf_dout;`
165			`reg rf_ack;`
166			`reg rf_we;`
167
168			`////////////////////////////////////////////////////////////////////`
169			`//`
170			`// Register File Select Logic`
171			`//`
172
173			`assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);`
174
175			`////////////////////////////////////////////////////////////////////`
176			`//`
177			`// Register File Logic`
178			`//`
179
180			`always @(posedge clk_i)`
181			`rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;`
182
183			`always @(posedge clk_i)`
184			`rf_ack <= #1 rf_sel & !rf_ack;`
185
186			`// Writre Logic`
187			`always @(posedge clk_i or posedge rst_i)`
188			`if(rst_i) conf0 <= #1 16'h0;`
189			`else`
190			`if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0];`
191
192			`always @(posedge clk_i or posedge rst_i)`
193			`if(rst_i) conf1 <= #1 16'h0;`
194			`else`
195			`if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0];`
196
197			`always @(posedge clk_i or posedge rst_i)`
198			`if(rst_i) conf2 <= #1 16'h0;`
199			`else`
200			`if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0];`
201
202			`always @(posedge clk_i or posedge rst_i)`
203			`if(rst_i) conf3 <= #1 16'h0;`
204			`else`
205			`if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0];`
206
207			`always @(posedge clk_i or posedge rst_i)`
208			`if(rst_i) conf4 <= #1 16'h0;`
209			`else`
210			`if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0];`
211
212			`always @(posedge clk_i or posedge rst_i)`
213			`if(rst_i) conf5 <= #1 16'h0;`
214			`else`
215			`if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0];`
216
217			`always @(posedge clk_i or posedge rst_i)`
218			`if(rst_i) conf6 <= #1 16'h0;`
219			`else`
220			`if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0];`
221
222			`always @(posedge clk_i or posedge rst_i)`
223			`if(rst_i) conf7 <= #1 16'h0;`
224			`else`
225			`if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0];`
226
227			`always @(posedge clk_i or posedge rst_i)`
228			`if(rst_i) conf8 <= #1 16'h0;`
229			`else`
230			`if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0];`
231
232			`always @(posedge clk_i or posedge rst_i)`
233			`if(rst_i) conf9 <= #1 16'h0;`
234			`else`
235			`if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0];`
236
237			`always @(posedge clk_i or posedge rst_i)`
238			`if(rst_i) conf10 <= #1 16'h0;`
239			`else`
240			`if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0];`
241
242			`always @(posedge clk_i or posedge rst_i)`
243			`if(rst_i) conf11 <= #1 16'h0;`
244			`else`
245			`if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0];`
246
247			`always @(posedge clk_i or posedge rst_i)`
248			`if(rst_i) conf12 <= #1 16'h0;`
249			`else`
250			`if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0];`
251
252			`always @(posedge clk_i or posedge rst_i)`
253			`if(rst_i) conf13 <= #1 16'h0;`
254			`else`
255			`if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0];`
256
257			`always @(posedge clk_i or posedge rst_i)`
258			`if(rst_i) conf14 <= #1 16'h0;`
259			`else`
260			`if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0];`
261
262			`always @(posedge clk_i or posedge rst_i)`
263			`if(rst_i) conf15 <= #1 16'h0;`
264			`else`
265			`if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0];`
266
267			`// Read Logic`
268			`always @(posedge clk_i)`
269			`if(!rf_sel) rf_dout <= #1 16'h0;`
270			`else`
271			`case(i_wb_addr_i[5:2])`
272			`4'd0: rf_dout <= #1 conf0;`
273			`4'd1: rf_dout <= #1 conf1;`
274			`4'd2: rf_dout <= #1 conf2;`
275			`4'd3: rf_dout <= #1 conf3;`
276			`4'd4: rf_dout <= #1 conf4;`
277			`4'd5: rf_dout <= #1 conf5;`
278			`4'd6: rf_dout <= #1 conf6;`
279			`4'd7: rf_dout <= #1 conf7;`
280			`4'd8: rf_dout <= #1 conf8;`
281			`4'd9: rf_dout <= #1 conf9;`
282			`4'd10: rf_dout <= #1 conf10;`
283			`4'd11: rf_dout <= #1 conf11;`
284			`4'd12: rf_dout <= #1 conf12;`
285			`4'd13: rf_dout <= #1 conf13;`
286			`4'd14: rf_dout <= #1 conf14;`
287			`4'd15: rf_dout <= #1 conf15;`
288			`endcase`
289
290			`////////////////////////////////////////////////////////////////////`
291			`//`
292			`// Register File By-Pass Logic`
293			`//`
294
295			`assign e_wb_addr_o = i_wb_addr_i;`
296			`assign e_wb_sel_o = i_wb_sel_i;`
297			`assign e_wb_data_o = i_wb_data_i;`
298
299			`assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i;`
300			`assign e_wb_stb_o = i_wb_stb_i;`
301			`assign e_wb_we_o = i_wb_we_i;`
302
303			`assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;`
304			`assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i;`
305			`assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i;`
306			`assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i;`
307
308			`endmodule`