URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [sim/] [rtl_sim/] [bin/] [Makefile] - Blame information for rev 7

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Line No.	Rev	Author	Line
1	7	parrado
2			`all: sim`
3
4			`SHELL = /bin/sh`
5			`MS=-s`
6
7			`##########################################################################`
8			`#`
9			`# DUT Sources`
10			`#`
11			`##########################################################################`
12			`DUT_SRC_DIR=../../../rtl/verilog`
13			`_TARGETS_= $(DUT_SRC_DIR)/wb_conmax_top.v \`
14			`$(DUT_SRC_DIR)/wb_conmax_slave_if.v \`
15			`$(DUT_SRC_DIR)/wb_conmax_master_if.v \`
16			`$(DUT_SRC_DIR)/wb_conmax_msel.v \`
17			`$(DUT_SRC_DIR)/wb_conmax_arb.v \`
18			`$(DUT_SRC_DIR)/wb_conmax_pri_enc.v \`
19			`$(DUT_SRC_DIR)/wb_conmax_pri_dec.v \`
20			`$(DUT_SRC_DIR)/wb_conmax_rf.v`
21
22
23			`##########################################################################`
24			`#`
25			`# Test Bench Sources`
26			`#`
27			`##########################################################################`
28			`_TOP_=test`
29			`TB_SRC_DIR=../../../bench/verilog`
30			`_TB_= $(TB_SRC_DIR)/test_bench_top.v \`
31			`$(TB_SRC_DIR)/wb_slv_model.v \`
32			`$(TB_SRC_DIR)/wb_mast_model.v`
33
34			`##########################################################################`
35			`#`
36			`# Misc Variables`
37			`#`
38			`##########################################################################`
39
40			`INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/`
41			`LOGF=-l .nclog`
42			`UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v`
43			`GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v`
44
45			`##########################################################################`
46			`#`
47			`# Make Targets`
48			`#`
49			`##########################################################################`
50
51			`ss:`
52			`signalscan -do waves/waves.do -waves waves/waves.trn &`
53
54			`simxl:`
55			`verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \`
56			`$(_TARGETS_) $(_TB_)`
57
58			`simw:`
59			`@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"`
60
61
62			`sim:`
63			`ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \`
64			`$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \`
65			+ncuid+`hostname`
66
67			`gatew:`
68			`@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"`
69
70			`gate:`
71			`ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \`
72			`$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \`
73			$(LOGF) +ncstatus +ncuid+`hostname`
74
75			`hal:`
76			`@echo ""`
77			`@echo "----- Running HAL ... ----------"`
78			`@hal -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \`
79			`+incdir+$(DUT_SRC_DIR) $(_TARGETS_)`
80			`@echo "----- DONE ... ----------"`
81
82			`clean:`
83			`rm -rf ./waves/.dsn ./waves/.trn \`
84			`ncwork/inc* ncwork/.inc* \`
85			`./verilog.* .nclog hal.log`
86
87			`##########################################################################`
88

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Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [trunk/] [sim/] [rtl_sim/] [bin/] [Makefile] - Blame information for rev 7