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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [BF2I.vhd] - Blame information for rev 5

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--Butterfly stage type 1 
--7/17/02  
 
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity BF2I is
 
generic (
        data_width :  INTEGER :=13;
        add_g : INTEGER :=1
        );
 
port    (
        fromreg_r :in std_logic_vector(data_width-1 downto 0);
        fromreg_i :in std_logic_vector(data_width-1 downto 0);
    prvs_r :in std_logic_vector(data_width-1-add_g downto 0);
        prvs_i :in std_logic_vector(data_width-1-add_g downto 0);
        s : in std_logic;
    toreg_r :out std_logic_vector(data_width-1 downto 0);
    toreg_i :out std_logic_vector(data_width-1 downto 0);
    tonext_r :out std_logic_vector(data_width-1 downto 0);
    tonext_i :out std_logic_vector(data_width-1 downto 0)
  );
 
end BF2I;
 
architecture behavior of  BF2I is
signal prvs_ext_r :  std_logic_vector(data_width-1 downto 0);
signal prvs_ext_i  : std_logic_vector(data_width-1 downto 0);
signal add1_out : std_logic_vector(data_width downto 0);
signal add2_out : std_logic_vector(data_width downto 0);
signal sub1_out : std_logic_vector(data_width downto 0);
signal sub2_out : std_logic_vector(data_width downto 0);
 
component adder
 generic (
        inst_width:integer
        );
        port(
             inst_A : in std_logic_vector(data_width-1 downto 0);
             inst_B : in std_logic_vector(data_width-1 downto 0);
             SUM : out std_logic_vector(data_width downto 0)
             );
end component;
 
component subtract
 generic (
        inst_width:integer
        );
        port(
            inst_A : in std_logic_vector(data_width-1 downto 0);
             inst_B : in std_logic_vector(data_width-1 downto  0);
            DIFF : out std_logic_vector(data_width downto 0)
            );
end component;
 
component mux2_mmw
 generic (data_width:integer);
  port(
        s : in std_logic;
        in0: in std_logic_vector(data_width-1 downto 0);
    in1: in std_logic_vector(data_width downto 0);
        data: out std_logic_vector(data_width-1 downto 0)
    );
end component;
 
begin
 
     add1 : adder
  generic map (
inst_width=>data_width
        )
     port map (
                inst_A=>prvs_ext_r,
                inst_B=>fromreg_r,
                SUM=>add1_out
                );
 
  add2 : adder
  generic map (
                inst_width=>data_width
)
     port map (
                inst_A=>prvs_ext_i,
                inst_B=>fromreg_i,
                SUM=>add2_out
                );
 
  sub1 : subtract
  generic map (
                inst_width=>data_width
                )
  port map (
        inst_A=>fromreg_r,
        inst_B=>prvs_ext_r,
        DIFF=>sub1_out
        );
 
  sub2 : subtract
  generic map (
        inst_width=>data_width
        )
  port map (
        inst_A=>fromreg_i,
        inst_B=>prvs_ext_i,
        DIFF=>sub2_out
        );
 
  mux_1 : mux2_mmw
     generic map (
                data_width=>data_width
                )
  port map (
                s=>s,
                in0=>fromreg_r,
                in1=>add1_out,
                data=>tonext_r
                );
 
  mux_2 : mux2_mmw
  generic map (
        data_width=>data_width
        )
  port map (
        s=>s,
        in0=>fromreg_i,
        in1=>add2_out,
        data=>tonext_i
        );
 
  mux_3 : mux2_mmw
  generic map (
        data_width=>data_width
        )
  port map (
                s=>s,
                in0=>prvs_ext_r,
                in1=>sub1_out,
                data=>toreg_r
                );
 
  mux_4 : mux2_mmw
  generic map (
        data_width=>data_width
        )
  port map (
                s=>s,
                in0=>prvs_ext_i,
                in1=>sub2_out,
                data=>toreg_i);
 
process(prvs_r, prvs_i)
begin
     if add_g=1 then
       prvs_ext_r <= prvs_r(data_width-2) &  prvs_r;
       prvs_ext_i <= prvs_i(data_width-2) &  prvs_i;
 else
   prvs_ext_r <=  prvs_r;
    prvs_ext_i <= prvs_i;
 end if;
end process;
 
end;
 

Line No.	Rev	Author	Line
1	5	parrado
2			`--Butterfly stage type 1`
3			`--7/17/02`
4
5			`library IEEE;`
6			`use IEEE.std_logic_1164.all;`
7			`use ieee.std_logic_arith.all;`
8
9			`entity BF2I is`
10
11			`generic (`
12			`data_width : INTEGER :=13;`
13			`add_g : INTEGER :=1`
14			`);`
15
16			`port (`
17			`fromreg_r :in std_logic_vector(data_width-1 downto 0);`
18			`fromreg_i :in std_logic_vector(data_width-1 downto 0);`
19			`prvs_r :in std_logic_vector(data_width-1-add_g downto 0);`
20			`prvs_i :in std_logic_vector(data_width-1-add_g downto 0);`
21			`s : in std_logic;`
22			`toreg_r :out std_logic_vector(data_width-1 downto 0);`
23			`toreg_i :out std_logic_vector(data_width-1 downto 0);`
24			`tonext_r :out std_logic_vector(data_width-1 downto 0);`
25			`tonext_i :out std_logic_vector(data_width-1 downto 0)`
26			`);`
27
28			`end BF2I;`
29
30			`architecture behavior of BF2I is`
31			`signal prvs_ext_r : std_logic_vector(data_width-1 downto 0);`
32			`signal prvs_ext_i : std_logic_vector(data_width-1 downto 0);`
33			`signal add1_out : std_logic_vector(data_width downto 0);`
34			`signal add2_out : std_logic_vector(data_width downto 0);`
35			`signal sub1_out : std_logic_vector(data_width downto 0);`
36			`signal sub2_out : std_logic_vector(data_width downto 0);`
37
38			`component adder`
39			`generic (`
40			`inst_width:integer`
41			`);`
42			`port(`
43			`inst_A : in std_logic_vector(data_width-1 downto 0);`
44			`inst_B : in std_logic_vector(data_width-1 downto 0);`
45			`SUM : out std_logic_vector(data_width downto 0)`
46			`);`
47			`end component;`
48
49			`component subtract`
50			`generic (`
51			`inst_width:integer`
52			`);`
53			`port(`
54			`inst_A : in std_logic_vector(data_width-1 downto 0);`
55			`inst_B : in std_logic_vector(data_width-1 downto 0);`
56			`DIFF : out std_logic_vector(data_width downto 0)`
57			`);`
58			`end component;`
59
60			`component mux2_mmw`
61			`generic (data_width:integer);`
62			`port(`
63			`s : in std_logic;`
64			`in0: in std_logic_vector(data_width-1 downto 0);`
65			`in1: in std_logic_vector(data_width downto 0);`
66			`data: out std_logic_vector(data_width-1 downto 0)`
67			`);`
68			`end component;`
69
70			`begin`
71
72			`add1 : adder`
73			`generic map (`
74			`inst_width=>data_width`
75			`)`
76			`port map (`
77			`inst_A=>prvs_ext_r,`
78			`inst_B=>fromreg_r,`
79			`SUM=>add1_out`
80			`);`
81
82			`add2 : adder`
83			`generic map (`
84			`inst_width=>data_width`
85			`)`
86			`port map (`
87			`inst_A=>prvs_ext_i,`
88			`inst_B=>fromreg_i,`
89			`SUM=>add2_out`
90			`);`
91
92			`sub1 : subtract`
93			`generic map (`
94			`inst_width=>data_width`
95			`)`
96			`port map (`
97			`inst_A=>fromreg_r,`
98			`inst_B=>prvs_ext_r,`
99			`DIFF=>sub1_out`
100			`);`
101
102			`sub2 : subtract`
103			`generic map (`
104			`inst_width=>data_width`
105			`)`
106			`port map (`
107			`inst_A=>fromreg_i,`
108			`inst_B=>prvs_ext_i,`
109			`DIFF=>sub2_out`
110			`);`
111
112			`mux_1 : mux2_mmw`
113			`generic map (`
114			`data_width=>data_width`
115			`)`
116			`port map (`
117			`s=>s,`
118			`in0=>fromreg_r,`
119			`in1=>add1_out,`
120			`data=>tonext_r`
121			`);`
122
123			`mux_2 : mux2_mmw`
124			`generic map (`
125			`data_width=>data_width`
126			`)`
127			`port map (`
128			`s=>s,`
129			`in0=>fromreg_i,`
130			`in1=>add2_out,`
131			`data=>tonext_i`
132			`);`
133
134			`mux_3 : mux2_mmw`
135			`generic map (`
136			`data_width=>data_width`
137			`)`
138			`port map (`
139			`s=>s,`
140			`in0=>prvs_ext_r,`
141			`in1=>sub1_out,`
142			`data=>toreg_r`
143			`);`
144
145			`mux_4 : mux2_mmw`
146			`generic map (`
147			`data_width=>data_width`
148			`)`
149			`port map (`
150			`s=>s,`
151			`in0=>prvs_ext_i,`
152			`in1=>sub2_out,`
153			`data=>toreg_i);`
154
155			`process(prvs_r, prvs_i)`
156			`begin`
157			`if add_g=1 then`
158			`prvs_ext_r <= prvs_r(data_width-2) & prvs_r;`
159			`prvs_ext_i <= prvs_i(data_width-2) & prvs_i;`
160			`else`
161			`prvs_ext_r <= prvs_r;`
162			`prvs_ext_i <= prvs_i;`
163			`end if;`
164			`end process;`
165
166			`end;`
167

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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [BF2I.vhd] - Blame information for rev 5