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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [BF2II.vhd] - Blame information for rev 5

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1 5 parrado
--Butterfly stage type 2 
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--7/17/0 2  
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity BF2II is
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generic (   data_width : INTEGER :=13;
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   add_g: INTEGER :=1
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           );
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port    (   fromreg_r :in std_logic_vector(data_width-1 downto
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   fromreg_i :in std_logic_vector(data_width-1 downto
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0) ;
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     prvs_r :in std_logic_vector(data_width-1-add_g downto
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0) ;
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   prvs_i :in std_logic_vector(data_width-1-add_g downto 0);
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   t : in std_logic;
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   s : in std_logic;
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      toreg_r :out std_logic_vector(data_width                        -1 downto 0);
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      toreg_i :out std_logic_vector(data_width                        -1 downto 0);
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    tonext_r :out std_logic_vector(data_width-1 downto 0);
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      tonext_i :out std_logic_vector(data_width-1 downto 0)
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  );
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end BF2II;
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architecture behavior of  BF2II is
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signal prvs_ext_r  : std_logic_vector(data_width-1 downto 0);
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signal prvs_ext_i : std_logic_vector(data_width-1 downto 0);
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signal add1_out : std_logic_vector(data_width downto 0);
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signal add2_out : std_logic_vector(data_width downto 0);
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signal sub1_out : std_logic_vector(data_width downto 0);
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signal sub2_out : std_logic_vector(data_width downto 0);
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signal swapadd  : std_logic_vector(data_width downto 0);
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signal swapsub  : std_logic_vector(data_width downto 0);
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component  adder
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  generic (inst_width:integer);
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        port(
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             inst_A : in std_logic_vector(       data_width-1 downto 0);
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             inst_B : in  std_logic_vector( data_width-1 downto 0);
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             SUM : out std_logic_vector(data_width downto 0)
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                  );
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end component;
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component subtract
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 generic (inst_width:integer);
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         port(
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             inst_A : in std_logic_vector(data_width-1 downto 0);
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             inst_B : in std_logic_vector(data_width-1 downto 0);
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         DIFF : out std_logic_vector(data_width downto 0)
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            );
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end component;
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component mux2_mmw
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 generic (data_width:integer);
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  port(
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   s :  in std_logic;
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       in0:     in std_logic_vector(data_width-1 downto 0);
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      in1: in std_logic_vector(data_width downto 0);
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       data: out std_logic_vector(data_width-1 downto 0)
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                     );
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end component;
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begin
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  add1 : adder
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  generic map (inst_width=>data_width)
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  port map (inst_A=>prvs_ext_r, inst_B=>fromreg_r, SUM=>add1_out);
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  add2 : adder
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  generic map (inst_width=>data_width)
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  port map (inst_A=>prvs_ext_i, inst_B=>fromreg_i, SUM=>add2_out);
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  sub1 : subtract
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  generic map (inst_width=>data_width)
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  port map (inst_A=>fromreg_r, inst_B=>prvs_ext_r, DIFF=>sub1_out);
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  sub2 : subtract
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  generic map (inst_width=>data_width)
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  port map (inst_A=>fromreg_i, inst_B=>prvs_ext_i, DIFF=>sub2_out);
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  mux_1 : mux2_mmw
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  generic map (data_width=>data_width)
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  port map (s=>s, in0=>fromreg_r, in1=>add1_out, data=>tonext_r);
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  mux_2 : mux2_mmw
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  generic map       (data_width=>data_width)
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  port map (s=>s, in0=>fromreg_i, in1=>swapadd, data=>tonext_i);
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  mux_3 : mux2_mmw
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  generic      map (data_width=>data_width)
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     port map (s=>s, in0=>prvs_ext_r, in1=>sub1_out, data=>toreg_r);
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     mux_4 : mux2_mmw
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     generic map (data_width=>data_width)
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     port map (s=>s, in0=>prvs_ext_i, in1=>swapsub, data=>toreg_i);
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process(prvs_r,prvs_i,s,t)
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begin
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     if add_g=1 then
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    if            (t='0' and s='1') then
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      prvs_ext_r <= prvs_i(data_width-2) & prvs_i;
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      prvs_ext_i <= prvs_r(data_width-2) & prvs_r;
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  else
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         prvs_ext_r <=              prvs_r(data_width-2) & prvs_r;
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                     prvs_ext_i <= prvs_i(data_width-2) & prvs_i;
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   end if;
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 else
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    if (t='0' and s='1') then
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    prvs_ext_r <= prvs_i;
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     prvs_ext_i <= prvs_r;
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  else
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   prvs_ext_r <= prvs_r;
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   prvs_ext_i <= prvs_i;
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  end if;
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 end if;
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end process;
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process(add2_out, sub2_out, s, t)
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begin
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  if (t='0' and s='1') then
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  swapadd<=sub2_out;
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  swapsub<=add2_out;
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 else
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  swapadd<=add2_out;
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  swapsub<=sub2_out;
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 end   if;
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end process;
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end;

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