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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [RAM_Memory.vhd] - Blame information for rev 5

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1 5 parrado
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity RAM_Memory is
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generic(
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Add_WordWidth: integer:=10;
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Data_WordWidth: integer:=32
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);
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port(
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 DATi: in   std_logic_vector( Data_WordWidth-1 downto 0 );
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 DATo: out   std_logic_vector( Data_WordWidth-1 downto 0 );
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 ADR_WB: in    std_logic_vector( Add_WordWidth-1 downto 0 );
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 ADR_FFT: in    std_logic_vector( Add_WordWidth-1 downto 0 );
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 W_R: in    std_logic;
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 clk: in std_logic
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 );
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end entity;
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architecture RTL of RAM_Memory is
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type array_aux is array((2**Add_WordWidth)-1 downto 0) of std_logic_vector(Data_WordWidth-1 downto 0);
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signal mem:array_aux;
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signal  reg0: std_logic_vector(Data_WordWidth-1 downto 0);
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begin
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process(clk)
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begin
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        if rising_edge(clk) then
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                        if ( W_R='1') then
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                                        mem(to_integer(unsigned(ADR_FFT)))<=DATi   ;
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                        end if;
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                                --DATo<=reg0;
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        DATo <=  mem(to_integer(unsigned(ADR_WB)));
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        end if;
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end process;
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end architecture;

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