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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [interface_slave_fft.vhd] - Blame information for rev 5

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--use work.fft_pkg.all;
 
entity interface_slave_fft is
generic(
N: integer:=1024;
data_wordwidth: integer:=32;
adress_wordwidth: integer:=32;
reg_control:integer:=0;
reg_data:integer:=4;
reg_status:integer:=8;
reg_memory:integer:=12
 
 
);
port(
 
 
 ACK_O: out   std_logic;--to MASTER
 ADR_I: in    std_logic_vector( adress_wordwidth-1 downto 0 );
 ADR_FFT: in    std_logic_vector( integer(ceil(log2(real(N))))-1 downto 0 );
 DAT_I: in    std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER
 sDAT_I: in    std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE
 DAT_O: out   std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER
 sDAT_O: out   std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE
 STB_I: in    std_logic;--from MASTER
 WE_I: in    std_logic;--from MASTER
 FFT_finish_in: in    std_logic;--from SLAVE    
 FFT_enable: out    std_logic;--to SLAVE        
 enable_in: in    std_logic;--from SLAVE        
 clear_out: out    std_logic;--to SLAVE
 clk: in std_logic
 );
end entity;
 
architecture RTL of interface_slave_fft is
 
component ramsita IS
        PORT
        (
                address         : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
                clock           : IN STD_LOGIC  := '1';
                data            : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                wren            : IN STD_LOGIC ;
                q               : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
        );
END component;
 
component RAM_Memory is
generic(
 
Add_WordWidth: integer;
Data_WordWidth: integer
);
port(
 
 
 DATi: in   std_logic_vector( Data_WordWidth-1 downto 0 );
 DATo: out   std_logic_vector( Data_WordWidth-1 downto 0 );
 ADR_WB: in    std_logic_vector( Add_WordWidth-1 downto 0 );
 ADR_FFT: in    std_logic_vector( Add_WordWidth-1 downto 0 );
 W_R: in    std_logic;
 clk: in std_logic
 
 );
end component;
 
signal OUT_AUX,OUT_AUX1, ZERO:  std_logic_vector( Data_wordwidth-1 downto 0 );
signal ADD_aux:std_logic_vector( integer(ceil(log2(real((N+3)*4))))-1 downto 0 );
 
signal ack_r, ack_w: std_logic;
 
begin
 
        OUT_AUX<=DAT_I;
        ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth));
 
 
 
        ACK_O<=ack_r or ack_w;
 
        --Reconocimiento de escritura sin estado de espera
        ack_w<= '1' when (STB_I='1' and WE_I='1') else '0';
 
 
 
        --Reconocimiento de lectura con 1 estado de espera, caso RAM sincrona
        process(clk)
 
        begin
                if(rising_edge(clk)) then
                        if(STB_I='1' and WE_I='0') then
 
                        ack_r<='1';
                        else
                        ack_r<='0';
 
                        end if;
                end if;
 
                end process;
 
 
   --Se elimina offset para direcciones de lectura de memoria RAM 
        ADD_aux<=std_logic_vector(unsigned(ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0))-(reg_memory));
 
        RAM: RAM_Memory
generic map(
 
Add_WordWidth=>integer(ceil(log2(real(N)))),
Data_WordWidth=>Data_WordWidth
)
port map(
 
 
 DATi=>sDAT_I,
 DATo=>OUT_AUX1,
 --Divide entre cuatro, direcciones alineadas cada 4 bytes
 ADR_WB=>ADD_aux(integer(ceil(log2(real((N)))))+1 downto 2),
 ADR_FFT=>ADR_FFT(integer(ceil(log2(real(N))))-1 downto 0),
 W_R=>enable_in,
 clk=>clk
 );
 
 
   --Decodificador de escritura
        process(ADR_I,STB_I,WE_I,ZERO,OUT_AUX,OUT_AUX1,FFT_finish_in)
        begin
 
 
                         if (WE_I='1' and STB_I='1') then--ESCRIBIR EN FFT
                                        case ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0) is
 
                                                when std_logic_vector(to_unsigned(Reg_control,integer(ceil(log2(real((N+3)*4)))))) =>
                                                                                                                                                                                                                                clear_out<='1';
                                                                                                                                                                                                                                FFT_enable<='1';
                                                                                                                                                                                                                                sDAT_O<=ZERO;
                                                when std_logic_vector(to_unsigned(Reg_data,integer(ceil(log2(real((N+3)*4))))))=>
                                                                                                                                                                                                                          sDAT_O<=OUT_AUX;
                                                                                                                                                                                                                         FFT_enable<='1';
                                                                                                                                                                                                                         clear_out<='0';
 
                                                when OTHERS => sDAT_O<=ZERO;
                                                                                        clear_out<='0';
                                                                                        FFT_enable<='0';
                                           end case;
 
                         else
                                                sDAT_O<=ZERO;
                                                clear_out<='0';
                                                FFT_enable<='0';
                         end if;
 
 
 
        end process;
 
        --Decodificador de lectura
        process(ADR_I,STB_I,WE_I,ZERO,OUT_AUX,OUT_AUX1,FFT_finish_in)
        begin
 
 
 
        if (WE_I='0' and STB_I='1') then
 
 
 
                                        if ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0) = std_logic_vector(to_unsigned(Reg_status,integer(ceil(log2(real((N+3)*4)))))) then
 
                                                                                                                                                                                                DAT_O(0)<=FFT_finish_in;
                                                                                                                                                                                                DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1);
                                                else
                                                                                                                                DAT_O<=OUT_AUX1;
 
                                                end if;
 
                                                else
                                                DAT_O<=ZERO;
                                                        end if;
 
end process;
 
 
 
end architecture;
 
 
 

Line No.	Rev	Author	Line
1	5	parrado	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4			`use ieee.math_real.all;`
5			`--use work.fft_pkg.all;`
6
7			`entity interface_slave_fft is`
8			`generic(`
9			`N: integer:=1024;`
10			`data_wordwidth: integer:=32;`
11			`adress_wordwidth: integer:=32;`
12			`reg_control:integer:=0;`
13			`reg_data:integer:=4;`
14			`reg_status:integer:=8;`
15			`reg_memory:integer:=12`
16
17
18			`);`
19			`port(`
20
21
22			`ACK_O: out std_logic;--to MASTER`
23			`ADR_I: in std_logic_vector( adress_wordwidth-1 downto 0 );`
24			`ADR_FFT: in std_logic_vector( integer(ceil(log2(real(N))))-1 downto 0 );`
25			`DAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER`
26			`sDAT_I: in std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE`
27			`DAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER`
28			`sDAT_O: out std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE`
29			`STB_I: in std_logic;--from MASTER`
30			`WE_I: in std_logic;--from MASTER`
31			`FFT_finish_in: in std_logic;--from SLAVE`
32			`FFT_enable: out std_logic;--to SLAVE`
33			`enable_in: in std_logic;--from SLAVE`
34			`clear_out: out std_logic;--to SLAVE`
35			`clk: in std_logic`
36			`);`
37			`end entity;`
38
39			`architecture RTL of interface_slave_fft is`
40
41			`component ramsita IS`
42			`PORT`
43			`(`
44			`address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);`
45			`clock : IN STD_LOGIC := '1';`
46			`data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);`
47			`wren : IN STD_LOGIC ;`
48			`q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)`
49			`);`
50			`END component;`
51
52			`component RAM_Memory is`
53			`generic(`
54
55			`Add_WordWidth: integer;`
56			`Data_WordWidth: integer`
57			`);`
58			`port(`
59
60
61			`DATi: in std_logic_vector( Data_WordWidth-1 downto 0 );`
62			`DATo: out std_logic_vector( Data_WordWidth-1 downto 0 );`
63			`ADR_WB: in std_logic_vector( Add_WordWidth-1 downto 0 );`
64			`ADR_FFT: in std_logic_vector( Add_WordWidth-1 downto 0 );`
65			`W_R: in std_logic;`
66			`clk: in std_logic`
67
68			`);`
69			`end component;`
70
71			`signal OUT_AUX,OUT_AUX1, ZERO: std_logic_vector( Data_wordwidth-1 downto 0 );`
72			`signal ADD_aux:std_logic_vector( integer(ceil(log2(real((N+3)*4))))-1 downto 0 );`
73
74			`signal ack_r, ack_w: std_logic;`
75
76			`begin`
77
78			`OUT_AUX<=DAT_I;`
79			`ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth));`
80
81
82
83			`ACK_O<=ack_r or ack_w;`
84
85			`--Reconocimiento de escritura sin estado de espera`
86			`ack_w<= '1' when (STB_I='1' and WE_I='1') else '0';`
87
88
89
90			`--Reconocimiento de lectura con 1 estado de espera, caso RAM sincrona`
91			`process(clk)`
92
93			`begin`
94			`if(rising_edge(clk)) then`
95			`if(STB_I='1' and WE_I='0') then`
96
97			`ack_r<='1';`
98			`else`
99			`ack_r<='0';`
100
101			`end if;`
102			`end if;`
103
104			`end process;`
105
106
107			`--Se elimina offset para direcciones de lectura de memoria RAM`
108			`ADD_aux<=std_logic_vector(unsigned(ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0))-(reg_memory));`
109
110			`RAM: RAM_Memory`
111			`generic map(`
112
113			`Add_WordWidth=>integer(ceil(log2(real(N)))),`
114			`Data_WordWidth=>Data_WordWidth`
115			`)`
116			`port map(`
117
118
119			`DATi=>sDAT_I,`
120			`DATo=>OUT_AUX1,`
121			`--Divide entre cuatro, direcciones alineadas cada 4 bytes`
122			`ADR_WB=>ADD_aux(integer(ceil(log2(real((N)))))+1 downto 2),`
123			`ADR_FFT=>ADR_FFT(integer(ceil(log2(real(N))))-1 downto 0),`
124			`W_R=>enable_in,`
125			`clk=>clk`
126			`);`
127
128
129			`--Decodificador de escritura`
130			`process(ADR_I,STB_I,WE_I,ZERO,OUT_AUX,OUT_AUX1,FFT_finish_in)`
131			`begin`
132
133
134			`if (WE_I='1' and STB_I='1') then--ESCRIBIR EN FFT`
135			`case ADR_I(integer(ceil(log2(real((N+3)*4))))-1 downto 0) is`
136
137			`when std_logic_vector(to_unsigned(Reg_control,integer(ceil(log2(real((N+3)*4)))))) =>`
138			`clear_out<='1';`
139			`FFT_enable<='1';`
140			`sDAT_O<=ZERO;`
141			`when std_logic_vector(to_unsigned(Reg_data,integer(ceil(log2(real((N+3)*4))))))=>`
142			`sDAT_O<=OUT_AUX;`
143			`FFT_enable<='1';`
144			`clear_out<='0';`
145
146			`when OTHERS => sDAT_O<=ZERO;`
147			`clear_out<='0';`
148			`FFT_enable<='0';`
149			`end case;`
150
151			`else`
152			`sDAT_O<=ZERO;`
153			`clear_out<='0';`
154			`FFT_enable<='0';`
155			`end if;`
156
157
158
159			`end process;`
160
161			`--Decodificador de lectura`
162			`process(ADR_I,STB_I,WE_I,ZERO,OUT_AUX,OUT_AUX1,FFT_finish_in)`
163			`begin`
164
165
166
167			`if (WE_I='0' and STB_I='1') then`
168
169
170
171			`if ADR_I(integer(ceil(log2(real((N+3)4))))-1 downto 0) = std_logic_vector(to_unsigned(Reg_status,integer(ceil(log2(real((N+3)4)))))) then`
172
173			`DAT_O(0)<=FFT_finish_in;`
174			`DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1);`
175			`else`
176			`DAT_O<=OUT_AUX1;`
177
178			`end if;`
179
180			`else`
181			`DAT_O<=ZERO;`
182			`end if;`
183
184			`end process;`
185
186
187
188			`end architecture;`
189
190
191

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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [interface_slave_fft.vhd] - Blame information for rev 5