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parrado |
-- Rom file for twiddle factors
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-- ../../../rtl/vhdl/WISHBONE_FFT/rom4.vhd contains 16 points of 16 width
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-- for a 1024 point fft.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_arith.ALL;
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ENTITY rom4 IS
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GENERIC(
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data_width : integer :=16;
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address_width : integer :=4
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);
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PORT(
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clk :in std_logic;
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address :in std_logic_vector (3 downto 0);
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datar : OUT std_logic_vector (data_width-1 DOWNTO 0) ;
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datai : OUT std_logic_vector (data_width-1 DOWNTO 0)
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);
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end rom4;
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ARCHITECTURE behavior OF rom4 IS
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BEGIN
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process (address,clk)
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begin
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if(rising_edge(clk)) then
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case address is
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when "0000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when "0001" => datar <= "0101101010000010";datai <= "1010010101111110"; --128
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when "0010" => datar <= "0000000000000000";datai <= "1000000000000001"; --256
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when "0011" => datar <= "1010010101111110";datai <= "1010010101111110"; --384
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when "0100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when "0101" => datar <= "0111011001000001";datai <= "1100111100000101"; --64
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when "0110" => datar <= "0101101010000010";datai <= "1010010101111110"; --128
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when "0111" => datar <= "0011000011111011";datai <= "1000100110111111"; --192
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when "1000" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when "1001" => datar <= "0011000011111011";datai <= "1000100110111111"; --192
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when "1010" => datar <= "1010010101111110";datai <= "1010010101111110"; --384
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when "1011" => datar <= "1000100110111111";datai <= "0011000011111011"; --576
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when "1100" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when "1101" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when "1110" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when "1111" => datar <= "0111111111111111";datai <= "0000000000000000"; --0
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when others => for i in data_width-1 downto 0 loop
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datar(i)<='0';datai(i)<='0';end loop;
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end case;
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end if;
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end process;
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END behavior;
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