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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [shiftreg1.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 5 parrado
 
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-- hds header_start 
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--1 stage shift register, data_width bits wide. 
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_arith.ALL;
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ENTITY shiftreg1 IS
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   GENERIC(
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   data_width : integer := 25
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   );
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    PORT(
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      clock      : IN     std_logic;
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                enable          : in std_logic;
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                clear       : in std_logic;
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      read_data  : OUT    std_logic_vector (data_width-1 DOWNTO 0);
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      write_data : IN     std_logic_vector (data_width-1 DOWNTO 0);
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      resetn     : IN     std_logic
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   );
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-- Declarations 
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END shiftreg1 ;
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-- hds interface_end 
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ARCHITECTURE behavior OF shiftreg1 IS
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--signal reg00 : std_logic_vector(data_width-1 downto 0); 
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BEGIN
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process(Clock,resetn)
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begin
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if (resetn='0') then
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--      for                i in data_width-1 downto 0 loop 
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--    r eg00(i)<='0'; 
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     read_data <= (others => '0');
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--     end loop;  
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  elsif (Clock'event and Clock='1') then
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          if (enable='1') then
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                if(clear ='1') then
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--    reg00<=write_data; 
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--   read _data<=reg00; 
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   read_data <= (others => '0');
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        else
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        read_data  <= write_data;
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  end if;
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  end if;
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  end if;
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end process;
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END behavior;

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