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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [stage_I.vhd] - Blame information for rev 5

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1 5 parrado 
--Component for Stages using BF2I (first and every odd stage)
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--Doesn't handle last stage
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--Input is a standard logic vector of       data_width-add_g
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--data_width - width of the internal busses
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--add_g - Add growth variable - if 1, data      _width grows by   1, if 0 then 0
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-- t_stages number of shift -shif  register stages
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity stage_I is
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generic  (
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                data_width : INTEGER :=13;
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                add_g : INTEGER := 1;
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                shift_stages : INTEGER := 32
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  );
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port  (
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                prvs_r :in std_logic_vector(data_width-1-add_g downto 0);
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                prvs_i :in std_logic_vector(data_width-1-add_g downto 0);
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                s :in std_logic;
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                clock : in std_logic;
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                resetn : in std_logic;
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                enable          : in std_logic;
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                tonext_r :out std_logic_vector(data_width-1 downto 0);
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                tonext_i :out std_logic_vector(data_width-1 downto 0)
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  );
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end stage_I;
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architecture structure of stage_I is
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signal toreg_r : std_logic_vector(data_width-1 downto 0);
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signal toreg_i : std_logic_vector(data_width-1 downto 0);
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signal fromreg_r : std_logic_vector(data_width-1 downto 0);
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signal fromreg_i : std_logic_vector(data_width-1 downto 0);
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signal tonext_r_aux : std_logic_vector(data_width-1 downto 0);
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signal tonext_i_aux : std_logic_vector(data_width-1 downto 0);
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component shiftregN
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  generic (
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                data_width : integer;
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                n : integer
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                );
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  port  (
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                clock : IN std_logic;
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                enable          : in std_logic;
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          read_data  : OUT    std_logic_vector (data_width-1 DOWNTO 0);
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          write_data : IN     std_logic_vector (data_width-1 DOWNTO 0 );
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          resetn     : IN     std_logic
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         );
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end component;
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component shiftreg1
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  generic (
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                data_width : integer
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);
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  port (
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                clock : IN std_logic;
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                enable: in std_logic;
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                clear: in std_logic;
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        read_data  : OUT    std_logic_vector (data_width-1 DOWNTO 0);
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        write_data : IN     std_logic_vector (data_width-1 DOWNTO 0);
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                resetn     : IN     std_logic
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                );
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end component;
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component BF2I
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  generic (
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        data_width : INTEGER;
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        add_g: INTEGER
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        );
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  port    (
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        fromreg_r :in std_logic_vector(data_width-1 downto 0);
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        fromreg_i :in std_logic_vector(data_width-1 downto 0);
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        prvs_r :in std_logic_vector(data_width-add_g-1 downto 0  );
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        prvs_i :in std_logic_vector(data_width-add_g-1 downto 0);
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    s : in std_logic;
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    toreg_r :out std_logic_vector(data_width-1 downto 0);
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    toreg_i :out std_logic_vector(data_width-1 downto 0);
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        tonext_r :out std_logic_vector(data_width-1 downto 0);
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    tonext_i :out std_logic_vector(data_width-1 downto 0)
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    );
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end component;
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begin
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regr : shiftregN
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  generic map (
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        data_width=>data_width,
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        n=>shift_stages
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        )
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  port map (
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clock=>clock,
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enable=>enable,
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read_data=>fromreg_r,
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write_data=>toreg_r,
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resetn=>resetn
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);
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regi : shiftregN
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  generic map (
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        data_width=>data_width,
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        n=>shift_stages
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        )
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port map (
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        clock=>clock,
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        enable=>enable,
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        read_data=>fromreg_i,
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        write_data=>toreg_i,
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        resetn=>resetn
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        );
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btrfly : BF2I
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  generic map (
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        data_width=>data_width,
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        add_g=>add_g
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        )
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  port map (
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        fromreg_r=>fromreg_r,
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        fromreg_i=>fromreg_i,
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    prvs_r=>prvs_r,
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        prvs_i=>prvs_i,
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    s=>s,
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    toreg_r=>toreg_r,
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        toreg_i=>toreg_i,
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    tonext_r=>tonext_r_aux,
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        tonext_i=>tonext_i_aux
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        );
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regsegr : shiftreg1
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  generic map (
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        data_width=>data_width
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        )
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port map (
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        clock=>clock,
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        enable=>'1',
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        clear=>'0',
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        read_data=>tonext_r,
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        write_data=>tonext_r_aux,
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        resetn=>resetn
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        );
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regsegi : shiftreg1
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  generic map (
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        data_width=>data_width
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        )
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port map (
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        clock=>clock,
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        enable=>'1',
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        clear=>'0',
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        read_data=>tonext_i,
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        write_data=>tonext_i_aux,
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        resetn=>resetn
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        );
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end;
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