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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [stage_I_last.vhd] - Blame information for rev 5

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--Component for Stages using BF2I (if BF2I is the last stage) 
--Input is a standard logic vector of data_width-add_g 
--data_width - width of the internal busses 
--add_g - Add growth variable  - if 1, data_width grows by  1, if 0 then 0 
--Only 1 shift stage 
 
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity stage_I_last  is
generic  (
                data_width : INTEGER :=13;
        add_g :            INTEGER := 1
   );
port  (
        prvs_r :in std_logic_vector(data_width-1-add_g downto 0);
    prvs_i :in std_logic_vector(data_width-1-add_g downto 0);
        s :in std_logic;
        clock : in  std_logic;
        enable : in  std_logic;
        resetn : in std_logic;
        tonext_r :out std_logic_vector(data_width-1 downto 0);
    tonext_i :out std_logic_vector(data_width-1 downto 0)
  );
end stage_I_last;
 
architecture structure of stage_I_last is
signal toreg_r : std_logic_vector(data_width-1 downto 0);
signal toreg_i : std_logic_vector(data_width-1 downto 0);
signal fromreg_r :  std_logic_vector(data_width-1 downto 0);
signal fromreg_i: std_logic_vector(data_width -1 downto 0);
 
signal tonext_r_aux : std_logic_vector(data_width-1 downto 0);
signal tonext_i_aux : std_logic_vector(data_width-1 downto 0);
 
component shiftreg1
  generic (
                data_width : integer
);
  port (
                clock : IN std_logic;
                enable : in  std_logic;
                clear : in  std_logic;
        read_data  : OUT    std_logic_vector (data_width-1 DOWNTO 0);
        write_data : IN     std_logic_vector (data_width-1 DOWNTO 0);
                resetn     : IN     std_logic
                );
end component;
 
component BF2I
  generic      (
        data_width : INTEGER;
    add_g: INTEGER
);
  port    (
                fromreg_r :in std_logic_vector(data_width-1 downto 0);
                fromreg_i :in std_logic_vector(data_width -1 downto 0);
                prvs_r :in std_logic_vector(data_width-add_g-1 downto 0) ;
                prvs_i :in std_logic_vector(data_width-add_g-1   downto 0) ;
                s : in std_logic;
                toreg_r :out std_logic_vector(data_width-1 downto 0);
        toreg_i :out std_logic_vector(data_width-1 downto 0);
                tonext_r :out std_logic_vector(data_width-1 downto 0);
                tonext_i :out std_logic_vector( data_width-1 downto 0)
   );
end component;
 
begin
regr : shiftreg1
  generic map (
        data_width=>data_width
        )
  port map (
        clock=>clock,
        enable=>enable,
        clear =>'0',
        read_data=>fromreg_r,
        write_data=>toreg_r,
        resetn=>resetn
        );
regi : shiftreg1
  generic map (
        data_width=>data_width
        )
  port map (
        clock=>clock,
        enable=>enable,
        clear =>'0',
        read_data=>fromreg_i,
        write_data=>toreg_i,
        resetn=>resetn
        );
btrfly : BF2I
     generic map (
        data_width=>data_width,
        add_g=>add_g
        )
  port map (
        fromreg_r=>fromreg_r,
        fromreg_i=>fromreg_i,
    prvs_r=>prvs_r,
        prvs_i=>prvs_i,
    s=>s,
    toreg_r=>toreg_r, toreg_i=>toreg_i,
     tonext_r=>tonext_r_aux,
        tonext_i=>tonext_i_aux
);
 
 
 
regsegr : shiftreg1
  generic map (
        data_width=>data_width
 
        )
port map (
        clock=>clock,
        enable=>'1',
        clear=>'0',
        read_data=>tonext_r,
        write_data=>tonext_r_aux,
        resetn=>resetn
        );
 
regsegi : shiftreg1
  generic map (
        data_width=>data_width
 
        )
port map (
        clock=>clock,
        enable=>'1',
        clear=>'0',
        read_data=>tonext_i,
        write_data=>tonext_i_aux,
        resetn=>resetn
        );
 
 
end;

Line No.	Rev	Author	Line
1	5	parrado	`--Component for Stages using BF2I (if BF2I is the last stage)`
2			`--Input is a standard logic vector of data_width-add_g`
3			`--data_width - width of the internal busses`
4			`--add_g - Add growth variable - if 1, data_width grows by 1, if 0 then 0`
5			`--Only 1 shift stage`
6
7			`library IEEE;`
8			`use IEEE.std_logic_1164.all;`
9			`use ieee.std_logic_arith.all;`
10
11			`entity stage_I_last is`
12			`generic (`
13			`data_width : INTEGER :=13;`
14			`add_g : INTEGER := 1`
15			`);`
16			`port (`
17			`prvs_r :in std_logic_vector(data_width-1-add_g downto 0);`
18			`prvs_i :in std_logic_vector(data_width-1-add_g downto 0);`
19			`s :in std_logic;`
20			`clock : in std_logic;`
21			`enable : in std_logic;`
22			`resetn : in std_logic;`
23			`tonext_r :out std_logic_vector(data_width-1 downto 0);`
24			`tonext_i :out std_logic_vector(data_width-1 downto 0)`
25			`);`
26			`end stage_I_last;`
27
28			`architecture structure of stage_I_last is`
29			`signal toreg_r : std_logic_vector(data_width-1 downto 0);`
30			`signal toreg_i : std_logic_vector(data_width-1 downto 0);`
31			`signal fromreg_r : std_logic_vector(data_width-1 downto 0);`
32			`signal fromreg_i: std_logic_vector(data_width -1 downto 0);`
33
34			`signal tonext_r_aux : std_logic_vector(data_width-1 downto 0);`
35			`signal tonext_i_aux : std_logic_vector(data_width-1 downto 0);`
36
37			`component shiftreg1`
38			`generic (`
39			`data_width : integer`
40			`);`
41			`port (`
42			`clock : IN std_logic;`
43			`enable : in std_logic;`
44			`clear : in std_logic;`
45			`read_data : OUT std_logic_vector (data_width-1 DOWNTO 0);`
46			`write_data : IN std_logic_vector (data_width-1 DOWNTO 0);`
47			`resetn : IN std_logic`
48			`);`
49			`end component;`
50
51			`component BF2I`
52			`generic (`
53			`data_width : INTEGER;`
54			`add_g: INTEGER`
55			`);`
56			`port (`
57			`fromreg_r :in std_logic_vector(data_width-1 downto 0);`
58			`fromreg_i :in std_logic_vector(data_width -1 downto 0);`
59			`prvs_r :in std_logic_vector(data_width-add_g-1 downto 0) ;`
60			`prvs_i :in std_logic_vector(data_width-add_g-1 downto 0) ;`
61			`s : in std_logic;`
62			`toreg_r :out std_logic_vector(data_width-1 downto 0);`
63			`toreg_i :out std_logic_vector(data_width-1 downto 0);`
64			`tonext_r :out std_logic_vector(data_width-1 downto 0);`
65			`tonext_i :out std_logic_vector( data_width-1 downto 0)`
66			`);`
67			`end component;`
68
69			`begin`
70			`regr : shiftreg1`
71			`generic map (`
72			`data_width=>data_width`
73			`)`
74			`port map (`
75			`clock=>clock,`
76			`enable=>enable,`
77			`clear =>'0',`
78			`read_data=>fromreg_r,`
79			`write_data=>toreg_r,`
80			`resetn=>resetn`
81			`);`
82			`regi : shiftreg1`
83			`generic map (`
84			`data_width=>data_width`
85			`)`
86			`port map (`
87			`clock=>clock,`
88			`enable=>enable,`
89			`clear =>'0',`
90			`read_data=>fromreg_i,`
91			`write_data=>toreg_i,`
92			`resetn=>resetn`
93			`);`
94			`btrfly : BF2I`
95			`generic map (`
96			`data_width=>data_width,`
97			`add_g=>add_g`
98			`)`
99			`port map (`
100			`fromreg_r=>fromreg_r,`
101			`fromreg_i=>fromreg_i,`
102			`prvs_r=>prvs_r,`
103			`prvs_i=>prvs_i,`
104			`s=>s,`
105			`toreg_r=>toreg_r, toreg_i=>toreg_i,`
106			`tonext_r=>tonext_r_aux,`
107			`tonext_i=>tonext_i_aux`
108			`);`
109
110
111
112			`regsegr : shiftreg1`
113			`generic map (`
114			`data_width=>data_width`
115
116			`)`
117			`port map (`
118			`clock=>clock,`
119			`enable=>'1',`
120			`clear=>'0',`
121			`read_data=>tonext_r,`
122			`write_data=>tonext_r_aux,`
123			`resetn=>resetn`
124			`);`
125
126			`regsegi : shiftreg1`
127			`generic map (`
128			`data_width=>data_width`
129
130			`)`
131			`port map (`
132			`clock=>clock,`
133			`enable=>'1',`
134			`clear=>'0',`
135			`read_data=>tonext_i,`
136			`write_data=>tonext_i_aux,`
137			`resetn=>resetn`
138			`);`
139
140
141			`end;`

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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FFT/] [stage_I_last.vhd] - Blame information for rev 5