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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_FIR/] [interface_slave_fir.vhd] - Blame information for rev 5

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1 5 parrado 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity interface_slave_fir is
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generic(
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data_wordwidth: integer;
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adress_wordwidth: integer;
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Adr_bas:integer;
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reg_control:integer;
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reg_data:integer;
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reg_status:integer;
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reg_Q:integer;
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reg_coef:integer;
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N_coef:integer;
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M:integer;
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WordWidth_Q:integer--width signal of Q
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);
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port(
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 ACK_O: out   std_logic;--to MASTER
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 ADR_I: in    std_logic_vector( adress_wordwidth-1 downto 0 );
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 DAT_I: in    std_logic_vector( data_wordwidth-1 downto 0 );--from MASTER
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 sDAT_I: in    std_logic_vector( data_wordwidth-1 downto 0 );--from SLAVE
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 DAT_O: out   std_logic_vector( data_wordwidth-1 downto 0 );--to MASTER
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 sDAT_O: out   std_logic_vector( data_wordwidth-1 downto 0 );--to SLAVE
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 STB_I: in    std_logic;--from MASTER
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 WE_I: in    std_logic;--from MASTER
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 Start: out    std_logic;--to SLAVE
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 h0: out std_logic_vector( (N_coef*M)-1 downto 0 );--to SLAVE
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 Q :out std_logic_vector(WordWidth_Q-1 downto 0);
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 clear,reset,clk: in std_logic
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 );
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end entity;
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architecture RTL of interface_slave_fir is
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--The fullregister component
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component fullregister is
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        generic
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        (
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                N: integer
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        );
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        port
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        (
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                clk               : in std_logic;
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                reset_n   : in std_logic;
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                enable    : in std_logic;
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                clear             : in std_logic;
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                d                 : in std_logic_vector(N-1 downto 0);
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                q                 : out std_logic_vector(N-1 downto 0)
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        );
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end component;
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signal OUT_AUX,rSTATUS_O, ZERO:  std_logic_vector( data_wordwidth-1 downto 0 );
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signal ZERO1:  std_logic_vector( WordWidth_Q-1 downto 0 );
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type array_aux is array(N_coef downto 0) of std_logic_vector(M-1 downto 0);
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signal h0_aux:array_aux;
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type array_aux1 is array(N_coef downto 0) of std_logic;
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signal enables:array_aux1;
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begin
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        ZERO<=std_logic_vector(to_unsigned(0,data_wordwidth));
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        ZERO1<=std_logic_vector(to_unsigned(0,WordWidth_Q));
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        OUT_AUX<=DAT_I;
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        ACK_O<=STB_I;
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        DAT_O<=sDAT_I;
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        coefficients:
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                        for k in N_coef-1 downto 0 generate
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                                 enables(k)<='1' when (STB_I='1' and  WE_I='1' and ADR_I(9 downto 0)=std_logic_vector(to_unsigned((4*k)+reg_coef,10))) else
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                                                                        '0';
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                                                coefs:fullregister
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                                                        generic map(
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                                                                                        N=>M
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                                                                                        )
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                                                        port map (
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                                                                                        clk=>clk,
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                                                                                        reset_n=>reset,
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                                                                                        enable=>enables(k),
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                                                                                        clear=>clear,
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                                                                                        d=>OUT_AUX(M-1 downto 0),
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                                                                                        q=>h0_aux(k)
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                                                                                        );
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                                                        h0((k+1)*M-1 downto k*M)<=std_logic_vector(signed(h0_aux(k)));
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                        end generate;
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        process(ADR_I,STB_I,WE_I,ZERO,ZERO1,OUT_AUX,sDAT_I,rSTATUS_O)
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        begin
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                                --if ((ADR_I(adress_wordwidth-1 downto adress_wordwidth-4))=std_logic_vector(to_unsigned(Adr_bas,4))) then
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                                 if (WE_I='1' and STB_I='1') then
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                                                case ADR_I(9 downto 0) is
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                                                                when std_logic_vector(to_unsigned(reg_control,10)) => start<='1';
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                                                                                                                                                                                                                                                        --sDAT_O<=ZERO;
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                                                                                                                                                                                                                                                        --DAT_O<=ZERO;
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                                                                                                                                                                                                                                                        rSTATUS_O<=ZERO;
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                                                                                                                                                                                                                                                        --Q<=ZERO1;
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                                                                when std_logic_vector(to_unsigned(Reg_status,10)) => rSTATUS_O<=std_logic_vector(unsigned(OUT_AUX));
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                                                                                                                                                                                                                                                  --sDAT_O<=ZERO;
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                                                                                                                                                                                                                                                 -- DAT_O<=ZERO;
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                                                                                                                                                                                                                                                  start<='0';
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                                                                                                                                                                                                                                                  --Q<=ZERO1;
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                                                                when OTHERS => --DAT_O<=ZERO;
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                                                                                                        --sDAT_O<=ZERO;
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                                                                                                        start<='0';
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                                                                                                        rSTATUS_O<=ZERO;
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                                                                                                        --Q<=ZERO1;
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                                                 end case;
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--                               elsif (WE_I='0' and STB_I='1') then
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--                                              case ADR_I(4 downto 0) is
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--                                                              when std_logic_vector(to_unsigned(reg_data,5)) => DAT_O<=sDAT_I;
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--                                                                                                                                                                                                                                              --sDAT_O<=ZERO;
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--                                                                                                                                                                                                                                              start<='0';
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--                                                                                                                                                                                                                                              rSTATUS_O<=ZERO;
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--                                                                                                                                                                                                                                              ---Q<=ZERO1;
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--
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--                                                              when std_logic_vector(to_unsigned(Reg_status,5)) => DAT_O<=rSTATUS_O;
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--                                                                                                                                                                                                                                                --sDAT_O<=ZERO;
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--                                                                                                                                                                                                                                                start<='0';
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--                                                                                                                                                                                                                                                rSTATUS_O<=ZERO;
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--                                                                                                                                                                                                                                                --Q<=ZERO1;
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--                                                              when OTHERS => DAT_O<=ZERO;
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--                                                                                                      --sDAT_O<=ZERO;
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--                                                                                                      start<='0';
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--                                                                                                      rSTATUS_O<=ZERO;
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--                                                                                                      --Q<=ZERO1;
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--                                               end case;
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                                        --end if;
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                                 else
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                                        --      DAT_O<=ZERO;
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                                                --sDAT_O<=ZERO;
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                                                start<='0';
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                                                rSTATUS_O<=ZERO;
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                                                --Q<=ZERO1;
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                                 end if;
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        end process;
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        process(ADR_I,STB_I,WE_I,ZERO,ZERO1,OUT_AUX,sDAT_I,rSTATUS_O)
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        begin
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         if rising_edge(clk) then
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                                 if (WE_I='1' and STB_I='1') then
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                                                if ADR_I(9 downto 0)=std_logic_vector(to_unsigned(reg_data,10)) then
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                                                                 sDAT_O<=OUT_AUX;
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                                                end if;
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                                                if ADR_I(9 downto 0)=std_logic_vector(to_unsigned(reg_Q,10)) then
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                                                                 --Q<=OUT_AUX(data_wordwidth-1 downto data_wordwidth-WordWidth_Q);
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                                                                 Q<=OUT_AUX(WordWidth_Q-1 downto 0);
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                                                end if;
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                                 end if;
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                        end if;
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        end process;
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end architecture;
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