URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_IIR/] [SOS.vhd] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log


library ieee;
--library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Structure SOS
entity SOS is
generic (WordWidth:integer;--width signal of in/out
                        Bit_growth:integer;
                        NSECT:integer;--Cant of sections
                        M:integer;--width word of coefs
                        Q:integer--Q--Quantifer
 
                        );
 
port(
 
signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);
h0: in std_logic_vector((NSECT*M*6)-1 downto 0);
gain: in std_logic_vector(M-1 downto 0);
signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);
en_out : in std_logic_vector(3 downto 0);
enable_out:out std_logic;
clk,reset,clear,enable:in std_logic
 
);
end entity;
 
architecture RTL of SOS is
--Filter Tworder component
component Tworder is
generic (WordWidth:integer;--:=16;--width signal of in/out
                        Bit_growth:integer;
                        M:integer;--:=16;--width word of coefs
                        Q:integer--:=15--Quantifer
                        );
 
port(
 
signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);
a0,a1,a2,b0,b1,b2: in std_logic_vector(M-1 downto 0);
signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);
clk,reset,clear,enable:in std_logic
 
);
end component;
 
--The fullregister component
component fullregister is
 
        generic
        (
                N: integer
        );
 
        port
        (
                clk               : in std_logic;
                reset_n   : in std_logic;
                enable    : in std_logic;
                clear             : in std_logic;
                d                 : in std_logic_vector(N-1 downto 0);
                q                 : out std_logic_vector(N-1 downto 0)
 
        );
end component;
--
type output_aux is array(NSECT downto 0) of std_logic_vector(WordWidth+Bit_growth-1 downto 0);
signal output,out_reg: output_aux;
 
type gain_out_t is array(NSECT downto 0) of std_logic_vector(M+WordWidth+Bit_growth-1 downto 0);
 
signal gain_out: gain_out_t;
 
 
constant Nh: integer :=(NSECT*M*6);
 
signal filter_coef:std_logic_vector(Nh-1 downto 0);
signal signal_output_aux:std_logic_vector(WordWidth+Bit_growth-1 downto 0);
--type aux_enable is array (0 to NSECT) of std_logic_vector(0 downto 0); 
type aux_enable is array (0 to 2*NSECT) of std_logic_vector(0 downto 0);
signal enable_aux:aux_enable;
begin
 
filter_coef<=h0;
myfilter:
        for k in NSECT-1 downto 0 generate
 
filter:Tworder
                generic map(
                                                WordWidth=>WordWidth,
                                                Bit_growth=>Bit_growth,
                                                M=>M,
                                                Q=>Q
                                                )
 
                port map(
                                        signal_input => out_reg(k),
                                        a2=>filter_coef((1*(M)+(k*(M)*6))-1 downto (k*(M)*6)),
                                        a1=>filter_coef((2*(M)+(k*(M)*6))-1 downto (1*(M)+(k*(M)*6))),
                                        a0=>filter_coef((3*(M)+(k*(M)*6))-1 downto (2*(M)+(k*(M)*6))),
                                        b2=>filter_coef((4*(M)+(k*(M)*6))-1 downto (3*(M)+(k*(M)*6))),
                                        b1=>filter_coef((5*(M)+(k*(M)*6))-1 downto (4*(M)+(k*(M)*6))),
                                        b0=>filter_coef((6*(M)+(k*(M)*6))-1 downto (5*(M)+(k*(M)*6))),
                                        signal_output => output(k),
                                        clk=>clk,
                                        reset=>reset,
                                        clear=>clear,
                                        enable=>enable_aux(k*2)(0)
                                        );
 
gain_out(k)<=std_logic_vector(signed(gain)*signed(output(k)));
 
        Reg_seg:fullregister
                                                        generic map(
                                                                                        N=>WordWidth+Bit_growth
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>'1',
                                                                                        clear=>clear,
                                                                                        d=>gain_out(k)(WordWidth+Bit_growth-1+Q downto Q),
                                                                                        q=>out_reg(k+1)
                                                                                        );
 
 
        end generate;
 
        myenables:
        for k in 0 to 2*NSECT-1 generate
 
 
        Reg_enables:fullregister
                                                        generic map(
                                                                                        N=>1
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>'1',
                                                                                        clear=>clear,
                                                                                        d=>enable_aux(k),
                                                                                        q=>enable_aux(k+1)
                                                                                        );
 
        end generate;
 
        out_reg(0)<=signal_input;
        enable_aux(0)(0)<=enable;
        enable_out<=enable_aux(to_integer((2*(unsigned(en_out))+2)))(0);
 
 
 
        signal_output_aux <=  gain_out(to_integer(unsigned(en_out)))(WordWidth+Bit_growth-1+Q downto Q);
 
        Reg_out:fullregister
                                                        generic map(
                                                                                        N=>WordWidth+Bit_growth
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>'1',
                                                                                        clear=>clear,
                                                                                        d=>signal_output_aux,
                                                                                        q=>signal_output
                                                                                        );
end architecture;

Line No.	Rev	Author	Line
1	5	parrado	`library ieee;`
2			`--library work;`
3			`use ieee.std_logic_1164.all;`
4			`use ieee.numeric_std.all;`
5			`--Structure SOS`
6			`entity SOS is`
7			`generic (WordWidth:integer;--width signal of in/out`
8			`Bit_growth:integer;`
9			`NSECT:integer;--Cant of sections`
10			`M:integer;--width word of coefs`
11			`Q:integer--Q--Quantifer`
12
13			`);`
14
15			`port(`
16
17			`signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);`
18			`h0: in std_logic_vector((NSECTM6)-1 downto 0);`
19			`gain: in std_logic_vector(M-1 downto 0);`
20			`signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);`
21			`en_out : in std_logic_vector(3 downto 0);`
22			`enable_out:out std_logic;`
23			`clk,reset,clear,enable:in std_logic`
24
25			`);`
26			`end entity;`
27
28			`architecture RTL of SOS is`
29			`--Filter Tworder component`
30			`component Tworder is`
31			`generic (WordWidth:integer;--:=16;--width signal of in/out`
32			`Bit_growth:integer;`
33			`M:integer;--:=16;--width word of coefs`
34			`Q:integer--:=15--Quantifer`
35			`);`
36
37			`port(`
38
39			`signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);`
40			`a0,a1,a2,b0,b1,b2: in std_logic_vector(M-1 downto 0);`
41			`signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);`
42			`clk,reset,clear,enable:in std_logic`
43
44			`);`
45			`end component;`
46
47			`--The fullregister component`
48			`component fullregister is`
49
50			`generic`
51			`(`
52			`N: integer`
53			`);`
54
55			`port`
56			`(`
57			`clk : in std_logic;`
58			`reset_n : in std_logic;`
59			`enable : in std_logic;`
60			`clear : in std_logic;`
61			`d : in std_logic_vector(N-1 downto 0);`
62			`q : out std_logic_vector(N-1 downto 0)`
63
64			`);`
65			`end component;`
66			`--`
67			`type output_aux is array(NSECT downto 0) of std_logic_vector(WordWidth+Bit_growth-1 downto 0);`
68			`signal output,out_reg: output_aux;`
69
70			`type gain_out_t is array(NSECT downto 0) of std_logic_vector(M+WordWidth+Bit_growth-1 downto 0);`
71
72			`signal gain_out: gain_out_t;`
73
74
75			`constant Nh: integer :=(NSECTM6);`
76
77			`signal filter_coef:std_logic_vector(Nh-1 downto 0);`
78			`signal signal_output_aux:std_logic_vector(WordWidth+Bit_growth-1 downto 0);`
79			`--type aux_enable is array (0 to NSECT) of std_logic_vector(0 downto 0);`
80			`type aux_enable is array (0 to 2*NSECT) of std_logic_vector(0 downto 0);`
81			`signal enable_aux:aux_enable;`
82			`begin`
83
84			`filter_coef<=h0;`
85			`myfilter:`
86			`for k in NSECT-1 downto 0 generate`
87
88			`filter:Tworder`
89			`generic map(`
90			`WordWidth=>WordWidth,`
91			`Bit_growth=>Bit_growth,`
92			`M=>M,`
93			`Q=>Q`
94			`)`
95
96			`port map(`
97			`signal_input => out_reg(k),`
98			`a2=>filter_coef((1(M)+(k(M)6))-1 downto (k(M)*6)),`
99			`a1=>filter_coef((2(M)+(k(M)6))-1 downto (1(M)+(k(M)6))),`
100			`a0=>filter_coef((3(M)+(k(M)6))-1 downto (2(M)+(k(M)6))),`
101			`b2=>filter_coef((4(M)+(k(M)6))-1 downto (3(M)+(k(M)6))),`
102			`b1=>filter_coef((5(M)+(k(M)6))-1 downto (4(M)+(k(M)6))),`
103			`b0=>filter_coef((6(M)+(k(M)6))-1 downto (5(M)+(k(M)6))),`
104			`signal_output => output(k),`
105			`clk=>clk,`
106			`reset=>reset,`
107			`clear=>clear,`
108			`enable=>enable_aux(k*2)(0)`
109			`);`
110
111			`gain_out(k)<=std_logic_vector(signed(gain)*signed(output(k)));`
112
113			`Reg_seg:fullregister`
114			`generic map(`
115			`N=>WordWidth+Bit_growth`
116			`)`
117			`port map (`
118			`clk=>clk,`
119			`reset_n=>reset,`
120			`enable=>'1',`
121			`clear=>clear,`
122			`d=>gain_out(k)(WordWidth+Bit_growth-1+Q downto Q),`
123			`q=>out_reg(k+1)`
124			`);`
125
126
127			`end generate;`
128
129			`myenables:`
130			`for k in 0 to 2*NSECT-1 generate`
131
132
133			`Reg_enables:fullregister`
134			`generic map(`
135			`N=>1`
136			`)`
137			`port map (`
138			`clk=>clk,`
139			`reset_n=>reset,`
140			`enable=>'1',`
141			`clear=>clear,`
142			`d=>enable_aux(k),`
143			`q=>enable_aux(k+1)`
144			`);`
145
146			`end generate;`
147
148			`out_reg(0)<=signal_input;`
149			`enable_aux(0)(0)<=enable;`
150			`enable_out<=enable_aux(to_integer((2*(unsigned(en_out))+2)))(0);`
151
152
153
154			`signal_output_aux <= gain_out(to_integer(unsigned(en_out)))(WordWidth+Bit_growth-1+Q downto Q);`
155
156			`Reg_out:fullregister`
157			`generic map(`
158			`N=>WordWidth+Bit_growth`
159			`)`
160			`port map (`
161			`clk=>clk,`
162			`reset_n=>reset,`
163			`enable=>'1',`
164			`clear=>clear,`
165			`d=>signal_output_aux,`
166			`q=>signal_output`
167			`);`
168			`end architecture;`

Browse

Tools

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_IIR/] [SOS.vhd] - Blame information for rev 7