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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_IIR/] [WB_SOS.vhd] - Blame information for rev 5

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1 5 parrado
library ieee;
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--library work;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity WB_SOS is
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generic (Filter_Width:integer:=16;--Filter width signals of in/out
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                        WB_Width:integer:=32;--WishBone width signal of in/out
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                        Bit_Growth:integer:=8;
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                        NSECT:integer:=6;--Cant of sections
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                        M:integer:=16;--width word of coefs
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                        Q:integer:=13;--Q--Quantifer
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                        Adress_wordwidth:integer:=32 ;
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                        Adr_bas:integer:=9;
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                        Reg_control:integer:=0;
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                        Reg_data:integer:=4;
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                        Reg_status:integer:=8;
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                        Reg_Nsec:integer:=12;
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                        Reg_gain: integer:=16;
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                        Reg_coef:integer:=20
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                        --Reg_coef:integer:=20
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                        --N_coef:integer:=42
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                        );
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port(
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DAT_I: in std_logic_vector(WB_Width-1 downto 0);
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DAT_O:out std_logic_vector(WB_Width-1 downto 0);
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ADR_I :in std_logic_vector(Adress_wordwidth-1 downto 0);
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STB_I,RST_I,CLK_I,WE_I: in std_logic;
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ACK_O: out   std_logic;
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clear:in std_logic
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);
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end entity;
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architecture RTL of WB_SOS is
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--Structure SOS
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component SOS is
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generic (WordWidth:integer;--width signal of in/out
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                        Bit_growth:integer;
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                        NSECT:integer;--Cant of sections
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                        M:integer;--width word of coefs
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                        Q:integer--Q--Quantifer
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                        );
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port(
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signal_input :in std_logic_vector(WordWidth+Bit_growth-1 downto 0);
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h0: in std_logic_vector((NSECT*M*6)-1 downto 0);
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gain: in std_logic_vector(M-1 downto 0);
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signal_output:out std_logic_vector(WordWidth+Bit_growth-1 downto 0);
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en_out : in std_logic_vector(3 downto 0);
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enable_out:out std_logic;
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clk,reset,clear,enable:in std_logic
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);  end component;
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--
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component interface_slave_iir is
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generic(
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Data_wordwidth: integer;
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Adress_wordwidth: integer;
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Adr_bas:integer;
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Reg_control:integer;
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Reg_data:integer;
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Reg_status:integer;
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Reg_coef:integer;
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Reg_gain:integer;
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Reg_Nsec:integer;
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NSECT:integer;
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--Offset_coef:integer;
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M:integer
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);
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port(
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 ACK_O: out   std_logic;--to MASTER
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 ADR_I: in    std_logic_vector( Adress_wordwidth-1 downto 0 );
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 DAT_I: in    std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER
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 sDAT_I: in    std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE
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 DAT_O: out   std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER
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 sDAT_O: out   std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE
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 en_out: out   std_logic_vector( 3 downto 0 );--to slave
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 STB_I: in    std_logic;--from MASTER
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 WE_I: in    std_logic;--from MASTER
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 Start: out    std_logic;--to SLAVE     
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 h0: out std_logic_vector( (NSECT*M*6)-1 downto 0 );--to SLAVE
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 gain: out std_logic_vector(M-1 downto 0);
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 enable_in: in std_logic;
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 clear,reset,clk: in std_logic
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 );
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end component;
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signal h0_aux:std_logic_vector((NSECT*M*6)-1 downto 0);
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signal gain_aux:std_logic_vector(M-1 downto 0);
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signal iir_data_in, iir_data_out:std_logic_vector(Filter_Width+Bit_Growth-1 downto 0);
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signal en_out_aux:std_logic_vector(3 downto 0);
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signal Start_aux, WE_O_aux,enable_aux:std_logic;
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signal sext:std_logic_vector(bit_growth-1 downto 0);
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begin
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sext<=(others=>iir_data_out(Filter_Width-1));
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sos_1:SOS
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generic map(WordWidth=>Filter_Width,--width signal of in/out
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                        Bit_growth=>Bit_Growth,
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                        NSECT=>NSECT,--Cant of sections
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                        M=>M,--width word of coefs
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                        Q=>Q--Quantifer
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                        )
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port map(
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signal_input=>iir_data_in((Filter_Width+Bit_Growth)-1 downto 0),
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--signal_input((WordWidth-(8*2))-1 downto 0)<=(others=>'0'),
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h0=>h0_aux,
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gain=>gain_aux,
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signal_output=>iir_data_out,
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en_out=>en_out_aux,
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enable_out=>enable_aux,
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clk=>CLK_I,
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reset=>RST_I,
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clear=>clear,
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enable=>start_aux
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);
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inteface:interface_slave_iir
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generic map(
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Data_wordwidth=>WB_Width,
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Adress_wordwidth=>Adress_wordwidth,
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Adr_bas=>Adr_bas,
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Reg_control=>Reg_control,
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Reg_data=>Reg_data,
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Reg_status=>Reg_status,
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Reg_coef=>Reg_coef,
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Reg_gain=>Reg_gain,
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Reg_Nsec=>Reg_Nsec,
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NSECT=>NSECT,
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--Offset_coef=>Offset_coef,
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M=>M
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)
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port map(
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 ACK_O=>ACK_O,
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 ADR_I=>ADR_I,
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 DAT_I=>DAT_I,
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 sDAT_I=>sext&iir_data_out,
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 DAT_O=>DAT_O,
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 sDAT_O((Filter_Width+Bit_Growth)-1 downto 0)=>iir_data_in,
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 en_out=>en_out_aux,
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 enable_in=>enable_aux,
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 STB_I=>STB_I,
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 WE_I=>WE_I,
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 Start=>Start_aux,
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 h0=>h0_aux,
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 gain=>gain_aux,
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 clear=>clear,
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 reset=>RST_I,
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 clk=>CLK_I
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 );
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end architecture;

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