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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_IIR/] [fullregister.vhd] - Blame information for rev 5

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1 5 parrado
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fullregister is
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        generic
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        (
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                N: integer
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        );
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        port
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        (
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                clk               : in std_logic;
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                reset_n   : in std_logic;
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                enable    : in std_logic;
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                clear             : in std_logic;
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                d                 : in std_logic_vector(N-1 downto 0);
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                q                 : out std_logic_vector(N-1 downto 0)
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        );
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end entity;
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architecture rtl of fullregister is
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begin
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        process (clk,reset_n,d,clear,enable)
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        begin
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        if reset_n = '0' then
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                                q <= (others=>'0');
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                elsif (rising_edge(clk)) then
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                        if enable = '1' then
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                                if clear='1' then
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                                   q <= (others=>'0');
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                                else
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                                        q<=d;
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                                end if;
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                end if;
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        end if;
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        end process;
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end rtl;

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