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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_IIR/] [interface_slave_iir.vhd] - Blame information for rev 5

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity interface_slave_iir is
generic(
 
Data_wordwidth: integer;
Adress_wordwidth: integer;
Adr_bas:integer;
Reg_control:integer;
Reg_data:integer;
Reg_status:integer;
Reg_coef:integer;
Reg_gain:integer;
Reg_Nsec:integer;
NSECT:integer;
M:integer
 
);
port(
 
 
 ACK_O: out   std_logic;--to MASTER
 ADR_I: in    std_logic_vector( Adress_wordwidth-1 downto 0 );
 DAT_I: in    std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER
 sDAT_I: in    std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE
 DAT_O: out   std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER
 sDAT_O: out   std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE
 en_out: out   std_logic_vector( 3 downto 0 );--to slave
 STB_I: in    std_logic;--from MASTER
 WE_I: in    std_logic;--from MASTER
 Start: out    std_logic;--to SLAVE     
 h0: out std_logic_vector( (NSECT*M*6)-1 downto 0 );--to SLAVE
 gain: out std_logic_vector(M-1 downto 0);
 enable_in: in std_logic;
 clear,reset,clk: in std_logic
 );
end entity;
 
architecture RTL of interface_slave_iir is
 
--The fullregister component
component fullregister is
 
        generic
        (
                N: integer
        );
 
        port
        (
                clk               : in std_logic;
                reset_n   : in std_logic;
                enable    : in std_logic;
                clear             : in std_logic;
                d                 : in std_logic_vector(N-1 downto 0);
                q                 : out std_logic_vector(N-1 downto 0)
 
        );
end component;
 
signal OUT_AUX, ZERO,ssDAT_O,RegsDAT_O:  std_logic_vector( Data_wordwidth-1 downto 0 );
signal rSTATUS_O,enable_in_aux:std_logic_vector( 0 downto 0 );
signal Clear_Status:std_logic;
signal enable_gain:std_logic;
signal EN_ZERO: std_logic_vector(3 downto 0);
 
type array_aux is array(6*NSECT downto 0) of std_logic_vector(M-1 downto 0);
signal h0_aux:array_aux;
 
signal gains: std_logic_vector(M-1 downto 0);
 
type array_aux1 is array(6*NSECT downto 0) of std_logic;
signal enables:array_aux1;
 
begin
        ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth));
 
        EN_ZERO<=std_logic_vector(to_unsigned(0,4));
        OUT_AUX<=DAT_I;
        ACK_O<=STB_I;
        enable_in_aux(0)<=enable_in;
        --DAT_O<=sDAT_I;
        coefficients:
                        for k in 6*NSECT-1 downto 0 generate
 
                                 enables(k)<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned((4*k)+Reg_coef,8))) else
                                                                        '0';
 
                                                coefs:fullregister
                                                        generic map(
                                                                                        N=>M
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>enables(k),
                                                                                        clear=>clear,
                                                                                        d=>OUT_AUX(M-1 downto 0),
                                                                                        q=>h0_aux(k)
                                                                                        );
                                                        h0((k+1)*M-1 downto k*M)<=std_logic_vector(h0_aux(k));
 
                        end generate;
 
 
 
        process(ADR_I,STB_I,WE_I,ZERO,EN_ZERO,OUT_AUX,rSTATUS_O)
        begin
 
                         if (WE_I='1' and STB_I='1') then--ESCRIBIR EN EL FILTRO
                                        case ADR_I(7 downto 0) is
 
                                                when std_logic_vector(to_unsigned(Reg_control,8)) =>    start<='1';
                                                                                                                                                                                                DAT_O<=ZERO;
                                                                                                                                                                                                Clear_Status<='0';
 
                                                when std_logic_vector(to_unsigned(Reg_status,8))=> Clear_Status<='1';
                                                                                                                                                                                                DAT_O<=ZERO;
                                                                                                                                                                                                start<='0';
                                                when OTHERS => start<='0';
                                                                                        DAT_O<=ZERO;
                                                                                        Clear_Status<='0';
                                           end case;
                         elsif (WE_I='0' and STB_I='1') then
                                        case ADR_I(7 downto 0) is --LEER EL FILTRO
                                                when std_logic_vector(to_unsigned(Reg_data,8)) =>
 
                                                                                                      DAT_O<=RegsDAT_O;
                                                                                                                                                                                                start<='0';
 
                                                                                                                                                                                                Clear_Status<='0';
 
                                                when std_logic_vector(to_unsigned(Reg_status,8)) =>     DAT_O(0)<=rSTATUS_O(0);
                                                                                                                                                                                                DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1);
                                                                                                                                                                                                start<='0';
 
                                                                                                                                                                                                Clear_Status<='0';
                                                when OTHERS => start<='0';
 
                                                                                        --DAT_O(M-1 downto 0)<= h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4);  
                                                                                        --DAT_O(Data_wordwidth-1 downto M)<=(others => h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4)(M-1) );  
 
                                                                                        --DAT_O<=ssDAT_O;
 
                                                                                        DAT_O(M-1 downto 0)<= gains;
                                                                                        DAT_O(Data_wordwidth-1 downto M)<=(others => gains(M-1) );
 
 
 
                                                                                        Clear_Status<='0';
                                        end case;
 
 
                         else
                                                start<='0';
                                                DAT_O<=ZERO;
                                                Clear_Status<='0';
                         end if;
 
        end process;
 
        process(ADR_I,STB_I,WE_I,OUT_AUX)
        begin
         if rising_edge(clk) then
 
                                 if (WE_I='1' and STB_I='1') then
                                                if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(reg_data,8)) then
                                                                ssDAT_O<=OUT_AUX;
                                                end if;
                                                if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_Nsec,8)) then
                                                                en_out<=OUT_AUX(3 downto 0);
                                                end if;
 
                                 end if;
         end if;
 
 
        end process;
 
                                                        Reg_Stat:fullregister
                                                        generic map(
                                                                                        N=>1
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>(enable_in or Clear_Status),
                                                                                        clear=>Clear_Status,
                                                                                        d=>enable_in_aux,
                                                                                        q=>rSTATUS_O
                                                                                        );
                                                        Reg_sDat_O:fullregister
                                                        generic map(
                                                                                        N=>Data_wordwidth
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>enable_in ,
                                                                                        clear=>clear,
                                                                                        d=>sDAT_I,
                                                                                        q=>RegsDAT_O
                                                                                        );
 
                                                                                        sDAT_O<=ssDAT_O;
 
                                                        --Registro para gain
 
                enable_gain<='1'  when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_gain,8))) else
                                                                        '0';
                        gainreg:fullregister
                                                        generic map(
                                                                                        N=>M
                                                                                        )
                                                        port map (
                                                                                        clk=>clk,
                                                                                        reset_n=>reset,
                                                                                        enable=>enable_gain,
                                                                                        clear=>clear,
                                                                                        d=>DAT_I(M-1 downto 0),
                                                                                        q=>gains
                                                                                        );
 
                                                                                        gain<=gains;
 
end architecture;
 
 
 

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[/] [wdsp/] [trunk/] [rtl/] [vhdl/] [WISHBONE_IIR/] [interface_slave_iir.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4
5			`entity interface_slave_iir is`
6			`generic(`
7
8			`Data_wordwidth: integer;`
9			`Adress_wordwidth: integer;`
10			`Adr_bas:integer;`
11			`Reg_control:integer;`
12			`Reg_data:integer;`
13			`Reg_status:integer;`
14			`Reg_coef:integer;`
15			`Reg_gain:integer;`
16			`Reg_Nsec:integer;`
17			`NSECT:integer;`
18			`M:integer`
19
20			`);`
21			`port(`
22
23
24			`ACK_O: out std_logic;--to MASTER`
25			`ADR_I: in std_logic_vector( Adress_wordwidth-1 downto 0 );`
26			`DAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER`
27			`sDAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE`
28			`DAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER`
29			`sDAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE`
30			`en_out: out std_logic_vector( 3 downto 0 );--to slave`
31			`STB_I: in std_logic;--from MASTER`
32			`WE_I: in std_logic;--from MASTER`
33			`Start: out std_logic;--to SLAVE`
34			`h0: out std_logic_vector( (NSECTM6)-1 downto 0 );--to SLAVE`
35			`gain: out std_logic_vector(M-1 downto 0);`
36			`enable_in: in std_logic;`
37			`clear,reset,clk: in std_logic`
38			`);`
39			`end entity;`
40
41			`architecture RTL of interface_slave_iir is`
42
43			`--The fullregister component`
44			`component fullregister is`
45
46			`generic`
47			`(`
48			`N: integer`
49			`);`
50
51			`port`
52			`(`
53			`clk : in std_logic;`
54			`reset_n : in std_logic;`
55			`enable : in std_logic;`
56			`clear : in std_logic;`
57			`d : in std_logic_vector(N-1 downto 0);`
58			`q : out std_logic_vector(N-1 downto 0)`
59
60			`);`
61			`end component;`
62
63			`signal OUT_AUX, ZERO,ssDAT_O,RegsDAT_O: std_logic_vector( Data_wordwidth-1 downto 0 );`
64			`signal rSTATUS_O,enable_in_aux:std_logic_vector( 0 downto 0 );`
65			`signal Clear_Status:std_logic;`
66			`signal enable_gain:std_logic;`
67			`signal EN_ZERO: std_logic_vector(3 downto 0);`
68
69			`type array_aux is array(6*NSECT downto 0) of std_logic_vector(M-1 downto 0);`
70			`signal h0_aux:array_aux;`
71
72			`signal gains: std_logic_vector(M-1 downto 0);`
73
74			`type array_aux1 is array(6*NSECT downto 0) of std_logic;`
75			`signal enables:array_aux1;`
76
77			`begin`
78			`ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth));`
79
80			`EN_ZERO<=std_logic_vector(to_unsigned(0,4));`
81			`OUT_AUX<=DAT_I;`
82			`ACK_O<=STB_I;`
83			`enable_in_aux(0)<=enable_in;`
84			`--DAT_O<=sDAT_I;`
85			`coefficients:`
86			`for k in 6*NSECT-1 downto 0 generate`
87
88			`enables(k)<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned((4*k)+Reg_coef,8))) else`
89			`'0';`
90
91			`coefs:fullregister`
92			`generic map(`
93			`N=>M`
94			`)`
95			`port map (`
96			`clk=>clk,`
97			`reset_n=>reset,`
98			`enable=>enables(k),`
99			`clear=>clear,`
100			`d=>OUT_AUX(M-1 downto 0),`
101			`q=>h0_aux(k)`
102			`);`
103			`h0((k+1)M-1 downto kM)<=std_logic_vector(h0_aux(k));`
104
105			`end generate;`
106
107
108
109			`process(ADR_I,STB_I,WE_I,ZERO,EN_ZERO,OUT_AUX,rSTATUS_O)`
110			`begin`
111
112			`if (WE_I='1' and STB_I='1') then--ESCRIBIR EN EL FILTRO`
113			`case ADR_I(7 downto 0) is`
114
115			`when std_logic_vector(to_unsigned(Reg_control,8)) => start<='1';`
116			`DAT_O<=ZERO;`
117			`Clear_Status<='0';`
118
119			`when std_logic_vector(to_unsigned(Reg_status,8))=> Clear_Status<='1';`
120			`DAT_O<=ZERO;`
121			`start<='0';`
122			`when OTHERS => start<='0';`
123			`DAT_O<=ZERO;`
124			`Clear_Status<='0';`
125			`end case;`
126			`elsif (WE_I='0' and STB_I='1') then`
127			`case ADR_I(7 downto 0) is --LEER EL FILTRO`
128			`when std_logic_vector(to_unsigned(Reg_data,8)) =>`
129
130			`DAT_O<=RegsDAT_O;`
131			`start<='0';`
132
133			`Clear_Status<='0';`
134
135			`when std_logic_vector(to_unsigned(Reg_status,8)) => DAT_O(0)<=rSTATUS_O(0);`
136			`DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1);`
137			`start<='0';`
138
139			`Clear_Status<='0';`
140			`when OTHERS => start<='0';`
141
142			`--DAT_O(M-1 downto 0)<= h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4);`
143			`--DAT_O(Data_wordwidth-1 downto M)<=(others => h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4)(M-1) );`
144
145			`--DAT_O<=ssDAT_O;`
146
147			`DAT_O(M-1 downto 0)<= gains;`
148			`DAT_O(Data_wordwidth-1 downto M)<=(others => gains(M-1) );`
149
150
151
152			`Clear_Status<='0';`
153			`end case;`
154
155
156			`else`
157			`start<='0';`
158			`DAT_O<=ZERO;`
159			`Clear_Status<='0';`
160			`end if;`
161
162			`end process;`
163
164			`process(ADR_I,STB_I,WE_I,OUT_AUX)`
165			`begin`
166			`if rising_edge(clk) then`
167
168			`if (WE_I='1' and STB_I='1') then`
169			`if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(reg_data,8)) then`
170			`ssDAT_O<=OUT_AUX;`
171			`end if;`
172			`if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_Nsec,8)) then`
173			`en_out<=OUT_AUX(3 downto 0);`
174			`end if;`
175
176			`end if;`
177			`end if;`
178
179
180			`end process;`
181
182			`Reg_Stat:fullregister`
183			`generic map(`
184			`N=>1`
185			`)`
186			`port map (`
187			`clk=>clk,`
188			`reset_n=>reset,`
189			`enable=>(enable_in or Clear_Status),`
190			`clear=>Clear_Status,`
191			`d=>enable_in_aux,`
192			`q=>rSTATUS_O`
193			`);`
194			`Reg_sDat_O:fullregister`
195			`generic map(`
196			`N=>Data_wordwidth`
197			`)`
198			`port map (`
199			`clk=>clk,`
200			`reset_n=>reset,`
201			`enable=>enable_in ,`
202			`clear=>clear,`
203			`d=>sDAT_I,`
204			`q=>RegsDAT_O`
205			`);`
206
207			`sDAT_O<=ssDAT_O;`
208
209			`--Registro para gain`
210
211			`enable_gain<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_gain,8))) else`
212			`'0';`
213			`gainreg:fullregister`
214			`generic map(`
215			`N=>M`
216			`)`
217			`port map (`
218			`clk=>clk,`
219			`reset_n=>reset,`
220			`enable=>enable_gain,`
221			`clear=>clear,`
222			`d=>DAT_I(M-1 downto 0),`
223			`q=>gains`
224			`);`
225
226			`gain<=gains;`
227
228			`end architecture;`
229
230
231