OpenCores
URL https://opencores.org/ocsvn/wdsp/wdsp/trunk

Subversion Repositories wdsp

[/] [wdsp/] [trunk/] [sw/] [matlab-scripts/] [fft/] [romgen_rc.m] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 parrado
function romgen_rc(rp,fp,tbits,rnum)
2
%   romgen_rc(rp,fp,tbits)
3
%        rp= number of points in this rom
4
%       fp= total number of points in the FFT.
5
%       tbits=width of the twiddle factor
6
%       rnum=rom number
7
%
8
%    This function creates the vhdl ROM file used to store the twiddle fac tors.
9
%       The  resulting file is named rom<rnum>.vhdl, where <rnum> is the value specifi ed in rp.
10
%       For exa mple: romgen_rc(16,64,10,1) would create a file called rom1.vhdl
11
%
12
%        This program uses:
13
%           frac2bin.m
14
%           writ ebin.m
15
 
16
%opening file for writing , (modified by Alex-Parrado)
17
fname=sprintf('../../../rtl/vhdl/WISHBONE_FFT/rom%d.vhd',rnum);
18
fprintf('creating file %s\n',fname);
19
fid=fopen(fname,'w');
20
%writing beginning stuff to the file
21
aw=log2(rp);
22
fprintf(fid,'-- Rom file for twiddle factors \n');
23
fprintf(fid ,'-- %s',fname);
24
fprintf(fid,' contains %d points of %d width \n',rp,tbits);
25
fprintf(fid,'--  for a %d point fft.\n\n',fp);
26
 
27
 
28
 
29
%Synchronous ROM modification by Alex-Parrado
30
fprintf(fid,'LIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;\nUSE ieee.std_logic_arith.ALL;\n');
31
fprintf(fid,'\n\nENTITY rom%d IS\n         GENERIC(\n',rnum);
32
fprintf(fid,'        data_width : integer :=%d;\n',tbits);
33
fprintf(fid,'        address_width : integer :=%d\n',aw);
34
fprintf (fid,'    );\n    PORT(\n');
35
fprintf(fid,'        clk :in std_logic;\n');
36
fprintf(fid,'        address :in std_logic_vector (%d      downto 0);\n',aw-1);
37
fprintf(fid ,'        datar : OUT std_logic_vector (data_width-1 DOWNTO 0) ;\n');
38
fprintf(fid,'        datai : OUT std_logic_vector (data_width-1 DOWNTO 0)\n    );\n');
39
fprintf(fid,'end rom%d;\n',rnum);
40
%begin writing architecture
41
fprintf(fid,'ARCHITECTURE behavior OF rom%d IS\n\n BEGIN\n\n',rnum);
42
fprintf(fid,'process (address,clk)\nbegin\n     if(rising_edge(clk)) then \n case address is\n');
43
ma=fp/rp*[2 1 3];
44
address=0;
45
for m=1:3
46
    for n=0:((rp/4)-1)
47
%          fprintf('%d %d %d %d %d',n,m,ma(m),rp,fp);
48
        expval=exp(-2*pi* j*n*ma(m)/fp);
49
      rscld=round(real(expval)*(2^(tbits-1)-1));
50
       iscld=round(imag(expval)*(2^(tbits-1)-1));
51
        bitvecr=frac2bin(rscld,tbits,0);
52
        bitveci=frac2bin(iscld,tbits,0);
53
         addrvec=dec2bin(address,aw);
54
        fprintf(fid,'        when "%s" => datar <= "',addrvec);
55
        writebin( fid,bitvecr);
56
      fprintf(fid,'";datai <= "');
57
         writebin(fid,bitveci);
58
          fprintf(fid,'"; --%d\n',n*ma(m));
59
         address=address+1;
60
    end
61
end
62
%filling out the remaining zeros
63
bitvecr=frac2bin((2^(tbits-1)-1),tbits,0);
64
bitveci=frac2bin(0,tbits,0);
65
for n=0:(rp/4-1)
66
    addrvec=dec2bin(address,aw);
67
    fprintf(fid,'           when "%s" => datar <= "',addrvec);
68
    writebin(fid,bitvecr);
69
    fprintf(fid,'";datai <= "');
70
    writebin(fid,bitveci);
71
    fprintf(fid,'"; --0\n');
72
    address=address+1;
73
end
74
 
75
fprintf(fid,'        when others => for i in data_width-1 downto 0 loop\n');
76
fprintf(fid,'            datar(i)<=''0'';datai(i)<=''0'';end loop;\n');
77
fprintf(fid,'    end case;\n\n');
78
fprintf(fid,'    end if;\n\n');
79
fprintf(fid,'end process;\nEND behavior;\n');
80
fclose(fid);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.