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[/] [wdsp/] [trunk/] [sw/] [support/] [mc.h] - Blame information for rev 5

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1 5 parrado
/* mc.h -- Simulation of Memory Controller
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         Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
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         This file is part of OpenRISC 1000 Architectural Simulator.
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         This program is free software; you can redistribute it and/or modify
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         it under the terms of the GNU General Public License as published by
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         the Free Software Foundation; either version 2 of the License, or
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         (at your option) any later version.
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         This program is distributed in the hope that it will be useful,
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         but WITHOUT ANY WARRANTY; without even the implied warranty of
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         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
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         GNU General Public License for more details.
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         You should have received a copy of the GNU General Public License
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         along with this program; if not, write to the Free Software
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         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Prototypes */
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#ifndef __MC_H
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#define __MC_H
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#define N_CE        (8)
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#define MC_CSR      (0x00)
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#define MC_POC      (0x04)
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#define MC_BA_MASK  (0x08)
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#define MC_CSC(i)   (0x10 + (i) * 8)
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#define MC_TMS(i)   (0x14 + (i) * 8)
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#define MC_ADDR_SPACE (MC_CSC(N_CE))
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/* POC register field definition */
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#define MC_POC_EN_BW_OFFSET     0
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#define MC_POC_EN_BW_WIDTH      2
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#define MC_POC_EN_MEMTYPE_OFFSET        2
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#define MC_POC_EN_MEMTYPE_WIDTH 2
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/* CSC register field definition */
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#define MC_CSC_EN_OFFSET        0
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#define MC_CSC_MEMTYPE_OFFSET   1
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#define MC_CSC_MEMTYPE_WIDTH    2
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#define MC_CSC_BW_OFFSET        4
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#define MC_CSC_BW_WIDTH         2
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#define MC_CSC_MS_OFFSET        6
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#define MC_CSC_MS_WIDTH         2
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#define MC_CSC_WP_OFFSET        8
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#define MC_CSC_BAS_OFFSET       9
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#define MC_CSC_KRO_OFFSET       10
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#define MC_CSC_PEN_OFFSET       11
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#define MC_CSC_SEL_OFFSET       16
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#define MC_CSC_SEL_WIDTH        8
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#define MC_CSC_MEMTYPE_SDRAM  0
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#define MC_CSC_MEMTYPE_SSRAM  1
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#define MC_CSC_MEMTYPE_ASYNC  2
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#define MC_CSC_MEMTYPE_SYNC   3
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#define MC_CSR_VALID            0xFF000703LU
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#define MC_POC_VALID            0x0000000FLU
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#define MC_BA_MASK_VALID        0x000000FFLU
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#define MC_CSC_VALID            0x00FF0FFFLU
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#define MC_TMS_SDRAM_VALID      0x0FFF83FFLU
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#define MC_TMS_SSRAM_VALID      0x00000000LU
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#define MC_TMS_ASYNC_VALID      0x03FFFFFFLU
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#define MC_TMS_SYNC_VALID       0x01FFFFFFLU
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#define MC_TMS_VALID            0xFFFFFFFFLU /* reg test compat. */
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/* TMS register field definition SDRAM */
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#define MC_TMS_SDRAM_TRFC_OFFSET        24
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#define MC_TMS_SDRAM_TRFC_WIDTH         4
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#define MC_TMS_SDRAM_TRP_OFFSET         20
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#define MC_TMS_SDRAM_TRP_WIDTH          4
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#define MC_TMS_SDRAM_TRCD_OFFSET        17
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#define MC_TMS_SDRAM_TRCD_WIDTH         4
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#define MC_TMS_SDRAM_TWR_OFFSET         15
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#define MC_TMS_SDRAM_TWR_WIDTH          2
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#define MC_TMS_SDRAM_WBL_OFFSET         9
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#define MC_TMS_SDRAM_OM_OFFSET          7
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#define MC_TMS_SDRAM_OM_WIDTH           2
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#define MC_TMS_SDRAM_CL_OFFSET          4
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#define MC_TMS_SDRAM_CL_WIDTH           3
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#define MC_TMS_SDRAM_BT_OFFSET          3
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#define MC_TMS_SDRAM_BL_OFFSET          0
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#define MC_TMS_SDRAM_BL_WIDTH           3
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/* TMS register field definition ASYNC */
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#define MC_TMS_ASYNC_TWWD_OFFSET        20
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#define MC_TMS_ASYNC_TWWD_WIDTH         6
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#define MC_TMS_ASYNC_TWD_OFFSET         16
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#define MC_TMS_ASYNC_TWD_WIDTH          4
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#define MC_TMS_ASYNC_TWPW_OFFSET        12
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#define MC_TMS_ASYNC_TWPW_WIDTH         4
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#define MC_TMS_ASYNC_TRDZ_OFFSET        8
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#define MC_TMS_ASYNC_TRDZ_WIDTH         4
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#define MC_TMS_ASYNC_TRDV_OFFSET        0
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#define MC_TMS_ASYNC_TRDV_WIDTH         8
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/* TMS register field definition SYNC  */
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#define MC_TMS_SYNC_TTO_OFFSET          16
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#define MC_TMS_SYNC_TTO_WIDTH           9
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#define MC_TMS_SYNC_TWR_OFFSET          12
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#define MC_TMS_SYNC_TWR_WIDTH           4
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#define MC_TMS_SYNC_TRDZ_OFFSET         8
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#define MC_TMS_SYNC_TRDZ_WIDTH          4
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#define MC_TMS_SYNC_TRDV_OFFSET         0
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#define MC_TMS_SYNC_TRDV_WIDTH          8
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#endif

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