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[/] [wdsp/] [trunk/] [sw/] [support/] [spr_defs.h] - Blame information for rev 5

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/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This file is also used by microkernel test bench. Among
others it is also used in assembly file(s). */
 
/* Definition of special-purpose registers (SPRs) */
 
#define MAX_GRPS (32)
#define MAX_SPRS_PER_GRP_BITS (11)
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
#define MAX_SPRS (0x10000)
 
/* Base addresses for the groups */
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
 
/* System control and status group */
#define SPR_VR          (SPRGROUP_SYS + 0)
#define SPR_UPR         (SPRGROUP_SYS + 1)
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
 
#if 0
/* Data MMU group */
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
 
/* Instruction MMU group */
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
#else
/* Data MMU group */
#define SPR_DMMUCR  (SPRGROUP_DMMU + 0)
#define SPR_DTLBMR_BASE(WAY)  (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
#define SPR_DTLBMR_LAST(WAY)  (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
#define SPR_DTLBTR_BASE(WAY)  (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
#define SPR_DTLBTR_LAST(WAY)  (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
 
/* Instruction MMU group */
#define SPR_IMMUCR  (SPRGROUP_IMMU + 0)
#define SPR_ITLBMR_BASE(WAY)  (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
#define SPR_ITLBMR_LAST(WAY)  (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
#define SPR_ITLBTR_BASE(WAY)  (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
#define SPR_ITLBTR_LAST(WAY)  (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
#endif
/* Data cache group */
#define SPR_DCCR        (SPRGROUP_DC + 0)
#define SPR_DCBPR       (SPRGROUP_DC + 1)
#define SPR_DCBFR       (SPRGROUP_DC + 2)
#define SPR_DCBIR       (SPRGROUP_DC + 3)
#define SPR_DCBWR       (SPRGROUP_DC + 4)
#define SPR_DCBLR       (SPRGROUP_DC + 5)
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
 
/* Instruction cache group */
#define SPR_ICCR        (SPRGROUP_IC + 0)
#define SPR_ICBPR       (SPRGROUP_IC + 1)
#define SPR_ICBIR       (SPRGROUP_IC + 2)
#define SPR_ICBLR       (SPRGROUP_IC + 3)
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
 
/* MAC group */
#define SPR_MACLO       (SPRGROUP_MAC + 1)
#define SPR_MACHI       (SPRGROUP_MAC + 2)
 
/* Debug group */
#define SPR_DVR(N)      (SPRGROUP_D + (N))
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
#define SPR_DMR1        (SPRGROUP_D + 16)
#define SPR_DMR2        (SPRGROUP_D + 17)
#define SPR_DWCR0       (SPRGROUP_D + 18)
#define SPR_DWCR1       (SPRGROUP_D + 19)
#define SPR_DSR         (SPRGROUP_D + 20)
#define SPR_DRR         (SPRGROUP_D + 21)
 
/* Performance counters group */
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
 
/* Power management group */
#define SPR_PMR (SPRGROUP_PM + 0)
 
/* PIC group */
#define SPR_PICMR (SPRGROUP_PIC + 0)
#define SPR_PICPR (SPRGROUP_PIC + 1)
#define SPR_PICSR (SPRGROUP_PIC + 2)
 
/* Tick Timer group */
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTCR (SPRGROUP_TT + 1)
 
/*
 * Bit definitions for the Version Register
 *
 */
#define SPR_VR_VER      0xffff0000  /* Processor version */
#define SPR_VR_REV      0x0000003f  /* Processor revision */
 
/*
 * Bit definitions for the Unit Present Register
 *
 */
#define SPR_UPR_UP      0x00000001  /* UPR present */
#define SPR_UPR_DCP     0x00000002  /* Data cache present */
#define SPR_UPR_ICP     0x00000004  /* Instruction cache present */
#define SPR_UPR_DMP     0x00000008  /* Data MMU present */
#define SPR_UPR_IMP     0x00000010  /* Instruction MMU present */
#define SPR_UPR_OB32P   0x00000020  /* ORBIS32 present */
#define SPR_UPR_OB64P   0x00000040  /* ORBIS64 present */
#define SPR_UPR_OF32P   0x00000080  /* ORFPX32 present */
#define SPR_UPR_OF64P   0x00000100  /* ORFPX64 present */
#define SPR_UPR_OV32P   0x00000200  /* ORVDX32 present */
#define SPR_UPR_OV64P   0x00000400  /* ORVDX64 present */
#define SPR_UPR_DUP     0x00000800  /* Debug unit present */
#define SPR_UPR_PCUP    0x00001000  /* Performance counters unit present */
#define SPR_UPR_PMP     0x00002000  /* Power management present */
#define SPR_UPR_PICP    0x00004000  /* PIC present */
#define SPR_UPR_TTP     0x00008000  /* Tick timer present */
#define SPR_UPR_SRP     0x00010000  /* Shadow registers present */
#define SPR_UPR_RES     0x00fe0000  /* ORVDX32 present */
#define SPR_UPR_CUST    0xff000000  /* Custom units */
 
/*
 * Bit definitions for the Supervision Register
 *
 */
#define SPR_SR_CID      0xf0000000  /* Context ID */
#define SPR_SR_FO       0x00008000  /* Fixed one */
#define SPR_SR_EPH      0x00004000  /* Exception Prefixi High */
#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */
#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */
#define SPR_SR_OV       0x00000800  /* Overflow flag */
#define SPR_SR_CY       0x00000400  /* Carry flag */
#define SPR_SR_F        0x00000200  /* Condition Flag */
#define SPR_SR_CE       0x00000100  /* CID Enable */
#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */
#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */
#define SPR_SR_DME      0x00000020  /* Data MMU Enable */
#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */
#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */
#define SPR_SR_IEE      0x00000004  /* Interrupt Exception Enable */
#define SPR_SR_TEE      0x00000002  /* Tick timer Exception Enable */
#define SPR_SR_SM       0x00000001  /* Supervisor Mode */
 
/*
 * Bit definitions for the Data MMU Control Register
 *
 */
#define SPR_DMMUCR_P2S  0x0000003e  /* Level 2 Page Size */
#define SPR_DMMUCR_P1S  0x000007c0  /* Level 1 Page Size */
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
 
/*
 * Bit definitions for the Instruction MMU Control Register
 *
 */
#define SPR_IMMUCR_P2S  0x0000003e  /* Level 2 Page Size */
#define SPR_IMMUCR_P1S  0x000007c0  /* Level 1 Page Size */
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
 
/*
 * Bit definitions for the Data TLB Match Register
 *
 */
#define SPR_DTLBMR_V    0x00000001  /* Valid */
#define SPR_DTLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_CID  0x0000003c  /* Context ID */
#define SPR_DTLBMR_LRU  0x000000c0  /* Least Recently Used */
#define SPR_DTLBMR_VPN  0xfffff000  /* Virtual Page Number */
 
/*
 * Bit definitions for the Data TLB Translate Register
 *
 */
#define SPR_DTLBTR_CC   0x00000001  /* Cache Coherency */
#define SPR_DTLBTR_CI   0x00000002  /* Cache Inhibit */
#define SPR_DTLBTR_WBC  0x00000004  /* Write-Back Cache */
#define SPR_DTLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
#define SPR_DTLBTR_A    0x00000010  /* Accessed */
#define SPR_DTLBTR_D    0x00000020  /* Dirty */
#define SPR_DTLBTR_URE  0x00000040  /* User Read Enable */
#define SPR_DTLBTR_UWE  0x00000080  /* User Write Enable */
#define SPR_DTLBTR_SRE  0x00000100  /* Supervisor Read Enable */
#define SPR_DTLBTR_SWE  0x00000200  /* Supervisor Write Enable */
#define SPR_DTLBTR_PPN  0xfffff000  /* Physical Page Number */
#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \
                          SPR_DTLBTR_UWE  | \
                          SPR_DTLBTR_SRE  | \
                          SPR_DTLBTR_SWE  )
/*
 * Bit definitions for the Instruction TLB Match Register
 *
 */
#define SPR_ITLBMR_V    0x00000001  /* Valid */
#define SPR_ITLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_CID  0x0000003c  /* Context ID */
#define SPR_ITLBMR_LRU  0x000000c0  /* Least Recently Used */
#define SPR_ITLBMR_VPN  0xfffff000  /* Virtual Page Number */
 
/*
 * Bit definitions for the Instruction TLB Translate Register
 *
 */
#define SPR_ITLBTR_CC   0x00000001  /* Cache Coherency */
#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */
#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */
#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
#define SPR_ITLBTR_A    0x00000010  /* Accessed */
#define SPR_ITLBTR_D    0x00000020  /* Dirty */
#define SPR_ITLBTR_SXE  0x00000040  /* User Read Enable */
#define SPR_ITLBTR_UXE  0x00000080  /* User Write Enable */
#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */
#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \
                          SPR_ITLBTR_UXE  )
 
 
/*
 * Bit definitions for Data Cache Control register
 *
 */
#define SPR_DCCR_EW     0x000000ff  /* Enable ways */
 
/*
 * Bit definitions for Insn Cache Control register
 *
 */
#define SPR_ICCR_EW     0x000000ff  /* Enable ways */
 
/*
 * Bit definitions for Debug Control registers
 *
 */
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
#define SPR_DCR_SC      0x00000010  /* Signed compare */
#define SPR_DCR_CT      0x000000e0  /* Compare to */
 
/* Bit results with SPR_DCR_CC mask */
#define SPR_DCR_CC_MASKED 0x00000000
#define SPR_DCR_CC_EQUAL  0x00000001
#define SPR_DCR_CC_LESS   0x00000002
#define SPR_DCR_CC_LESSE  0x00000003
#define SPR_DCR_CC_GREAT  0x00000004
#define SPR_DCR_CC_GREATE 0x00000005
#define SPR_DCR_CC_NEQUAL 0x00000006
 
/* Bit results with SPR_DCR_CT mask */
#define SPR_DCR_CT_DISABLED 0x00000000
#define SPR_DCR_CT_IFEA     0x00000020
#define SPR_DCR_CT_LEA      0x00000040
#define SPR_DCR_CT_SEA      0x00000060
#define SPR_DCR_CT_LD       0x00000080
#define SPR_DCR_CT_SD       0x000000a0
#define SPR_DCR_CT_LSEA     0x000000c0
 
/*
 * Bit definitions for Debug Mode 1 register
 *
 */
#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */
#define SPR_DMR1_CW1    0x0000000c  /* Chain watchpoint 1 */
#define SPR_DMR1_CW2    0x00000030  /* Chain watchpoint 2 */
#define SPR_DMR1_CW3    0x000000c0  /* Chain watchpoint 3 */
#define SPR_DMR1_CW4    0x00000300  /* Chain watchpoint 4 */
#define SPR_DMR1_CW5    0x00000c00  /* Chain watchpoint 5 */
#define SPR_DMR1_CW6    0x00003000  /* Chain watchpoint 6 */
#define SPR_DMR1_CW7    0x0000c000  /* Chain watchpoint 7 */
#define SPR_DMR1_CW8    0x00030000  /* Chain watchpoint 8 */
#define SPR_DMR1_CW9    0x000c0000  /* Chain watchpoint 9 */
#define SPR_DMR1_CW10   0x00300000  /* Chain watchpoint 10 */
#define SPR_DMR1_ST     0x00400000  /* Single-step trace*/
#define SPR_DMR1_BT     0x00800000  /* Branch trace */
#define SPR_DMR1_DXFW   0x01000000  /* Disable external force watchpoint */
 
/*
 * Bit definitions for Debug Mode 2 register
 *
 */
#define SPR_DMR2_WCE0   0x00000001  /* Watchpoint counter 0 enable */
#define SPR_DMR2_WCE1   0x00000002  /* Watchpoint counter 0 enable */
#define SPR_DMR2_AWTC   0x00001ffc  /* Assign watchpoints to counters */
#define SPR_DMR2_WGB    0x00ffe000  /* Watchpoints generating breakpoint */
 
/*
 * Bit definitions for Debug watchpoint counter registers
 *
 */
#define SPR_DWCR_COUNT  0x0000ffff  /* Count */
#define SPR_DWCR_MATCH  0xffff0000  /* Match */
 
/*
 * Bit definitions for Debug stop register
 *
 */
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
#define SPR_DSR_TTE     0x00000010  /* iTick Timer exception */
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
#define SPR_DSR_RE      0x00000400  /* Range exception */
#define SPR_DSR_SCE     0x00000800  /* System call exception */
#define SPR_DSR_SSE     0x00001000  /* Single Step Exception */
#define SPR_DSR_TE      0x00002000  /* Trap exception */
 
/*
 * Bit definitions for Debug reason register
 *
 */
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
#define SPR_DRR_RE      0x00000400  /* Range exception */
#define SPR_DRR_SCE     0x00000800  /* System call exception */
#define SPR_DRR_TE      0x00001000  /* Trap exception */
 
/*
 * Bit definitions for Performance counters mode registers
 *
 */
#define SPR_PCMR_CP     0x00000001  /* Counter present */
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
#define SPR_PCMR_LA     0x00000010  /* Load access event */
#define SPR_PCMR_SA     0x00000020  /* Store access event */
#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
 
/*
 * Bit definitions for the Power management register
 *
 */
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
 
/*
 * Bit definitions for PICMR
 *
 */
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
 
/*
 * Bit definitions for PICPR
 *
 */
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
 
/*
 * Bit definitions for PICSR
 *
 */
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
 
/*
 * Bit definitions for Tick Timer Control Register
 *
 */
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
#define SPR_TTMR_SR     0x80000000  /* Single run */
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
 
/*
 * l.nop constants
 *
 */
#define NOP_NOP         0x0000      /* Normal nop instruction */
#define NOP_EXIT        0x0001      /* End of simulation */
#define NOP_REPORT      0x0002      /* Simple report */
#define NOP_PRINTF      0x0003      /* Simprintf instruction */
#define NOP_REPORT_FIRST 0x0400     /* Report with number */
#define NOP_REPORT_LAST 0x03ff      /* Report with number */

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[/] [wdsp/] [trunk/] [sw/] [support/] [spr_defs.h] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	parrado	`/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* This file is also used by microkernel test bench. Among`
21			`others it is also used in assembly file(s). */`
22
23			`/* Definition of special-purpose registers (SPRs) */`
24
25			`#define MAX_GRPS (32)`
26			`#define MAX_SPRS_PER_GRP_BITS (11)`
27			`#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)`
28			`#define MAX_SPRS (0x10000)`
29
30			`/* Base addresses for the groups */`
31			`#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)`
32			`#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)`
33			`#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)`
34			`#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)`
35			`#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)`
36			`#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)`
37			`#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)`
38			`#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)`
39			`#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)`
40			`#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)`
41			`#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)`
42
43			`/* System control and status group */`
44			`#define SPR_VR (SPRGROUP_SYS + 0)`
45			`#define SPR_UPR (SPRGROUP_SYS + 1)`
46			`#define SPR_CPUCFGR (SPRGROUP_SYS + 2)`
47			`#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)`
48			`#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)`
49			`#define SPR_DCCFGR (SPRGROUP_SYS + 5)`
50			`#define SPR_ICCFGR (SPRGROUP_SYS + 6)`
51			`#define SPR_DCFGR (SPRGROUP_SYS + 7)`
52			`#define SPR_PCCFGR (SPRGROUP_SYS + 8)`
53			`#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */`
54			`#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */`
55			`#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */`
56			`#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */`
57			`#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */`
58			`#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)`
59			`#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)`
60			`#define SPR_ESR_BASE (SPRGROUP_SYS + 64)`
61			`#define SPR_ESR_LAST (SPRGROUP_SYS + 79)`
62
63			`#if 0`
64			`/* Data MMU group */`
65			`#define SPR_DMMUCR (SPRGROUP_DMMU + 0)`
66			`#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)`
67			`#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)`
68			`#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)`
69			`#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)`
70
71			`/* Instruction MMU group */`
72			`#define SPR_IMMUCR (SPRGROUP_IMMU + 0)`
73			`#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)`
74			`#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)`
75			`#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)`
76			`#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)`
77			`#else`
78			`/* Data MMU group */`
79			`#define SPR_DMMUCR (SPRGROUP_DMMU + 0)`
80			`#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)`
81			`#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)`
82			`#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)`
83			`#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)`
84
85			`/* Instruction MMU group */`
86			`#define SPR_IMMUCR (SPRGROUP_IMMU + 0)`
87			`#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)`
88			`#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)`
89			`#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)`
90			`#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)`
91			`#endif`
92			`/* Data cache group */`
93			`#define SPR_DCCR (SPRGROUP_DC + 0)`
94			`#define SPR_DCBPR (SPRGROUP_DC + 1)`
95			`#define SPR_DCBFR (SPRGROUP_DC + 2)`
96			`#define SPR_DCBIR (SPRGROUP_DC + 3)`
97			`#define SPR_DCBWR (SPRGROUP_DC + 4)`
98			`#define SPR_DCBLR (SPRGROUP_DC + 5)`
99			`#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)`
100			`#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)`
101
102			`/* Instruction cache group */`
103			`#define SPR_ICCR (SPRGROUP_IC + 0)`
104			`#define SPR_ICBPR (SPRGROUP_IC + 1)`
105			`#define SPR_ICBIR (SPRGROUP_IC + 2)`
106			`#define SPR_ICBLR (SPRGROUP_IC + 3)`
107			`#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)`
108			`#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)`
109
110			`/* MAC group */`
111			`#define SPR_MACLO (SPRGROUP_MAC + 1)`
112			`#define SPR_MACHI (SPRGROUP_MAC + 2)`
113
114			`/* Debug group */`
115			`#define SPR_DVR(N) (SPRGROUP_D + (N))`
116			`#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))`
117			`#define SPR_DMR1 (SPRGROUP_D + 16)`
118			`#define SPR_DMR2 (SPRGROUP_D + 17)`
119			`#define SPR_DWCR0 (SPRGROUP_D + 18)`
120			`#define SPR_DWCR1 (SPRGROUP_D + 19)`
121			`#define SPR_DSR (SPRGROUP_D + 20)`
122			`#define SPR_DRR (SPRGROUP_D + 21)`
123
124			`/* Performance counters group */`
125			`#define SPR_PCCR(N) (SPRGROUP_PC + (N))`
126			`#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))`
127
128			`/* Power management group */`
129			`#define SPR_PMR (SPRGROUP_PM + 0)`
130
131			`/* PIC group */`
132			`#define SPR_PICMR (SPRGROUP_PIC + 0)`
133			`#define SPR_PICPR (SPRGROUP_PIC + 1)`
134			`#define SPR_PICSR (SPRGROUP_PIC + 2)`
135
136			`/* Tick Timer group */`
137			`#define SPR_TTMR (SPRGROUP_TT + 0)`
138			`#define SPR_TTCR (SPRGROUP_TT + 1)`
139
140			`/*`
141			`* Bit definitions for the Version Register`
142			`*`
143			`*/`
144			`#define SPR_VR_VER 0xffff0000 /* Processor version */`
145			`#define SPR_VR_REV 0x0000003f /* Processor revision */`
146
147			`/*`
148			`* Bit definitions for the Unit Present Register`
149			`*`
150			`*/`
151			`#define SPR_UPR_UP 0x00000001 /* UPR present */`
152			`#define SPR_UPR_DCP 0x00000002 /* Data cache present */`
153			`#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */`
154			`#define SPR_UPR_DMP 0x00000008 /* Data MMU present */`
155			`#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */`
156			`#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */`
157			`#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */`
158			`#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */`
159			`#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */`
160			`#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */`
161			`#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */`
162			`#define SPR_UPR_DUP 0x00000800 /* Debug unit present */`
163			`#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */`
164			`#define SPR_UPR_PMP 0x00002000 /* Power management present */`
165			`#define SPR_UPR_PICP 0x00004000 /* PIC present */`
166			`#define SPR_UPR_TTP 0x00008000 /* Tick timer present */`
167			`#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */`
168			`#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */`
169			`#define SPR_UPR_CUST 0xff000000 /* Custom units */`
170
171			`/*`
172			`* Bit definitions for the Supervision Register`
173			`*`
174			`*/`
175			`#define SPR_SR_CID 0xf0000000 /* Context ID */`
176			`#define SPR_SR_FO 0x00008000 /* Fixed one */`
177			`#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */`
178			`#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */`
179			`#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */`
180			`#define SPR_SR_OV 0x00000800 /* Overflow flag */`
181			`#define SPR_SR_CY 0x00000400 /* Carry flag */`
182			`#define SPR_SR_F 0x00000200 /* Condition Flag */`
183			`#define SPR_SR_CE 0x00000100 /* CID Enable */`
184			`#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */`
185			`#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */`
186			`#define SPR_SR_DME 0x00000020 /* Data MMU Enable */`
187			`#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */`
188			`#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */`
189			`#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */`
190			`#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */`
191			`#define SPR_SR_SM 0x00000001 /* Supervisor Mode */`
192
193			`/*`
194			`* Bit definitions for the Data MMU Control Register`
195			`*`
196			`*/`
197			`#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */`
198			`#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */`
199			`#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */`
200			`#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */`
201
202			`/*`
203			`* Bit definitions for the Instruction MMU Control Register`
204			`*`
205			`*/`
206			`#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */`
207			`#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */`
208			`#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */`
209			`#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */`
210
211			`/*`
212			`* Bit definitions for the Data TLB Match Register`
213			`*`
214			`*/`
215			`#define SPR_DTLBMR_V 0x00000001 /* Valid */`
216			`#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */`
217			`#define SPR_DTLBMR_CID 0x0000003c /* Context ID */`
218			`#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */`
219			`#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */`
220
221			`/*`
222			`* Bit definitions for the Data TLB Translate Register`
223			`*`
224			`*/`
225			`#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */`
226			`#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */`
227			`#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */`
228			`#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */`
229			`#define SPR_DTLBTR_A 0x00000010 /* Accessed */`
230			`#define SPR_DTLBTR_D 0x00000020 /* Dirty */`
231			`#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */`
232			`#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */`
233			`#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */`
234			`#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */`
235			`#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */`
236			`#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE \| \`
237			`SPR_DTLBTR_UWE \| \`
238			`SPR_DTLBTR_SRE \| \`
239			`SPR_DTLBTR_SWE )`
240			`/*`
241			`* Bit definitions for the Instruction TLB Match Register`
242			`*`
243			`*/`
244			`#define SPR_ITLBMR_V 0x00000001 /* Valid */`
245			`#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */`
246			`#define SPR_ITLBMR_CID 0x0000003c /* Context ID */`
247			`#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */`
248			`#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */`
249
250			`/*`
251			`* Bit definitions for the Instruction TLB Translate Register`
252			`*`
253			`*/`
254			`#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */`
255			`#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */`
256			`#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */`
257			`#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */`
258			`#define SPR_ITLBTR_A 0x00000010 /* Accessed */`
259			`#define SPR_ITLBTR_D 0x00000020 /* Dirty */`
260			`#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */`
261			`#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */`
262			`#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */`
263			`#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE \| \`
264			`SPR_ITLBTR_UXE )`
265
266
267			`/*`
268			`* Bit definitions for Data Cache Control register`
269			`*`
270			`*/`
271			`#define SPR_DCCR_EW 0x000000ff /* Enable ways */`
272
273			`/*`
274			`* Bit definitions for Insn Cache Control register`
275			`*`
276			`*/`
277			`#define SPR_ICCR_EW 0x000000ff /* Enable ways */`
278
279			`/*`
280			`* Bit definitions for Debug Control registers`
281			`*`
282			`*/`
283			`#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */`
284			`#define SPR_DCR_CC 0x0000000e /* Compare condition */`
285			`#define SPR_DCR_SC 0x00000010 /* Signed compare */`
286			`#define SPR_DCR_CT 0x000000e0 /* Compare to */`
287
288			`/* Bit results with SPR_DCR_CC mask */`
289			`#define SPR_DCR_CC_MASKED 0x00000000`
290			`#define SPR_DCR_CC_EQUAL 0x00000001`
291			`#define SPR_DCR_CC_LESS 0x00000002`
292			`#define SPR_DCR_CC_LESSE 0x00000003`
293			`#define SPR_DCR_CC_GREAT 0x00000004`
294			`#define SPR_DCR_CC_GREATE 0x00000005`
295			`#define SPR_DCR_CC_NEQUAL 0x00000006`
296
297			`/* Bit results with SPR_DCR_CT mask */`
298			`#define SPR_DCR_CT_DISABLED 0x00000000`
299			`#define SPR_DCR_CT_IFEA 0x00000020`
300			`#define SPR_DCR_CT_LEA 0x00000040`
301			`#define SPR_DCR_CT_SEA 0x00000060`
302			`#define SPR_DCR_CT_LD 0x00000080`
303			`#define SPR_DCR_CT_SD 0x000000a0`
304			`#define SPR_DCR_CT_LSEA 0x000000c0`
305
306			`/*`
307			`* Bit definitions for Debug Mode 1 register`
308			`*`
309			`*/`
310			`#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */`
311			`#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */`
312			`#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */`
313			`#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */`
314			`#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */`
315			`#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */`
316			`#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */`
317			`#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */`
318			`#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */`
319			`#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */`
320			`#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */`
321			`#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/`
322			`#define SPR_DMR1_BT 0x00800000 /* Branch trace */`
323			`#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */`
324
325			`/*`
326			`* Bit definitions for Debug Mode 2 register`
327			`*`
328			`*/`
329			`#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */`
330			`#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */`
331			`#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */`
332			`#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */`
333
334			`/*`
335			`* Bit definitions for Debug watchpoint counter registers`
336			`*`
337			`*/`
338			`#define SPR_DWCR_COUNT 0x0000ffff /* Count */`
339			`#define SPR_DWCR_MATCH 0xffff0000 /* Match */`
340
341			`/*`
342			`* Bit definitions for Debug stop register`
343			`*`
344			`*/`
345			`#define SPR_DSR_RSTE 0x00000001 /* Reset exception */`
346			`#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */`
347			`#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */`
348			`#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */`
349			`#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */`
350			`#define SPR_DSR_AE 0x00000020 /* Alignment exception */`
351			`#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */`
352			`#define SPR_DSR_IE 0x00000080 /* Interrupt exception */`
353			`#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */`
354			`#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */`
355			`#define SPR_DSR_RE 0x00000400 /* Range exception */`
356			`#define SPR_DSR_SCE 0x00000800 /* System call exception */`
357			`#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */`
358			`#define SPR_DSR_TE 0x00002000 /* Trap exception */`
359
360			`/*`
361			`* Bit definitions for Debug reason register`
362			`*`
363			`*/`
364			`#define SPR_DRR_RSTE 0x00000001 /* Reset exception */`
365			`#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */`
366			`#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */`
367			`#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */`
368			`#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */`
369			`#define SPR_DRR_AE 0x00000020 /* Alignment exception */`
370			`#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */`
371			`#define SPR_DRR_IE 0x00000080 /* Interrupt exception */`
372			`#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */`
373			`#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */`
374			`#define SPR_DRR_RE 0x00000400 /* Range exception */`
375			`#define SPR_DRR_SCE 0x00000800 /* System call exception */`
376			`#define SPR_DRR_TE 0x00001000 /* Trap exception */`
377
378			`/*`
379			`* Bit definitions for Performance counters mode registers`
380			`*`
381			`*/`
382			`#define SPR_PCMR_CP 0x00000001 /* Counter present */`
383			`#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */`
384			`#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */`
385			`#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */`
386			`#define SPR_PCMR_LA 0x00000010 /* Load access event */`
387			`#define SPR_PCMR_SA 0x00000020 /* Store access event */`
388			`#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/`
389			`#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */`
390			`#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */`
391			`#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */`
392			`#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */`
393			`#define SPR_PCMR_BS 0x00000800 /* Branch stall event */`
394			`#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */`
395			`#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */`
396			`#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */`
397			`#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */`
398
399			`/*`
400			`* Bit definitions for the Power management register`
401			`*`
402			`*/`
403			`#define SPR_PMR_SDF 0x0000000f /* Slow down factor */`
404			`#define SPR_PMR_DME 0x00000010 /* Doze mode enable */`
405			`#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */`
406			`#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */`
407			`#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */`
408
409			`/*`
410			`* Bit definitions for PICMR`
411			`*`
412			`*/`
413			`#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */`
414
415			`/*`
416			`* Bit definitions for PICPR`
417			`*`
418			`*/`
419			`#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */`
420
421			`/*`
422			`* Bit definitions for PICSR`
423			`*`
424			`*/`
425			`#define SPR_PICSR_IS 0xffffffff /* Interrupt status */`
426
427			`/*`
428			`* Bit definitions for Tick Timer Control Register`
429			`*`
430			`*/`
431			`#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */`
432			`#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD`
433			`#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */`
434			`#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */`
435			`#define SPR_TTMR_RT 0x40000000 /* Restart tick */`
436			`#define SPR_TTMR_SR 0x80000000 /* Single run */`
437			`#define SPR_TTMR_CR 0xc0000000 /* Continuous run */`
438			`#define SPR_TTMR_M 0xc0000000 /* Tick mode */`
439
440			`/*`
441			`* l.nop constants`
442			`*`
443			`*/`
444			`#define NOP_NOP 0x0000 /* Normal nop instruction */`
445			`#define NOP_EXIT 0x0001 /* End of simulation */`
446			`#define NOP_REPORT 0x0002 /* Simple report */`
447			`#define NOP_PRINTF 0x0003 /* Simprintf instruction */`
448			`#define NOP_REPORT_FIRST 0x0400 /* Report with number */`
449			`#define NOP_REPORT_LAST 0x03ff /* Report with number */`