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//=======================================================================
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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// d3d_top.v
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//
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// Abstract:
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// DE0 RTL top module
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//
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// Author:
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// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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module d3d_top (
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// system
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input CLK,
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input RST,
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// SDRAM
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output DRAM_CLK,
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output [11:0] DRAM_ADDR,
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output [1:0] DRAM_BA,
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output DRAM_CAS_N,
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output DRAM_CKE,
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output DRAM_CS_N,
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inout[15:0] DRAM_DQ,
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output [1:0] DRAM_DQM,
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output DRAM_RAS_N,
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output DRAM_WE_N,
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input [3:0] SW,
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// USB
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//inout USB_DP,
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//inout USB_DN,
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// VGA
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output [3:0] VGA_R,
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output [3:0] VGA_G,
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output [3:0] VGA_B,
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output VGA_VS,
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output VGA_HS,
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// FLASH
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output DCLK,
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output SCE,
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output SDO,
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input DATA
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);
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d3d_system u0 (
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.clk_clk(CLK),
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.reset_reset_n(RST),
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.altpll_0_c1_clk(DRAM_CLK),
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.sdram0_wire_addr(DRAM_ADDR),
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.sdram0_wire_ba(DRAM_BA),
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.sdram0_wire_cas_n(DRAM_CAS_N),
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.sdram0_wire_cke(DRAM_CKE),
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.sdram0_wire_cs_n(DRAM_CS_N),
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.sdram0_wire_dq(DRAM_DQ),
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.sdram0_wire_dqm(DRAM_DQM),
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.sdram0_wire_ras_n(DRAM_RAS_N),
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.sdram0_wire_we_n(DRAM_WE_N),
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.altpll_0_areset_conduit_export(),
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.altpll_0_locked_conduit_export(),
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.altpll_0_phasedone_conduit_export(),
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.pio_0_in_export(SW[3:0]),
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//.usb_inout_dp(USB_DP),
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//.usb_inout_dn(USB_DN),
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.vga_out_cr(VGA_R),
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.vga_out_cg(VGA_G),
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.vga_out_cb(VGA_B),
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.vga_out_vsync_x(VGA_VS),
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.vga_out_hsync_x(VGA_HS),
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.epcs_flash_controller_0_external_dclk (DCLK),
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.epcs_flash_controller_0_external_sce (SCE),
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.epcs_flash_controller_0_external_sdo (SDO),
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.epcs_flash_controller_0_external_data0 (DATA)
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);
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endmodule
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