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[/] [wf3d/] [trunk/] [implement/] [rtl/] [fm_hvc/] [fm_cmn_ram.v] - Blame information for rev 2

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1 2 specular 
//=======================================================================
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// Project Monophony
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//   Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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//   fm_cmn_ram.v
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//
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// Abstract:
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//   Dualport RAM, this will be mapped to block ram
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//   with different clocks
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//
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// Author:
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//   Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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//  -Redistributions of source code must retain the above copyright notice,
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//   this list of conditions and the following disclaimer.
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//  -Redistributions in binary form must reproduce the above copyright notice,
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//   this list of conditions and the following disclaimer in the documentation
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//   and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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//=======================================================================
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//                        Project Polyphony
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//
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// File:
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//   fm_cmn_bram_02.v
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//
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// Abstract:
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//   Dualport RAM, this will be mapped onto block ram
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//   with different clocks
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//  Created:
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//    5 November 2008
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//======================================================================
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//
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// Copyright (c) 2013, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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//  -Redistributions of source code must retain the above copyright notice,
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//   this list of conditions and the following disclaimer.
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//  -Redistributions in binary form must reproduce the above copyright notice,
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//   this list of conditions and the following disclaimer in the documentation
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//   and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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// $Date: 2014-12-09 16:38:37 +0900 (Tue, 09 Dec 2014) $
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// $Rev: 14 $
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module fm_cmn_ram (
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    clka,
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    clkb,
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    wea,
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    addra,
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    addrb,
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    dia,
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    doa,
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    dob
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 );
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//////////////////////////////////
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// parameter
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//////////////////////////////////
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    parameter P_RAM_TYPE="TYPE_A";
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    parameter P_WIDTH = 32;
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    parameter P_RANGE = 2;
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    parameter P_DEPTH = 1 << P_RANGE;
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//////////////////////////////////
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// I/O port definition
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//////////////////////////////////
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    input                clka;
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    input                clkb;
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    input                wea;
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    input  [P_RANGE-1:0] addra;
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    input  [P_RANGE-1:0] addrb;
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    input  [P_WIDTH-1:0] dia;
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    output [P_WIDTH-1:0] doa;
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    output [P_WIDTH-1:0] dob;
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//////////////////////////////////
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// reg
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//////////////////////////////////
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    reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
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    reg [P_WIDTH-1:0] doa;
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    reg [P_WIDTH-1:0] dob;
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//////////////////////////////////
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// always
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//////////////////////////////////
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generate
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  if (P_RAM_TYPE=="TYPE_A") begin
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    always @(posedge clka) begin
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        if (wea) ram[addra] <= dia;
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    end
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    always @(posedge clkb) begin
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        dob <= ram[addrb];
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    end
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  end else begin
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    // port A: write-first
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    always @(posedge clka) begin
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        if (wea) begin
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            ram[addra] <= dia;
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            doa <= dia;
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        end else begin
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            doa <= ram[addra];
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        end
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    end
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    // port B: read-first
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    always @(posedge clkb) begin
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        dob <= ram[addrb];
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    end
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  end
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endgenerate
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endmodule

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